CN210129329U

CN210129329U - Numerical value comparator experimental apparatus for teaching

Info

Publication number: CN210129329U
Application number: CN201921036852.0U
Authority: CN
Inventors: 郭立强; 邹修明; 刘恋
Original assignee: Huaiyin Normal University
Current assignee: Huaiyin Normal University
Priority date: 2019-06-28
Filing date: 2019-06-28
Publication date: 2020-03-06
Anticipated expiration: 2029-06-28

Abstract

The utility model discloses a numerical comparator experimental device for teaching, which comprises a base, a panel and a banana head connecting wire; the panel integrates an AND gate logic unit, a NOR gate logic unit, a light emitting diode unit, a numerical value comparator unit, a logic level unit and a UPS unit. The device is flexible to use and easy to realize, a user can connect all the functional units into a 1-digit numerical comparator through the banana head connecting wire, and meanwhile, the functional test and demonstration can be carried out on the numerical comparator chip 74LS 85; the utility model discloses the unique jumbo size design that adopts makes it have good classroom demonstration function, is the interactive good experiment carrier of teachers and students, is convenient for use widely in colleges and universities classroom, has higher use value and wide application prospect.

Description

Numerical value comparator experimental apparatus for teaching

Technical Field

The utility model relates to the field of electronic technology, concretely relates to numerical value comparator experimental apparatus is used in teaching.

Background

The course is a necessary course for the electronic specialties such as electronic science and technology, electronic information engineering, communication engineering and the like in colleges and universities, and the professional basis of non-electronic specialties such as computer science and technology, Internet of things engineering, physics and the like, plays an important role in the whole talent training system, and lays a good foundation for the study of courses such as subsequent digital system design, singlechip, computer composition principle, integrated circuit design and the like. The numerical comparator, as a typical combinational logic circuit, plays an important role in the lesson of digital electronics technology foundation. The numerical value comparator has wide application in digital multimeters, temperature alarm circuits and timing comparison circuits. The point of knowledge about the numerical comparators and their circuit principles mainly consists of the design of the discrete-element numerical comparator and the use of the numerical comparator chip 74LS 85. Through the learning of the two key knowledge points, students can master the design method of the numerical value comparator and the test and the use of the numerical value comparator chip. The firmness of the knowledge of the numerical value comparator directly influences the learning of other subsequent combinational logic circuits.

At present, the experiment conditions of the electrical major of all colleges and universities are better, and the electrical major laboratories are equipped with digital circuits. However, in the existing course system of colleges and universities, the teaching mode of "theoretical course + experimental course" is adopted in the course, i.e. theoretical teaching is firstly performed in a multimedia classroom, and then experimental teaching is performed in a professional laboratory. The digital electronic technology foundation is a highly practical course, and if knowledge is infused in theoretical teaching, the learning effect of students is poor. If experimental demonstration is alternated in the teaching process, a plurality of problems exist. For example, the laboratory equipment in a professional laboratory is either a large laboratory platform with a large floor space or a relatively heavy laboratory box. For a large-scale experiment platform, the experiment platform cannot be moved to a common multimedia classroom for class demonstration. For the experimental box, because the volume is small, the functional units are many, which results in high element density, and the LED, the nixie tube, the switch and the like all use small-sized elements. During experiment demonstration, only the front two rows of students can clearly see the experiment, and the later students can hardly see the experiment process and results clearly. Meanwhile, the experiment box adopts 220V alternating current for power supply, and the mobility is poor. In addition, if the experiment box is to face the student to perform classroom demonstration, the flip cover on the experiment box can block the sight of the student, and the demonstration is very inconvenient.

For non-electronic specialties such as computer science and technology, Internet of things engineering and physics, the situation is also not optimistic. For colleges and universities with poor experimental conditions, because non-electric professionals do not have specialized laboratories, the experiments of the class usually adopt EDA simulation based on a computer to complete relevant experimental teaching. This is most common for computer-like specialties. Finally, the learning experience of students is poor, the teachers lack intuition in the explanation of knowledge points, and the teaching atmosphere is quite tedious.

According to questionnaires for college student course study by authorities such as Max, students often are most interested in lesson modes with strong interactivity and courses of experimental demonstration, and are most concentrated in energy when attending lessons. But often cannot raise the spirit of PPT infusion type teaching. According to the problem that meets in this kind of course of the digital electronics technology basis gives lessons in-process, can't use hardware equipment to conveniently carry out numerical value comparator circuit function demonstration on theoretical class promptly, the utility model provides a numerical value comparator experimental apparatus convenient to classroom demonstration for build discrete component numerical value comparator and carry out functional test to 74LS85 chip. The device both is the teaching instrument of numerical value comparator circuit experiment demonstration, also is the good carrier of carrying on teachers and students 'interaction simultaneously, plays positive exemplary effect to the classroom teaching, can improve student's classroom attention and study initiative, has good popularization and use prospect.

Disclosure of Invention

To the problem that exists among the prior art, improve the quality of giving lessons in class, the utility model provides a numerical value comparator experimental apparatus is used in teaching, the utility model discloses the technical scheme who takes as follows:

a numerical comparator experimental device for teaching comprises a base, a panel and a banana head connecting wire; the panel integrates an AND gate logic unit, a NOR gate logic unit, a light emitting diode unit, a numerical value comparator unit, a logic level unit and a UPS unit;

the AND gate logic unit is composed of a CD4081 chip, a chip adapter plate and a banana head socket, the CD4081 chip is fixed on the panel through the chip adapter plate, a power supply port and a ground port of the CD4081 chip are respectively connected with a power supply output port and a ground port of the UPS unit, and an AND logic input end and an AND logic output end of the CD4081 chip are connected with the banana head socket;

the NOR gate logic unit is composed of a CD4001 chip, a chip adapter plate and a banana head socket, the CD4001 chip is fixed on the panel through the chip adapter plate, a power supply port and a ground port of the CD4001 chip are respectively connected with a power supply output port and a ground port of the UPS unit, and a NOR logic input and output end of the CD4001 chip are connected with the banana head socket;

the NOT gate logic unit is composed of a CD4069 chip, a chip adapter plate and a banana head socket, the CD4069 chip is fixed on the panel through the chip adapter plate, a power supply port and a ground port of the CD4069 chip are respectively connected with a power supply output port and a ground port of the UPS unit, and a 'non-logic' input end and an 'non-logic' output end of the CD4069 chip are connected with the banana head socket;

the light-emitting diode unit consists of a light-emitting diode, a resistor and a banana head socket, the cathode of the light-emitting diode is connected with the ground port of the UPS unit through the resistor, and the anode of the light-emitting diode is connected with the banana head socket;

the numerical value comparator unit consists of a 74LS85 chip, a locking seat and a banana head socket, and the 74LS85 chip is fixed on the panel through the locking seat;

the logic level unit is composed of a single-pole double-throw switch, a banana head socket and a resistor divider, wherein the input end of one side of the single-pole double-throw switch is connected with the ground port of the UPS unit, the input end of the other side of the single-pole double-throw switch is connected with the power output port of the UPS unit through the resistor divider, and the middle output end of the single-pole double-throw switch is connected with the banana head socket;

the UPS unit is by 5V supply socket, UPS power module, the lithium cell, switch and banana head socket constitute, 5V supply socket's the positive pole and the negative pole link to each other with UPS power module's power input port, the positive pole and the negative pole of lithium cell link to each other with UPS power module's battery port, UPS power module's the positive output of passing through switch links to each other with banana head socket, for whole experimental apparatus power supply, UPS power module's the output negative pole links to each other with banana head socket, as whole experimental apparatus's earthing terminal.

Preferably, the base is a cuboid structure formed by single-layer acrylic plates, and the panel is a single-layer acrylic plate and is fixed on the base through long-rod screws; the base and the panel are 60 cm long and 45 cm wide.

Preferably, the chip adapter plate is composed of a screw hole site, a chip socket, a printed wire and a bonding pad, the bonding pad is connected with the banana head socket through the wire, and the chip adapter plate is fixed on the panel through screws.

Preferably, the diameter of the light emitting diode is 1 cm, and the light emitting color is red.

Preferably, the lithium battery is a 18650 lithium battery.

Preferably, each there is a plug at banana head connecting wire both ends, the plug comprises plastics handle and metal lotus flower head, the diameter of metal lotus flower head with the hole diameter of banana head socket is 2 millimeters, the top of plastics handle has the jack that the internal diameter is 2 millimeters.

Compared with the prior art, the utility model discloses following beneficial effect has:

1. the utility model discloses can test the model for the numerical value comparator chip of 74LS85, can also build simultaneously based on "AND gate", "NOR gate" and "NOT gate" 1 bit numerical value comparator, the demonstration through this experimental apparatus makes the student master the basic principle of numerical value comparator, is familiar with the pin function of 74LS85 chip, masters combinational logic circuit's design method, has simple, easily understood and the characteristics that the commonality is strong.

2. The utility model discloses a functional unit is abundant, easily realizes that user's accessible banana head connecting wire is connected each functional unit and is accomplished the test of numerical value comparator chip and putting up of discrete component numerical value comparator circuit, uses in a flexible way.

3. The utility model discloses a base and panel all adopt the preparation of inferior gram force board, have weatherability and acid and alkali resistance good, and the impact resistance is strong, easy clean and insulating advantage such as good to the cost is low, the sexual valence relative altitude.

4. The utility model discloses the middle base is 60 centimetres with the panel length, and the width is 45 centimetres, and each unit all prints the jumbo size map that has corresponding chip or component on the panel, and emitting diode's diameter is 1 centimetre, and this kind of unique jumbo size design makes the utility model discloses have good classroom demonstration function, be the interactive good experiment carrier of teachers and students, conveniently use widely on colleges and universities classroom, have wide use value and application prospect.

Drawings

Fig. 1 is a schematic view of a base of the present invention;

FIG. 2 is a structural diagram of the middle panel of the present invention;

FIG. 3 is a circuit diagram of each unit on the middle panel of the present invention;

FIG. 4 is a schematic view of a chip adapter plate according to the present invention;

FIG. 5 is a circuit diagram of a 1-bit digital comparator according to the present invention;

fig. 6 is a circuit diagram of the 74LS85 chip under test in the present invention.

Reference numerals: 101-AND gate logic unit, 102-NOR gate logic unit, 103-NOR gate logic unit, 104-light emitting diode unit, 105-numerical value comparator unit, 106-logic level unit, 107-UPS unit, 201-chip adapter plate, 202-screw hole position, 203-chip socket, 204-printed wire and 205-bonding pad.

Detailed Description

In order to facilitate the technical solution of the present invention to be understood by the skilled person, the technical solution of the present invention will be further described with reference to the accompanying drawings.

A numerical comparator experimental device for teaching comprises a base, a panel and a banana head connecting line. The structure schematic diagram of the base is shown in fig. 1, the base is a box-shaped cuboid made of an acrylic plate with the thickness of 3 mm, the length of the cuboid is 60 cm, the width of the cuboid is 45 cm, and the height of the cuboid is 5 cm. The structure diagram of the panel is shown in fig. 2, and is also made of an acrylic plate with the thickness of 3 mm, 4 corners of the panel and the base are respectively provided with a screw hole position which is aligned up and down, so that the panel is conveniently fixed on the base through long rod screws. The electronic circuit of protection panel back is walked the line for an important effect of base, and another effect is convenient for openly face the student with this experimental apparatus and stand on the podium, makes things convenient for the student to observe the connection and the state of circuit.

As shown in fig. 2, the panel integrates an and gate logic unit 101, a nor gate logic unit 102, a not gate logic unit 103, a light emitting diode unit 104, a numerical comparator unit 105, a logic level unit 106, and a UPS unit 107.

The AND gate logic unit 101 is composed of a CD4081 chip, a chip adapter board 201 and a banana head socket, the CD4081 chip is fixed on the panel through the chip adapter board 201, a power port and a ground port of the CD4081 chip are respectively connected with a power output port and a ground port of the UPS unit 107 and supply power for the chip, and the 'and logic' input and output ends of the CD4081 chip are connected with the banana head socket. As shown in the and gate logic unit 101 of fig. 2, the banana head sockets a1 and B1 are connected to the input terminals of the first and gate, and the banana head socket Y1 is connected to the output terminals of the first and gate. By analogy, two input ends and one output end of the other three groups of AND gates are respectively connected with the banana head sockets "A2, B2, Y2", "A3, B3, Y3" and "A4, B4 and Y4". The circuit diagram of the and logic unit 101 of fig. 2 is shown as a sub-circuit diagram of fig. 3, labeled 101, and is drawn using the software of Proteus, which defaults to the chip automatically connecting power and ground, so that both

pins

7 and 14 of the chip are omitted (i.e., there are no pins in the circuit diagram). As shown in the sub-circuit diagram of fig. 3,

reference numeral

101, 4 independent and gates are respectively connected by "U1: a' to "U1: the D mark, the number on the input and output pins of the 4 AND gates represents the pin number of the CD4081 chip.

The main function of the and gate logic unit 101 is to construct a 1-bit digital comparator together with the nor gate logic unit 102 and the not gate logic unit 103, which will be described in detail in the following embodiments.

The nor gate logic unit 102 is composed of a CD4001 chip, a chip adapter plate 201 and a banana head socket, the CD4001 chip is fixed on the panel through the chip adapter plate 201, a power port and a ground port of the CD4001 chip are respectively connected with a power output port and a ground port of the UPS unit 107 and supply power to the chip, and a nor logic input and output end of the CD4001 chip are connected with the banana head socket. There are four independent sets of two-input nor gates inside the CD4001 chip, and as shown in the nor gate logic unit 102 of fig. 2, banana head sockets a1 and B1 are connected to the inputs of the first set of nor gates, and banana head socket Y1 is connected to the outputs of the first set of nor gates. By analogy, two input ends and one output end of the other three groups of NOR gates are respectively connected with banana head sockets "A2, B2, Y2", "A3, B3, Y3" and "A4, B4 and Y4". The circuit diagram of nor gate logic 102 of fig. 2 is shown as a sub-circuit diagram 102 of fig. 3, which is drawn using the software of Proteus, which defaults to automatically connecting power and ground to the chip, so that both

pins

reference numeral

102, 4 independent nor gates are respectively connected by "U2: a' to "U2: and D' mark, the numbers on the input and output pins of the 4 NOR gates represent the pin numbers of the CD4001 chip.

The main function of the nor logic unit 102 is to construct a 1-bit digital comparator together with the and logic unit 101 and the not logic unit 103, which will be described in detail in the following embodiments.

The NOT gate logic unit 103 is composed of a CD4069 chip, a chip adapter plate 201 and a banana head socket, the CD4069 chip is fixed on the panel through the chip adapter plate 201, a power port and a ground port of the CD4069 chip are respectively connected with a power output port and a ground port of the UPS unit 107 and supply power for the chip, and a 'non-logic' input end and an 'non-logic' output end of the CD4069 chip are connected with the banana head socket. The CD4069 chip has six independent sets of not gates inside, and as shown in the not gate logic unit 103 of fig. 2, the banana head socket a1 is connected to the input terminal of the first set of not gates, and the banana head socket Y1 is connected to the output terminal of the first set of not gates. By analogy, the input ends and the output ends of the other five groups of NOT gates are respectively connected with banana head sockets "A2, Y2", "A3, Y3", "A4, Y4", "A5, Y5" and "A6 and Y6". The circuit diagram of the not-gate logic unit 103 in fig. 2 is shown as a sub-circuit diagram of fig. 3, which is labeled 103, and is drawn by the software of Proteus, which defaults to the chip automatically connecting to power and ground, so that both

pins

reference numeral

103, 6 independent not gates are respectively connected by "U3: a' to "U3: the F "mark, the numbers on the 6 not gate input and output pins represent the pin numbers of the CD4069 chip.

The main function of the not gate logic unit 103 is to build a 1-bit digital comparator together with the and gate logic unit 101 and the nor gate logic unit 102, which will be described in detail in the following embodiments.

The led unit 104 is composed of 8 red leds with a diameter of 1 cm and a banana head socket, as shown in fig. 2. The purpose of selecting the large-diameter light-emitting diode is to facilitate experimental demonstration and observation of students. The light emitting diode is fixed on the corresponding area of the panel through an LED lamp holder with the diameter of an inner hole of 1 cm, and the LED lamp holder is commercially available. When the LED lamp holder is installed, holes are formed in the corresponding area of the panel according to the actual size of the outer diameter of the lamp holder, and then the LED lamp holder is inserted into the panel and fixed to the back of the panel through nuts. In this embodiment, a lamp base with an outer diameter of 1.35 cm is used. The adjacent center spacing of 8 lamp holders is required to be appropriate, so that holes are convenient to open, and in the embodiment, the center spacing of the adjacent lamp holders is 3.5 centimeters. A round hole with the diameter of 4 mm is formed at a position 5 cm below each lamp holder and is used for mounting the banana head socket. Next, the red led is placed in the lamp holder, the cathode of the led is connected to the ground port of the UPS unit 107 through a resistor with a resistance of 10K Ω (specifically, through wire bonding), and the anode of the led is connected to the banana head socket. As shown in the LED unit 104 in fig. 2, "LED 1" to "LED 8" represent 8 red LEDs with a diameter of 1 cm, and anodes of the 8 LEDs are respectively connected to the banana head sockets "L1" to "L8", and a specific circuit is shown in a sub-circuit diagram of reference numeral 104 in fig. 3, in which element numerals "D1" to "D8" represent the aforementioned 8 LEDs, respectively.

The main function of the led unit 104 is to display the result of the numerical comparison. In order to verify whether the mounted leds are successful, one plug of the banana head connecting line may be inserted into the power port of the UPS unit 107 in fig. 2, that is, into the banana head socket marked with "V1", and the other plug of the banana head connecting line is inserted into the banana head sockets marked with "L1", "L2", … "and" L8 "in the led unit 104 in sequence, and the power switch is pressed to see whether the corresponding leds are lit, so as to verify whether the led mounting process is problematic.

As shown in fig. 4, the chip interposer 201 has screw holes 202 (distributed at 4 corners of the chip interposer 201), a chip socket 203, printed wires 204 and pads 205. The chip adapter plate 201 is used for fixing the integrated logic gate chip, and each bonding pad and the chip pin form good electrical communication, so that the chip adapter plate can be conveniently connected with a corresponding banana head socket. In this embodiment, specifically taking the and logic unit 101 as an example, two rows of 14 circular holes with a diameter of 1 mm are formed in the and logic unit 101 on the front surface of the panel, the center distance between two adjacent circular holes in the horizontal direction is 2.5 mm, and the center distance between two adjacent circular holes in the vertical direction is 30 mm; inserting a CD4081 chip into the chip socket 203 (as shown in FIG. 4, note that the chip notch faces to the left, at this time, the bottom row is from the left to the right, the 1 st pad is connected to the 1 pin of the chip, the 2 nd pad is connected to the 2 pin of the chip, and so on to the 7 th pad; the pad right above the 7 th pad is the 8 th pad, at this time, the pads are from the right to the left, the 9 th pad in turn, and up to the 14 th pad at the upper left corner); and selecting the 1 st hole site at the lower left corner, enabling the lead to pass through the acrylic panel and the 1 st bonding pad at the lower left corner of the chip adapter plate 201 from the back of the panel, welding the lead on the bonding pad, welding the other end of the lead on the banana head socket A1 according to the sub circuit diagram marked with the reference number 101 in the figure 3, and so on, except the 7 th bonding pad and the 14 th bonding pad, welding the rest bonding pads on the corresponding banana head sockets. The 7 pin of the CD4081 chip is ground, so the 7 th pad wire is soldered to the ground port of the UPS unit 107 at the back of the panel. Similarly, the 14 th pin of the chip is the power supply terminal, so the 14 th pad is soldered to the power output port of the UPS unit 107 on the back of the panel. After all the wires are welded, the chip adapter plate is fixed in the area shown by the AND logic unit 101 on the front surface of the panel by 4 screws. The implementation steps of fixing the CD4001 and the CD4069 chips by using the chip adapter board in the nor logic unit 102 and the nor logic unit 103 are similar, and are not described herein again.

The numerical comparator unit 105 is composed of a 74LS85 chip, a locking seat and a banana head socket, and the 74LS85 chip is fixed on the panel through the locking seat. In this embodiment, a wide locking socket with 16 pins is used, the diameter of the pin is 0.8 mm, the length of the pin is 1 cm, and the locking socket is commercially available. Two rows of 16 round holes with the diameter of 1 mm are formed in the middle area of the numerical comparator unit 105 on the front surface of the panel, the central distance between two adjacent round holes in the horizontal direction is 2.5 mm, and the central distance between two adjacent round holes in the vertical direction is 10 mm. And (4) coating 101 glue on the bottom of the locking seat, inserting the locking seat into the two rows of round holes, and fixing the locking seat and the panel together through the 101 glue. Adopt the form of flying wire to link to each other 16 pins of locking seat and the banana head socket that corresponds at the back of panel, concrete circuit is as shown by the sub-circuit diagram that the reference numeral is 105 in figure 3, the pin of the 1 st hole site in the locking seat lower left corner links to each other with the banana head socket that the reference numeral is "1" on the panel, the pin of the 2 nd hole site in the lower left corner links to each other with the banana head socket that the reference numeral is "2" on the panel, so on, according to the anticlockwise, the pin of the 1 st hole site in the locking seat upper left corner links to each other with the banana head socket that the reference numeral is "16" on the panel.

The circuit of the numerical comparator unit 105 is shown in the sub-circuit diagram of reference numeral 105 in fig. 3, where "CHIP LOCK" represents a LOCK socket having 16 pins, and the 16 pins are respectively connected to terminals of reference numerals "1", "2", … "and" 16 "(these terminals represent banana head sockets in the numerical comparator unit 105). Insertion of the 74LS85 chip into the locking socket results in electrical connection of the chip pins to the corresponding banana head sockets on the value comparator unit 105.

As shown in fig. 2, an enlarged version of the 74LS85 chip schematic and pin identification text is printed in the middle of the area of the numerical comparator unit 105. Of a chip

Comparing the input ports for the values, wherein

And

the pins are the 1 st bits of two sets of four-bit binary numbers to be compared, respectively, identified by the letters "A0" and "B0", respectively. Similarly, of the chip

And

a pin,

And

a pin,

And

the pins are respectively the 2 nd bit, the 3 rd bit and the 4 th bit of two groups of four-bit binary numbers to be compared. Of a chip

And

the pins are all cascade input ends respectively using' I_A＜B”、“I_A＝B"and" I_A＞B"to identify. Of a chip

And

the pins are all comparison result output ends, and are respectively O_A＞B”、“O_A＝BAnd O_A＜B"to identify. If the two sets of four-digit binary numbers "A0A 1A 2A 3" to be compared are greater than "B0B 1B 2B 3", the chip is then calibrated

The pin outputs a high level of voltage,

and

the pins all output low level; if "A0A 1A 2A 3" is equal to "B0B 1B 2B 3", the chip is made

The pin outputs a high level of voltage,

and

the pins all output low level; if "A0A 1A 2A 3" is smaller than "B0B 1B 2B 3", the chip is made of

The pin outputs a high level of voltage,

and

the pins all output a low level. Of a chip

The pin is a ground port and is identified by the letter "GND"; of a chip

The pin is a power port, identified by the letter "VCC". The chip pin identification and the banana head socket in the area of the numerical value comparator unit 105 on the panel are in one-to-one correspondence, that is to say

Corresponding to the banana head socket numbered "1",

corresponding to the banana head socket labeled "2", …,

corresponding to the banana head socket numbered "16" which facilitates the electrical connection. The chip schematic diagram and the pin identification can be printed on the acrylic plate by adopting a UV printing mode (entrusting the relevant UV printing business to customize). Through the design, the functions of the pins of the 74LS85 chip are clearly visible, and teaching demonstration is facilitated.

The main function of the numerical comparator unit 105 is to test the 74LS85 chip, familiar with its peripheral pin functions.

The logic level unit 106 is composed of a single-pole double-throw switch, a banana head socket and two 5Pin exclusion circuits. In this embodiment, the single pole double throw switch is a toggle switch model MTS102, which is commercially available. The main reason for using the button switch is that the nut is arranged on the button switch, so that the button switch is convenient to fix on a panel. As shown by the logic level cells 106 in FIG. 2, "SW 1" through "SW 8" represent 8 single pole double throw switches. A row of 8 round holes with the diameter of 7 mm is arranged in the logic level unit 106 area on the front surface of the panel, and the distance between the centers of two adjacent round holes in the horizontal direction is 4 cm. The leftmost hole is selected, the handle of a single-pole double-throw switch (toggle switch) is inserted into the hole from the back of the panel, and the switch is fixed to the panel by a nut on the front of the panel. The specific circuit is shown in the sub-circuit diagram 106 of FIG. 3, in which the resistor of the resistor bank RP1 is 5.1K Ω. On the back of the panel, the input end of one side of the single-pole double-throw switch is connected with the ground port of the UPS unit 107, the input end of the other side of the single-pole double-throw switch is connected with the 2 pin of the resistor pack, the common end (1 pin) of the resistor pack is connected with the power supply output port of the UPS unit 107, and the middle output end of the single-pole double-throw switch is connected with the banana head socket O1. In the same way, the remaining 7 single pole double throw switches SW 2-SW 8 are connected to the exclusion, UPS unit 107 and corresponding banana head socket in sequence.

The output end of the logic level unit 106 provides a high level or a low level for the circuit, as shown in the sub-circuit diagram labeled 106 in fig. 3, when the single-pole double-throw switch SW1 is pulled to the upper end, the output end is connected to the power supply through the resistor, that is, the banana head socket O1 outputs a high level at this time; when the single-pole double-throw switch SW1 is turned to the lower end, the output end is directly connected with the ground, namely the banana head socket O1 outputs low level. The level of the output of the banana head socket O1 can also be verified by the LED unit 104, specifically, using a banana head connection wire, one end of which is inserted into the banana head socket O1 of the logic level unit 106, and the other end of which is inserted into the banana head socket L1 of the LED unit 104, and toggling a single-pole double-throw switch to observe whether the LED1 is turned on, if so, it indicates that the banana head socket O1 of the logic level unit 106 outputs a high level, otherwise, it outputs a low level. When verifying the logic function of the 74LS85 chip and building a discrete component 1-bit digital comparator, the logic level unit 106 is used, which is described in detail in the following embodiments.

The UPS unit 107 is composed of a 5V power socket, a UPS power module, 18650 lithium batteries, a power switch, and a banana head socket, and is specifically arranged as shown in the UPS unit 107 in fig. 2. In this embodiment, the 5V power socket is a pure copper socket with a nut, model number QZ7034-M9-2.1, and the diameter of the opening is 9 mm. The UPS power module is a miniature circuit board with a size of 3.5 cm × 1.5 cm, and the circuit board has 6 ports, specifically, as shown in a sub-circuit diagram with reference number 107 in fig. 3, the corresponding device is named as "UPS", where two ports with reference numbers "1" and "2" are power input terminals, and are connected to the positive electrode and the negative electrode of a 5V power socket; the positive pole of the 5V power socket is connected with the port 1, and the negative pole is connected with the port 2; the two ports with the labels of 3 and 4 are battery input ends and are respectively connected with the anode and the cathode of the 18650 lithium battery; the two ports marked as '5' and '6' are power output ports, the '5' port is the grounding end of the whole circuit system, the '6' port outputs standard 5V voltage and maximum output current 1A, and the '6' port is connected with the banana head socket through a power switch to supply power to the whole device. All of the components of UPS unit 107 are commercially available in which 18650 lithium batteries are secured to the front of the panel by battery compartments with screw holes in the bottom.

The main functions of the UPS unit 107 are two, one is that in case of an external power input (the power of a computer or a mobile power source can be connected to a 5V power socket through a USB patch cord), the external power can charge the 18650 lithium battery in the UPS unit 107 and supply power to the whole experimental apparatus. And secondly, when no external power supply is available, the UPS module automatically converts the voltage of the 18650 lithium battery into standard 5V voltage to be output and supplies power to the whole experimental device. The UPS unit 107 thus provides uninterruptible power supply for the entire experimental apparatus, and has the advantage of flexibility and convenience, and facilitates experimental operations without power supply.

Two embodiments based on the present invention, namely, the setup of a 1-bit digital comparator circuit and the 74LS85 chip function test, are described next.

As shown in fig. 5, the specific steps of the 1-bit digital comparator circuit construction are as follows:

step 1, with reference to fig. 5 and the sub-circuit diagrams denoted by

reference numerals

103 and 106 in fig. 3, on the panel shown in fig. 2, a banana head connection line is used to connect the banana head socket "O1" in the logic level unit 106 and the banana head socket "a 2" of the not gate logic unit 103, that is, the logic level of the "O1" port is connected to the 3 pins of the CD4069 chip; similarly, according to fig. 5, the banana head socket "O2" in logic level unit 106 and banana head socket "a 1", i.e. "O2" port of not gate logic unit 103 are connected to pin 1 of the CD4069 chip using banana head connection wires.

Step 2, as shown in fig. 5 and the sub-circuit diagrams labeled 101, 103 and 106 in fig. 3, on the panel shown in fig. 2, the banana head socket "Y2" of the not gate logic unit 103 and the banana head socket "a 1" of the and gate logic unit 101 are connected by using the banana head connection line, that is, the level of the output terminal (4 pin) of the second not gate in the CD4069 chip is connected to the input terminal (1 pin) of the first and gate in the CD4081 chip, and simultaneously, the banana head socket "B1" corresponding to the other input terminal (2 pin) of the first and gate in the and gate logic unit 101 and the banana head socket "O2" in the logic level unit 106 are connected by using the banana head connection line. Similarly, banana head connection line is used to connect banana head socket "Y2" of not gate logic unit 103 and banana head socket "B2" of and gate logic unit 101, i.e. the level of the output (pin 2) of the first not gate in CD4069 chip is connected to the input (pin 6) of the second and gate in CD4081 chip, and banana head connection line is used to connect banana head socket "a 2" corresponding to the other input (pin 5) of the second and gate in and gate logic unit 101 and banana head socket "O1" in logic level unit 106. In the last step, banana head sockets "O1" and "O2" in the logic level unit 106 are both occupied, but the plastic handle top of the banana head connection line used in the present invention has a jack with an inner diameter of 2 mm, into which the banana head connection line can be inserted for cascading.

Step 3, as shown in fig. 5 and the sub-circuit diagrams marked with

reference numbers

101, 102 and 104 in fig. 3, the banana head socket "Y1" of the and gate logic unit 101 and the banana head socket "L1" of the led unit 104 are connected by using a banana head connection line, that is, the 3 pin output level of the CD4081 chip is connected to the anode of the led D1, so as to display the value comparison result "a < B". Similarly, banana head connection wire is used to connect banana head socket "Y2" of and gate logic unit 101 and banana head socket "L3" in led unit 104, i.e. 4 pin output level of CD4081 chip is connected to anode of led D3 for displaying numerical comparison result "a > B". Banana head sockets 'Y1' and 'Y2' of the and gate logic unit 101 are respectively connected to banana head sockets 'a 1' and 'B1' of the nor gate logic unit 102 by using banana head connecting wires, namely, first and second and gate output ends (3 pins and 4 pins) of the CD4081 chip are connected to first nor gate input ends (1 pin and 2 pins) of the CD4001 chip in a signal mode; next, the banana head socket "Y1" of the nor gate logic unit 102 and the banana head socket "L2" of the led unit 104 are connected by using banana head connection wires, that is, the 3 pin output level of the CD4001 chip is connected to the anode of the led D2, so as to display the numerical comparison result "a ═ B".

The three steps complete the 1-bit digital comparator circuit building based on the CD4081, CD4001 and CD4069 chips. The circuit shown in fig. 5 implements the most basic numerical comparator circuit, the input and output of which are active high. The power switch is pressed down to toggle the single-pole double-throw switches SW 1-SW 2 in the logic level unit 106, and then the states of the LEDs 1-LED 3 in the LED unit 104 are observed, so that the 1-digit numerical comparison logic function is realized.

Of course, we can also build a 2-bit value comparator, and the circuit structure is similar, so the description is omitted here. The problem can be reserved for students as classroom work, the students are requested to complete circuit building by using a combinational logic circuit design method, and the students build circuits on the experimental device in classroom, so that the classroom atmosphere is activated.

The following describes a method for testing a 74LS85 chip by using the present invention with reference to FIG. 6, which includes the following steps:

step 1, in conjunction with fig. 6 and the sub-circuit diagrams labeled 105 and 106 in fig. 3, on the panel shown in fig. 2, the eight output levels in the logic level unit 106 are divided into two and connected to the value comparison input port of 74LS 85. Specifically, banana head sockets "O1", "O2", "O3" and "O4" in the logic level unit 106 are connected to the banana head sockets with the numbers "10", "12", "13" and "15" in the numerical comparator unit 105 respectively by using banana head connection wires, that is, the logic levels of the ports "O1", "O2", "O3" and "O4" are switched into the numerical comparison input "a 0 a1 A2 A3" (corresponding to the pins 10, 12, 13 and 15 of the chip) of the 74LS85 chip as the first 4-bit binary number; similarly, banana head connectors are used to connect banana head sockets "O5", "O6", "O7" and "O8" in the logic level unit 106 to the banana head sockets labeled "9", "11", "14" and "1" in the numerical comparator unit 105, respectively, i.e., the logic levels of the ports "O5", "O6", "O7" and "O8" are connected as the second 4-bit binary number to the numerical comparison input "B0B 1B 2B 3" of the 74LS85 chip (corresponding to the 9, 11, 14 and 1 pins of the chip).

And 2, switching the cascade input end into a low level. Specifically, on the panel shown in fig. 2, banana head sockets labeled "2", "3" and "4" in the numerical comparator unit 105 are connected to the "G1" port in the UPS unit 107 using banana head connection lines, i.e., pins 2, 3 and 4 of the 74LS85 chip are grounded.

And step 3, combining the sub-circuit diagrams of 104 and 105 in fig. 6 and fig. 3, and displaying the result of the numerical comparison by using a Light Emitting Diode (LED). Specifically, banana head sockets labeled "7", "6" and "5" in the numerical comparator unit 105 are connected to the banana head sockets "L1", "L2" and "L3" in the light emitting diode unit 104, respectively, using banana head connection lines, i.e., the levels of the numerical comparison outputs (pins 7, 6 and 5) in the 74LS85 chip are connected to the anodes of the light emitting diodes D1, D2 and D3, respectively, for displaying the results of the numerical comparison.

Step 4, banana head sockets labeled "8" and "16" in the numerical comparator unit 105 are connected to "G1" and "V1" ports in the UPS unit 107, respectively, using banana head connection wires, that is, power is supplied to 74LS85, a ground port in the UPS unit 107 is connected to 8 pins of 74LS85, and a power port in the UPS unit 107 is connected to 16 pins of 74LS 85.

The circuit construction of the 74LS85 chip test circuit on the panel of the invention shown in FIG. 6 is completed through the above steps. The switch of the UPS unit 107 is pressed to turn on the power supply, the single-pole double-throw switches SW 1-SW 8 in the logic level unit 106 are toggled to access different levels, and the states of the LEDs 1-LED 3 in the LED unit 104 on the panel are observed, so that the test and verification of the value comparison function of the 74LS85 chip are realized.

It should be noted that the above embodiments can be freely combined as necessary. The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. The utility model provides a numerical value comparator experimental apparatus is used in teaching, includes base, panel and banana head connecting wire, its characterized in that: the panel integrates an AND gate logic unit, a NOR gate logic unit, a light emitting diode unit, a numerical value comparator unit, a logic level unit and a UPS unit;

2. The experimental device of numerical comparator for teaching of claim 1, wherein said base is a rectangular parallelepiped structure composed of a single-layer acrylic plate, said panel is a single-layer acrylic plate and fixed on said base by long rod screws; the base and the panel are 60 cm long and 45 cm wide.

3. The experimental device of numerical comparator for teaching of claim 1, wherein said chip adapter plate is composed of a screw hole site, a chip socket, a printed wire and a bonding pad, said bonding pad is connected with said banana head socket through a wire, said chip adapter plate is fixed on said panel through a screw.

4. The teaching numerical comparator experimental device as claimed in claim 1, wherein the diameter of the light emitting diode is 1 cm, and the light emitting color is red.

5. The numerical comparator experimental apparatus for teaching of claim 1, wherein the lithium battery is a 18650 lithium battery.

6. The numerical comparator experimental device for teaching of claim 1, wherein two ends of the banana head connecting wire are respectively provided with a plug, each plug is composed of a plastic handle and a metal lotus head, the diameter of the metal lotus head and the diameter of the inner hole of the banana head socket are both 2 mm, and the top of the plastic handle is provided with a jack with an inner diameter of 2 mm.