CN210129333U

CN210129333U - Parity checker teaching experiment device

Info

Publication number: CN210129333U
Application number: CN201921036876.6U
Authority: CN
Inventors: 郭立强; 陈伏兵; 刘恋
Original assignee: Huaiyin Normal University
Current assignee: Huaiyin Normal University
Priority date: 2019-06-28
Filing date: 2019-06-28
Publication date: 2020-03-06
Anticipated expiration: 2029-06-28

Abstract

The utility model discloses a parity checker teaching experimental device, which comprises a base, a panel and a banana head connecting wire; the panel integrates an exclusive-OR gate logic unit, a light emitting diode unit, a parity checker unit, a logic level unit and a UPS unit. The device is flexible to use and easy to realize, a user can connect all functional units into a 4-way parity checker through the banana head connecting wire, and meanwhile, the functional test and demonstration can be carried out on the parity checker chip 74LS 280; the experimental device adopts large-size elements and chip marks, has a good classroom demonstration function, is a good experimental carrier for teacher-student interaction, is convenient to popularize and use in the classroom of colleges and universities, and has high use value and wide application prospect.

Description

Parity checker teaching experiment device

Technical Field

The utility model relates to the field of electronic technology, concretely relates to parity checker teaching experiment device.

Background

The course is a necessary course for the electronic specialties such as electronic science and technology, electronic information engineering, communication engineering and the like in colleges and universities, and the professional basis of non-electronic specialties such as computer science and technology, Internet of things engineering, physics and the like, plays an important role in the whole talent training system, and lays a good foundation for the study of courses such as subsequent digital system design, singlechip, computer composition principle, integrated circuit design and the like. Parity checkers, as a typical combinational logic circuit, play an important role in the lesson digital electronics foundation. The point of knowledge about the parity checker and its circuit principles primarily includes the design of the discrete component parity checker and the testing and use of the parity checker chip 74LS 280. Through the learning of the two key knowledge points, students can master the design method of the parity checker and the test and the use of the chip of the parity checker. The firmness of the knowledge of the parity checker directly influences the learning of other subsequent combinational logic circuits.

At present, the experiment conditions of the electrical major of all colleges and universities are better, and the electrical major laboratories are equipped with digital circuits. However, in the existing course system of colleges and universities, the teaching mode of "theoretical course + experimental course" is adopted in the course, i.e. theoretical teaching is firstly performed in a multimedia classroom, and then experimental teaching is performed in a professional laboratory. The digital electronic technology foundation is a highly practical course, and if knowledge is infused in theoretical teaching, the learning effect of students is poor. If experimental demonstration is alternated in the teaching process, a plurality of problems exist. For example, the laboratory equipment in a professional laboratory is either a large laboratory platform with a large floor space or a relatively heavy laboratory box. The large experiment platform can not be moved to a common multimedia classroom for class demonstration. For the experimental box, because the volume is small, the functional units are many, which results in high element density, and the LED, the nixie tube, the switch and the like all use small-sized elements. During experiment demonstration, only the front two rows of students can clearly see the experiment, and the later students can hardly see the experiment process and results clearly. Meanwhile, the experiment box adopts 220V alternating current for power supply, and the mobility is poor. In addition, if the experiment box is to face the student to perform classroom demonstration, the flip cover on the experiment box can block the sight of the student, and the demonstration is very inconvenient.

For non-electronic specialties such as computer science and technology, Internet of things engineering and physics, the situation is also not optimistic. For colleges and universities with poor experimental conditions, because non-electric professionals do not have specialized laboratories, the experiments of the class usually adopt EDA simulation based on a computer to complete relevant experimental teaching. This is most common for computer-like specialties. Finally, the learning experience of students is poor, the teachers lack intuition in the explanation of knowledge points, and the teaching atmosphere is quite tedious.

According to questionnaires for college student course study by authorities such as Max, students often are most interested in lesson modes with strong interactivity and courses of experimental demonstration, and are most concentrated in energy when attending lessons. But often cannot raise the spirit of PPT infusion type teaching. According to the problem that meets in this kind of course of the digital electronics technology basis gives lessons in-process, can't use hardware equipment conveniently to carry out parity checker circuit function demonstration on theoretical class promptly, the utility model provides a parity checker experiment teaching device convenient to classroom demonstration for build discrete component parity checker and carry out functional test to 74LS280 chip. The device is a teaching instrument for circuit experiment demonstration of the parity checker, is also a good carrier for teacher-student interaction, plays a positive exemplary role in classroom teaching, can improve classroom attention and learning initiative of students, and has good popularization and use prospects.

Disclosure of Invention

To the problem that exists among the prior art, improve the quality of giving lessons in class, the utility model provides a parity checker experiment teaching device, the utility model discloses the technical scheme who takes as follows:

a parity checker teaching experimental device comprises a base, a panel and a banana head connecting line; the panel integrates an exclusive-OR gate logic unit, a light emitting diode unit, a parity checker unit, a logic level unit and a UPS unit;

the exclusive-OR gate logic unit is composed of a 74LS86 chip, a chip adapter plate and a banana head socket, wherein the 74LS86 chip is fixed on the panel through the chip adapter plate, a power supply port and a ground port of the 74LS86 chip are respectively connected with a power supply output port and a ground port of the UPS unit, and an exclusive-OR logic input end and an exclusive-OR logic output end of the 74LS86 chip are connected with the banana head socket;

the light-emitting diode unit consists of a light-emitting diode, a resistor and a banana head socket, the cathode of the light-emitting diode is connected with the ground port of the UPS unit through the resistor, and the anode of the light-emitting diode is connected with the banana head socket;

the parity checker unit consists of a 74LS280 chip, a chip adapter plate and a banana head socket, wherein the 74LS280 chip is fixed on the panel through the chip adapter plate, and all pins of the 74LS280 chip are connected with the banana head socket;

the logic level unit is composed of a single-pole double-throw switch, a banana head socket and a resistor divider, wherein the input end of one side of the single-pole double-throw switch is connected with the ground port of the UPS unit, the input end of the other side of the single-pole double-throw switch is connected with the power output port of the UPS unit through the resistor divider, and the middle output end of the single-pole double-throw switch is connected with the banana head socket;

the UPS unit is by 5V supply socket, UPS power module, the lithium cell, switch and banana head socket constitute, 5V supply socket's the positive pole and the negative pole link to each other with UPS power module's power input port, the positive pole and the negative pole of lithium cell link to each other with UPS power module's battery port, UPS power module's the positive output of passing through switch links to each other with banana head socket, for whole experimental apparatus power supply, UPS power module's the output negative pole links to each other with banana head socket, as whole experimental apparatus's earthing terminal.

Preferably, the base is a cuboid structure formed by single-layer acrylic plates, and the panel is a single-layer acrylic plate and is fixed on the base through long-rod screws; the base and the panel are 60 cm long and 45 cm wide.

Preferably, the chip adapter plate is composed of a screw hole site, a chip socket, a printed wire and a bonding pad, the bonding pad is connected with the banana head socket through the wire, and the chip adapter plate is fixed on the panel through screws.

Preferably, the diameter of the light emitting diode is 1 cm, and the light emitting color is red.

Preferably, the lithium battery is a 18650 lithium battery.

Preferably, each there is a plug at banana head connecting wire both ends, the plug comprises plastics handle and metal lotus flower head, the diameter of metal lotus flower head with the hole diameter of banana head socket is 2 millimeters, the top of plastics handle has the jack that the internal diameter is 2 millimeters.

Compared with the prior art, the utility model discloses following beneficial effect has:

1. the utility model discloses can test the parity checker chip that the model is 74LS280, can also build 4 way parity checkers based on "exclusive-OR gate" simultaneously, the demonstration through this experimental apparatus makes the student master the basic principle of parity checker, is familiar with the pin function of 74LS280 chip, masters combinational logic circuit's design method, has simple, understandable and the characteristics that the commonality is strong.

2. The utility model discloses a functional unit is abundant, easily realizes that user's accessible banana head connecting wire is connected each functional unit and is accomplished the test of parity checker chip and putting up of discrete component parity checker circuit, uses in a flexible way.

3. The utility model discloses a base and panel all adopt the preparation of inferior gram force board, have weatherability and acid and alkali resistance good, and the impact resistance is strong, easy clean and insulating advantage such as good to the cost is low, the sexual valence relative altitude.

4. The utility model discloses the middle base is 60 centimetres with the panel length, and the width is 45 centimetres, and each unit all prints the jumbo size map that has corresponding chip or component on the panel, and emitting diode's diameter is 1 centimetre, and this kind of unique jumbo size design makes the utility model discloses have good classroom demonstration function, be the interactive good experiment carrier of teachers and students, conveniently use widely on colleges and universities classroom, have wide use value and application prospect.

Drawings

Fig. 1 is a schematic view of a base of the present invention;

FIG. 2 is a structural diagram of the middle panel of the present invention;

FIG. 3 is a circuit diagram of each unit on the middle panel of the present invention;

FIG. 4 is a schematic view of a chip adapter plate according to the present invention;

FIG. 5 is a circuit diagram of a 4-way parity checker according to the present invention;

fig. 6 is a circuit diagram of a 74LS280 chip under test in the present invention.

Reference numerals: 101-exclusive-or gate logic unit, 102-light emitting diode unit, 103-parity checker unit, 104-logic level unit, 105-UPS unit, 201-chip adapter plate, 202-screw hole position, 203-chip socket, 204-printed wire, 205-bonding pad.

Detailed Description

In order to facilitate the technical solution of the present invention to be understood by the skilled person, the technical solution of the present invention will be further described with reference to the accompanying drawings.

A parity checker teaching experimental device comprises a base, a panel and a banana head connecting line. The structure schematic diagram of the base is shown in fig. 1, the base is a box-shaped cuboid made of an acrylic plate with the thickness of 3 mm, the length of the cuboid is 60 cm, the width of the cuboid is 45 cm, and the height of the cuboid is 5 cm. The structure diagram of the panel is shown in fig. 2, and is also made of an acrylic plate with the thickness of 3 mm, 4 corners of the panel and the base are respectively provided with a screw hole position which is aligned up and down, so that the panel is conveniently fixed on the base through long rod screws. The electronic circuit of protection panel back is walked the line for an important effect of base, and another effect is convenient for openly face the student with this experimental apparatus and stand on the podium, makes things convenient for the student to observe the connection and the state of circuit.

As shown in fig. 2, the panel integrates an xor gate logic unit 101, a light emitting diode unit 102, a parity check unit 103, a logic level unit 104, and a UPS unit 105.

The exclusive-or gate logic unit 101 is composed of a 74LS86 chip, a chip adapter plate 201 and a banana head socket, wherein the 74LS86 chip is fixed on a panel through the chip adapter plate 201, a power supply port and a ground port of the 74LS86 chip are respectively connected with a power supply output port and a ground port of the UPS unit 105 and supply power for the chip, and an exclusive-or logic input end and an exclusive-or logic output end of the 74LS86 chip are connected with the banana head socket. There are 4 independent sets of two-input exclusive-or gates in the chip 74LS86, and as shown in the exclusive-or gate logic unit 101 of fig. 2, banana head sockets a1 and B1 are connected to the inputs of the first set of exclusive-or gates, and banana head socket Y1 is connected to the outputs of the first set of exclusive-or gates. By analogy, two input ends and one output end of the other 3 groups of exclusive-or gates are respectively connected with banana head sockets "a 2, B2, Y2", "A3, B3, Y3" and "a 4, B4, Y4". The circuit diagram of the xor gate logic unit 101 in fig. 2 is shown as a sub-circuit diagram of fig. 3, labeled 101, and is drawn with the software of Proteus, which defaults to the chip automatically connecting power and ground, so that both

pins

7 and 14 of the chip are omitted (i.e., there are no pins in the circuit diagram). As shown in the sub-circuit diagram of fig. 3,

reference numeral

101, 4 independent exclusive or gates are respectively connected by "U1: a' to "U1: d "label, the numbers on the 4 xor gate input and output pins represent the pin labels of the 74LS86 chip.

The main function of the xor gate logic unit 101 is to build a 4-way parity checker, which will be described in detail in the following embodiments.

As shown in fig. 4, the chip interposer 201 has screw holes 202 (distributed at 4 corners of the chip interposer 201), a chip socket 203, printed wires 204 and pads 205. The chip adapter plate 201 is used for fixing the chip, and each bonding pad and the chip pin form good electrical communication, so that the chip adapter plate can be conveniently connected with a corresponding banana head socket. In this embodiment, specifically taking the xor gate logic unit 101 as an example, two rows of 14 circular holes with a diameter of 1 mm are formed in the xor gate logic unit 101 on the front surface of the panel, the center distance between two adjacent circular holes in the horizontal direction is 2.5 mm, and the center distance between two adjacent circular holes in the vertical direction is 30 mm; inserting a 74LS86 chip into the chip socket 203 (as shown in FIG. 4, note that the chip has a notch facing to the left, and the bottom row is from left to right, the 1 st pad is connected to the 1 st pin of the chip, the 2 nd pad is connected to the 2 nd pin of the chip, and so on to the 7 th pad; the pad directly above the 7 th pad is the 8 th pad, and the direction is from right to left, and the 9 th pad is in turn from the right to left to the 14 th pad at the top left corner); and selecting a first hole site at the lower left corner, enabling a wire to pass through the acrylic panel and the 1 st bonding pad at the lower left corner of the chip adapter plate 201 from the back of the panel, welding the wire on the bonding pad, and welding the other end of the wire on the banana head socket A1 according to a sub circuit diagram marked with the reference number 101 in the figure 3, and so on, wherein the rest bonding pads are welded on the corresponding banana head sockets except the 7 th and the 14 th bonding pads. The 7 pin of the 74LS86 chip is ground, so the 7 th pad wire is soldered to the ground port of the UPS unit 105 at the back of the panel. Similarly, pin 14 of the chip is the power supply terminal, so the 14 th pad is soldered to the power output port of the UPS unit 105 at the back of the panel. After all the wires are welded, the chip adapter plate is fixed at the middle position of the area shown by the exclusive-or gate logic unit 101 on the front surface of the panel by 4 screws. The implementation steps of fixing 74LS280 chips in the parity checker unit 103 by using a chip adapter plate are similar, and are not described herein again.

The led unit 102 is composed of 8 red leds with a diameter of 1 cm and a banana head socket, as shown in fig. 2. The purpose of selecting the large-diameter light-emitting diode is to facilitate experimental demonstration and observation of students. The light emitting diode is fixed on the corresponding area of the panel through an LED lamp holder with the diameter of an inner hole of 1 cm, and the LED lamp holder is commercially available. When the LED lamp holder is installed, holes are formed in the corresponding area of the panel according to the actual size of the outer diameter of the lamp holder, and then the LED lamp holder is inserted into the panel and fixed to the back of the panel through nuts. In this embodiment, a lamp base with an outer diameter of 1.35 cm is used. The adjacent center spacing of 8 lamp holders is required to be appropriate, so that holes are convenient to open, and in the embodiment, the center spacing of the adjacent lamp holders is 3.5 centimeters. A round hole with the diameter of 4 mm is formed at a position 5 cm below each lamp holder and is used for mounting the banana head socket. Next, the red led is placed in the lamp holder, the cathode of the led is connected to the ground port of the UPS unit 105 through a resistor with a resistance of 10K Ω (specifically, through wire bonding), and the anode of the led is connected to the banana head socket. As shown in the LED unit 102 in fig. 2, "LED 1" to "LED 8" represent 8 red LEDs with a diameter of 1 cm, and anodes of the 8 LEDs are respectively connected to the banana head sockets "L1" to "L8", and the specific circuit is shown in the sub-circuit diagram of reference numeral 102 in fig. 3, in which the element numerals "D1" to "D8" represent the aforementioned 8 LEDs, respectively.

The main function of the led unit 102 is to display the level of the parity output terminal. In order to verify whether the mounted leds are successful, one plug of the banana head connecting line may be inserted into the power port of the UPS unit 105 in fig. 2, i.e. into the banana head socket marked with "V1", and the other plug of the banana head connecting line is inserted into the banana head sockets marked with "L1", "L2", … "and" L8 "of the led unit 102 in sequence, and the power switch is pressed to see whether the corresponding leds are lit, so as to verify whether the led mounting process is problematic.

The parity checker unit 103 is composed of a 74LS280 chip, a chip adapter plate 201 and a banana head socket, and the 74LS280 chip is fixed on the middle area of the parity checker unit 103 on the panel through the chip adapter plate 201. Each pin of the CHIP socket 203 is connected to the corresponding banana head socket of the parity checker unit 103 on the panel through the carrier of the CHIP adapter board 201 by means of flying-wire bonding, and the specific circuit is shown as a sub-circuit diagram 103 in fig. 3, in which "CHIP LOCK" represents the CHIP socket 203, which has 14 pins thereon, and the 14 pins are connected to terminals "1", "2", … "and" 14 ", respectively (these terminals represent the banana head sockets corresponding to the parity checker units 103). Insertion of the 74LS280 chip into the chip socket 203 effects electrical connection of the chip pins to the corresponding banana head socket on the parity checker unit 103. The steps of mounting 74 the LS280 chip using the chip adapter plate 201 are as described above and will not be described in detail here.

As shown in FIG. 2, an enlarged version of the 74LS280 chip schematic and pin identifier text are printed in the area of parity checker unit 103

And

the pin is a 9-way parity input port and is identified by letters 'A' to 'I'.

The pins are empty pins, so that the chip compatibility and the encapsulation are consistent, and no electrical connection meaning exists.

The pin is an even check output port, namely when the 9 parity check input ports have even high levels, the pin outputs the high level, otherwise, the pin outputs the low level.

The pin is an odd check output port, namely when the odd number of high levels exist in the 9 parity check input ports, the pin outputs high level, otherwise, the pin outputs low level. At the same input (whether an odd number of high levels or an even number of high levels),

pin and

the output of the pins is reciprocal.

The pin is a ground port and is identified by the letter "GND"; of a chip

The pin is a power port, identified by the letter "VCC". The chip pin identifiers and the banana head sockets in the area of the parity checker unit 103 on the panel are in one-to-one correspondence, that is to say

Corresponding to the banana head socket numbered "1",

corresponding to the banana head socket labeled "2", …,

corresponding to the banana head socket labeled "14" to facilitate circuit connection. The chip schematic diagram and the pin identification can be printed on the acrylic plate by adopting a UV printing mode (entrusting the relevant UV printing business to customize). Through the design, the functions of all pins of the 74LS280 chip are clearly visible, and teaching demonstration is facilitated.

The main role of the parity checker unit 103 is to test the 74LS280 chip, familiar with its peripheral pin function.

The logic level unit 104 is composed of a single-pole double-throw switch, a banana head socket and two 5Pin exclusion circuits. In this embodiment, the single pole double throw switch is a toggle switch model MTS102, which is commercially available. The main reason for using the button switch is that the nut is arranged on the button switch, so that the button switch is convenient to fix on a panel. As shown by the logic level cells 104 in FIG. 2, "SW 1" through "SW 8" represent 8 single pole double throw switches. A row of 8 round holes with the diameter of 7 mm in total are formed in the logic level unit 104 area on the front surface of the panel, and the distance between the centers of two adjacent round holes in the horizontal direction is 4 cm. The leftmost hole is selected, the handle of a single-pole double-throw switch (toggle switch) is inserted into the hole from the back of the panel, and the switch is fixed to the panel by a nut on the front of the panel. The specific circuit is shown in the sub-circuit diagram 104 in FIG. 3, in which the resistance of the exclusion PP1 is 5.1K Ω. On the back of the panel, the input end of one side of the single-pole double-throw switch is connected with the ground port of the UPS unit 105, the input end of the other side of the single-pole double-throw switch is connected with the 2 pin of the exclusion, the common end (1 pin) of the exclusion is connected with the power output port of the UPS unit 105, and the middle output end of the single-pole double-throw switch is connected with the banana head socket O1. In the same way, the remaining 7 single pole double throw switches SW 2-SW 8 are connected to the exclusion, UPS unit 105 and corresponding banana head sockets in sequence.

The output end of the logic level unit 104 provides a high level or a low level for the circuit, as shown in the sub-circuit diagram labeled 104 in fig. 3, when the single-pole double-throw switch SW1 is pulled to the upper end, the output end is connected to the power supply through the exclusion, that is, the banana head socket O1 outputs a high level at this time; when the single-pole double-throw switch SW1 is turned to the lower end, the output end is directly connected with the ground, namely the banana head socket O1 outputs low level. The level output by the banana head socket O1 can also be verified by the LED unit 102, specifically, using banana head connection wire, one end of which is inserted into the banana head socket O1 of the logic level unit 104, and the other end of which is inserted into the banana head socket L1 of the LED unit 102, and toggling the single-pole double-throw switch to observe whether the LED1 is turned on, if so, it indicates that the banana head socket O1 of the logic level unit 104 outputs high level, otherwise, it outputs low level. When verifying the logic function of the 74LS280 chip and building the split 4-way parity checker, the logic level unit 104 is required, which can be seen in the embodiments described later.

The UPS unit 105 is composed of a 5V power socket, a UPS power module, 18650 lithium batteries, a power switch, and a banana head socket, and is specifically arranged as shown in the UPS unit 105 in fig. 2. In this embodiment, the 5V power socket is a pure copper socket with a nut, model number QZ7034-M9-2.1, and the diameter of the opening is 9 mm. The UPS power module is a miniature circuit board with a size of 3.5 cm × 1.5 cm, and the circuit board has 6 ports, specifically, as shown in a sub-circuit diagram with reference number 105 in fig. 3, the corresponding device is named as "UPS", where two ports with reference numbers "1" and "2" are power input terminals and are connected with the positive electrode and the negative electrode of a 5V power socket; the positive pole of the 5V power socket is connected with the port 1, and the negative pole is connected with the port 2; the two ports with the labels of 3 and 4 are battery input ends and are respectively connected with the anode and the cathode of the 18650 lithium battery; the two ports marked as '5' and '6' are power output ports, the '5' port is the grounding end of the whole circuit system, the '6' port outputs standard 5V voltage and maximum output current 1A, and the '6' port is connected with the banana head socket through a power switch to supply power to the whole device. All of the components of the UPS unit 105 are commercially available in which the 18650 lithium battery is secured to the front of the panel by a battery compartment with screw holes in the bottom.

The main functions of the UPS unit 105 are two, one is that in case of an external power input (the power of a computer or a mobile power source can be connected to a 5V power socket through a USB patch cord), the external power can charge the 18650 lithium battery in the UPS unit 105 and also supply power to the whole experimental apparatus. And secondly, when no external power supply is available, the UPS module automatically converts the voltage of the 18650 lithium battery into standard 5V voltage to be output and supplies power to the whole experimental device. The UPS unit 105 thus provides an uninterruptible power supply for the entire experimental apparatus, which is flexible and convenient, and facilitates experimental operations without power supply.

Two embodiments based on the present invention, namely, the building of a 4-way parity checker circuit and the 74LS280 chip function test, are described next.

The specific experimental steps for building a 4-way parity checker circuit on the panel shown in FIG. 2, according to the circuit shown in FIG. 5, in conjunction with the sub-circuit diagrams labeled 101, 102, 104, and 105 in FIG. 3, are as follows:

step 1, a banana head connecting wire is used for connecting a banana head socket 'O1' in a logic level unit 104 with a banana head socket 'A1' of an exclusive-OR gate logic unit 101, namely, the logic level of an O1 port is connected to a1 pin of a 74LS86 chip; similarly, according to fig. 5, banana head sockets "O2", "O3" and "O4" in logic level unit 104 are connected to banana head sockets "B1", "a 2" and "B2" of xor gate logic unit 101 using banana head connection lines, i.e. the logic levels of the "O2", "O3" and "O4" ports are connected to

pins

2, 4 and 5 of 74LS86 chip, respectively.

Step 2, banana head connection wires are used for connecting banana head sockets "Y1" and "A3" and "Y2" and "B3" of the xor gate logic unit 101, namely, the levels of the output ends (3 pins and 6 pins) of the first and second xor gates in the 74LS86 chip are respectively connected to the input ends (9 pins and 10 pins) of the third xor gate in the chip.

Step 3, according to fig. 5, banana head connection wires are used to connect banana head sockets "Y3" and "a 4" of the xor gate logic unit 101, i.e. the level of the third xor gate output (pin 8) in the 74LS86 chip is switched to the fourth xor gate input (pin 12). The other input (pin 13) of the fourth xor gate is connected to the power supply port "G1" of the UPS unit 105 by using a banana head connection line, i.e. pin 13 of the 74LS86 chip is high. The banana head socket "Y4" of the xor gate logic unit 101 and the banana head socket "L1" of the led unit 102 are connected by using a banana head connection line, that is, the level of the fourth xor gate output (pin 11) of the 74LS86 chip is connected to the anode of the led D1, which is used to indicate whether there are even high levels (the led D1 is turned on) or odd high levels (the led D1 is turned off) in the currently input level, so as to implement the parity check function.

The above three steps complete the 4-way parity checker circuit building based on the 74LS86 chip. The power switch is pressed to toggle the single-pole double-throw switches SW 1-SW 4 in the logic level unit 104, and then the state of the LED1 in the LED unit 102 is observed, so as to implement the parity check function.

Of course, the 4-way parity checker may also adopt basic logic gates (a four-input and gate CD4082, a four-input or gate CD4072, and a not gate CD4069) to build a circuit, but the required logic gates are large in types and chip quantity, and the circuit structure is complex, so that the circuit building is inconvenient, and the principle of the parity checker is not easy to understand for students.

The method of performing 74LS280 chip testing using the present invention is described next with reference to FIG. 6. The 74LS280 chip can perform parity check on 9 input levels, and in order to simplify the test circuit, and also in order to correspond to the previous embodiment, we perform parity check on only 4 input levels, and all the other 5 input ports are connected with high level (connected with power supply). The specific experimental steps for building a 74LS280 chip test circuit on the panel shown in fig. 2, according to the circuit shown in fig. 6 and with the sub-circuit diagrams of fig. 3, which are labeled 102, 103, 104 and 105, are as follows:

step 1, as shown in fig. 6, the 4 output levels in the logic level unit 104 are switched into the parity input port of the 74LS 280. Specifically, banana head connection wires are used to connect the banana head socket "O1" in the logic level unit 104 and the banana head socket labeled "8" in the parity checker unit 103, i.e., the logic level of the "O1" port is switched into the parity check input "a" (8 pins) of the 74LS280 chip; similarly, banana head sockets "O2", "O3" and "O4" in the logic level unit 104 are respectively connected to parity inputs "B" (9 pins), "C" (10 pins) and "D" (11 pins) of the 74LS280 chip using banana head connection lines.

And 2, processing redundant parity input ports. According to fig. 6, the remaining 5 parity input ports of 74LS 280: pins 12, 13, 1, 2 and 4 need to be powered (i.e., high), and for chips in the 74LS family, if an input port is not connected to a circuit (pin is floating), the port is connected to a high level. Of course, these 5 parity input ports can also be connected to the power supply using banana head connection lines to switch high.

And 3, displaying the parity check result by using a Light Emitting Diode (LED). The banana head socket labeled "5" in the parity checker unit 103 is connected to the banana head socket "L1" in the led unit 102 by using a banana head connection line, that is, the level of the EVEN check output port "EVEN" (5 pins) in the 74LS280 chip is connected to the anode of the led D1, for displaying the EVEN check result (when there are EVEN high levels in the current 4 parity input ports, D1 is lighted, otherwise D1 is extinguished). The banana head socket labeled "6" in the parity checker unit 103 is connected to the banana head socket "L2" in the led unit 102 by using a banana head connection line, that is, the level of the ODD check output port "ODD" (pin 6) in the 74LS280 chip is connected to the anode of the led D2, so as to display the ODD check result (when there are ODD high levels in the current 4 parity input ports, D2 is turned on, otherwise D2 is turned off).

Step 4, banana head sockets labeled "7" and "14" in the parity checker unit 103 are connected to "G1" and "V1" ports in the UPS unit 105, respectively, using banana head connection lines, that is, power is supplied to the 74LS280, the ground port "G1" in the UPS unit 105 is connected to 7 pins of the 74LS280, and the power port "V1" in the UPS unit 105 is connected to 14 pins of the 74LS 280.

The circuit construction of the 74LS280 chip test circuit on the panel of the utility model shown in FIG. 6 is completed through the above steps. The switch of the UPS unit 105 is pressed to switch on the power supply, the single-pole double-throw switches SW 1-SW 4 in the logic level unit 104 are switched to access different levels, and the states of the LED1 and the LED2 in the light emitting diode unit 102 on the panel are observed, so that the test and the verification of the parity check function of the 74LS280 chip are realized.

In the above step involving multiple ports connected to the power supply port "V1" in the UPS unit 105 (e.g., processing of the redundant parity input port in step 2), the concatenation can be achieved by inserting the banana head cord into a2 mm inner diameter receptacle provided on the top of the plastic handle of the banana head cord.

In fact, the parity check of 5-way level input can be realized by appropriately modifying the circuit shown in fig. 6: in addition to the above circuit, the banana head socket "O5" in the logic level unit 104 and the banana head socket labeled "12" in the parity checker unit 103 may be connected by using a banana head connection line. Similarly, parity checking for 6-way to 8-way level inputs may be implemented.

It should be noted that the above embodiments can be freely combined as necessary. The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. The utility model provides a parity checker teaching experiment device, includes base, panel and banana head connecting wire, its characterized in that: the panel integrates an exclusive-OR gate logic unit, a light emitting diode unit, a parity checker unit, a logic level unit and a UPS unit;

2. The parity checker teaching experiment device according to claim 1, wherein the base is a rectangular parallelepiped structure composed of a single-layer acrylic plate, and the face plate is a single-layer acrylic plate and fixed to the base by long-rod screws; the base and the panel are 60 cm long and 45 cm wide.

3. The parity checker teaching experiment device according to claim 1, wherein the chip adapter plate is composed of a screw hole site, a chip socket, a printed wire, and a bonding pad, the bonding pad is connected to the banana head socket through a wire, and the chip adapter plate is fixed to the panel through a screw.

4. The parity checker teaching experiment device according to claim 1, wherein the light emitting diode has a diameter of 1 cm and a light emitting color of red.

5. The parity checker teaching experiment device according to claim 1, wherein the lithium battery is a 18650 lithium battery.

6. The parity checker teaching experiment device according to claim 1, wherein each of the two ends of the banana head connecting wire has a plug, the plug is composed of a plastic handle and a metal lotus head, the diameter of the metal lotus head and the diameter of the inner hole of the banana head socket are both 2 mm, and the top of the plastic handle is provided with a jack with an inner diameter of 2 mm.