CN207690363U - A kind of 8 bit digital circuit synthesis experiment plate of portable type - Google Patents
A kind of 8 bit digital circuit synthesis experiment plate of portable type Download PDFInfo
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- CN207690363U CN207690363U CN201720724145.5U CN201720724145U CN207690363U CN 207690363 U CN207690363 U CN 207690363U CN 201720724145 U CN201720724145 U CN 201720724145U CN 207690363 U CN207690363 U CN 207690363U
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Abstract
The utility model is related to a kind of 8 bit digital circuit synthesis experiment plates of portable type, including pcb board, simulation bread board and 8 circuit units are provided on the pcb board, wherein 8 circuit units are respectively fixed logic condition generator and radix-minus-one complement converter, based on 555 clock pulse generator, monopulse generator, 2 decade counters, 8 binary counters, 2 decimal system number displays, logic state indicator, system power supply power supply interface.The utility model is simple in structure portable, and beginner is suitble to use.
Description
Technical field
The utility model is related to Digital Electronic Technique field, especially a kind of 8 bit digital circuit synthesis experiment plate of portable type.
Background technology
The paces of development are constantly progressive along with modern age science and technology, Digital Electronic Technique becomes more next in the application of every field
It is wider.《Digital Electronic Technique》As a core curriculum of electric specialty, its knowledge is very abundant, while being had very
Strong practicality, however due to being limited by the timing closing of school experiment room and experiment number, often make student's logarithm
The practical operation of word circuit and manipulative ability cannot adequately temper raising.
Currently, most of college student is tested with digital circuit experiment case under lab, and experimental box is bulky,
It exists simultaneously and contacts situation bad, that wiring is complicated.Especially student is concentrated use in frequently often, the circuit in experimental box
It is easy to happen failure, causes the failure of an experiment.It is all caused by poor contact, when both wasting in this way that the failure of appearance is most of
Between, and harvest little.
Digital circuit experiment from most begin to use discrete component carry out simply with or NOT logic test, to use small rule
Vlsi die carries out digital circuit and builds, then arrives and carry out digital display circuit experiment with medium scale integration (MSI).In Scientific Research in University Laboratory
Digital experiment circuit be all based on middle small scale integrated circuit.Digital and electronic experiment is done in laboratory, usually by bread
Plate builds circuit, and the line of bread board is more, the failure 80% that occurs in experiment be all due to bread board bottom plate strip conductor with
Caused by poor contact between chip or element pin, excluding these failures will spend for 60% time, really be used for circuit
The time of design is less than 40%.Students, which are tested, much to be limited.
Similar application has with the application institute：
1, " portable general Logical Design and EDA Comprehensive Experiments plate ", the patent No.：CN201120020362.9.This
Item patent is equipped with Field Programmable Logic Array (FPGA), causes the programming of the design erasable, reusable, logic is set
It can intuitively be realized on FPGA after meter compiling, while reduce the use of bread board, but because of this, the design loses
The flexibility of bread board cannot carry out detailed analysis to experimental circuit well, can only also simply use EDA technologies into
The design of row logic circuit.In addition by the way of it downloads file, serial communication and single power supply power supply using USB interface, this
Although sample reduces design cost, it is no longer necessary to buy power source special and dedicated downloading wire, but be easy to cause because of power supply
Output current is too small and the case where subsequent conditioning circuit module can not be driven, especially in the digital circuit experiment of middle scale.
2, " Portable dual-platform digital logic experiment device ", the patent No.：CN201120398713.X.This patent is main
Be made of experiment mainboard and FPGA daughter board two parts, and carry out digital circuit contrived experiment in, using signal source module,
The key signal that logic level switching group module, clock module generate all be by the extraction one by one of the copper hole of each module with
What other interfaces were connected, while the expansion area socket of General experimental socket and FPGA plates is to share plug wire copper hole, this is certain
The reliability of plank is reduced in degree, is broken down the disadvantage is that being easy to cause experimental provision by prolonged use.
Above two patents are not to do experimental design for digital circuit beginner, more suitable for product development.
3, " Portable multifunctional experimental box for class teaching ", the patent No.：CN200520140039.X.This patent is to carry
It can be convenient for carrying the experimental box to the portable multi-function classroom instruction of progress experimental demonstration on the dais of classroom for a kind of, it
Using object mainly in teacher, for student, this patent is not very applicable.The operation of the experimental box simultaneously
Process is that the acquisition of signal is completed by capture card, and data are passed in computer by acquiring card interface, are transported on computers
It has been shown that, processing and the processing of other signals of the corresponding complete pair signals of application software of row are also required to through computer ability
It completes, this series of process is excessively cumbersome, while too relying on computer, is unfavorable for student and carries, discomfort shares
To do digital circuit experiment.
4, " a kind of digital circuit experiment equipment ", the patent No.：CN201620051874.4.This patent provides a kind of number
Word Experiment of Electrical Circuits equipment.The digital circuit experiment equipment includes that power module, circuit build module and multiple experiential function modules,
The power module and multiple experiential function modules are inserted into circuit and build module respectively, and one or more experiential functions can be inserted
Module.Provide it is a kind of easily, realize flexible function, digital circuit experiment equipment that kinds of experiments can be carried out.
This digital circuit power source module, function module needs are built mutually, and circuit does not weld on same circuit board,
Connection reliability is under suspicion.In addition experimental data digit only has four, and flexibility is not strong, and experiment dynamics is inadequate.
5, " digital circuit experiment platform ", the patent No.：CN201420193282.7.This patent discloses a kind of number electricity
Road experiment porch, including CPLD circuit, signal generator, liquid crystal display, button, buzzer, reset circuit, JTAG mouthfuls, door
Current Controller circuit, trigger control circuit, forward-backward counter circuit, decoder circuit and power circuit；The CPLD circuit
It is separately connected signal generator, liquid crystal display, button, buzzer, reset circuit, JTAG mouthfuls, gate circuit control circuit, triggers
Device control circuit, forward-backward counter circuit, decoder circuit, power circuit.But this patent is clearly to be set for laboratory
Meter, belong to large and complete design, is not suitable for student and carries.
Invention content
In view of this, the purpose of this utility model is to provide a kind of 8 bit digital circuit synthesis experiment plate of portable type, structure letter
It is single portable, it is suitble to beginner to use.
The utility model is realized using following scheme：A kind of 8 bit digital circuit synthesis experiment plate of portable type, including pcb board,
Simulation bread board, fixed logic condition generator and radix-minus-one complement converter are provided on the pcb board, based on 555 clock pulses
Generator, monopulse generator, 2 decade counters, 8 binary counters, 2 decimal system number displays, logics
Positioning indicator, system power supply power supply interface；
The fixed logic condition generator and radix-minus-one complement converter to by two 4 bits respectively with true form or anti-
Code output, and export two sign bits；Also exportable 2 8421BCD codes.The system power supply power supply interface and the falseface
Wrapper sheet, logic state indicator, monopulse generator, 2 decade counters, 8 binary counters, based on 555 when
Clock pulse generator, 2 decimal system number displays, fixed logic condition generator and radix-minus-one complement converter are connected.
It is described that the square wave of 10kHz is exported using the oscillation of 555 chips based on 555 clock pulse generator, and pass through two panels
SN74LS390N realizes 4 times 10 frequency dividings, generates the square wave of 1kHz, 100Hz, 10Hz, 1Hz respectively；
The monopulse generator exports two-way positive pulse, two-way negative pulse respectively with two rest-set flip-flops, for single step arteries and veins
Punching, which counts, to be used；
2 decade counters use the ends the Q state of 8 triggers of diode displaying, and export 2 variations
8421BCD code signals, for coding display or cycle send number；
8 binary counters use the ends the Q state of 8 triggers of diode displaying, and export 8 variations
Binary signal, send number for concurrently or sequentially recycling；
2 decimal system number displays receive 2 8421BCD code signals, and two charactrons is used in combination to be shown；
Logic state indicator diode displaying low and high level.
Further, the system power supply power supply interface is reserved with ten positive and negative isopotential points, in case needed for experiment.
Further, the terminal of the simulation bread board connection is welded on same pcb board, is connected above each pad
It is connected to contact pin, the wire jumper that jumper cap is connected to by both ends carrys out unicom total interface.
Further, the simulation bread board is in such a way that top layer, bottom alternately connect up, under the simulation bread board
Side is provided with discrete component prefecture.
Further, the simulation bread board, fixed logic condition generator and radix-minus-one complement converter, based on 555 clock
Impulse generator, monopulse generator, 2 decade counters, 8 binary counters, 2 decimal system number displays,
Logic state indicator is both provided with independent power switch.
The utility model is simple in structure, has the basic function circuit module that Digital Circuit Basics experiment needs, is reducing
While testing plate suqare, using the advantage that simulation bread board is flexible and convenient, the reliability of experimental plate is effectively improved, experimental plate is made
Function is more complete.Meanwhile the utility model creates the experiment of Digital Electronic Technique in the case of do not have oscillograph in student's hand
Condition and experimental situation such as simulate the effect of oscillograph with light emitting diode, and bright lamp is high level, and lamp goes out for low level.This reality
It is integrated on a PCB, can be carried with novel all circuit modules, be that student can be allowed to carry out whenever and wherever possible certainly
The device of main property digital and electronic experiment.
Description of the drawings
Fig. 1 is the schematic block circuit diagram of the utility model embodiment.
Fig. 2 is the fixed logic condition generator and radix-minus-one complement converter schematic diagram of the utility model embodiment.
Fig. 3 is the utility model embodiment based on 555 clock pulse generator schematic diagram.
Fig. 4 is the monopulse generator schematic diagram of the utility model embodiment.
Fig. 5 is 2 decade counter schematic diagrames of the utility model embodiment.
Fig. 6 is 8 binary counter schematic diagrames of the utility model embodiment.
Fig. 7 is 2 decimal system number display schematic diagrames of the utility model embodiment.
Fig. 8 is the logic state indicator schematic diagram of the utility model embodiment.
Fig. 9 is the system power supply power supply interface diagram of the utility model embodiment.
Figure 10 is the digital circuit Comprehensive Experiment plate pcb board wiring diagram schematic diagram of the utility model embodiment.
Specific implementation mode
The utility model is described further with reference to the accompanying drawings and embodiments.
As shown in Figure 1, present embodiments providing a kind of 8 bit digital circuit synthesis experiment plate of portable type, including pcb board, institute
It states and is provided with simulation bread board and 8 circuit units on pcb board, wherein 8 circuit units are respectively fixed logic state hair
Raw device with radix-minus-one complement converter, based on 555 clock pulse generator, monopulse generator, 2 decade counters, 8 two into
Counter processed, 2 decimal system number displays, logic state indicator, system power supply power supply interface.
The title and function of 8 module unit circuits are as follows：
Unit one：Fixed logic condition generator and radix-minus-one complement converter.8 height can be artificially set by single-pole double-throw switch (SPDT)
Low logic level, and two sign bits are set.Two 4 bits can be respectively with true form or Inverse code output, and exports two
Sign bit；Also exportable two 8421BCD codes, double figures code pipe can show corresponding 2 decimal numbers.It is convenient for adding entirely
Device, comparator, the application experiment of data selector or counter export preset data.
Unit two：Based on 555 clock pulse generator.555 chips export the square wave of 10kHz, pass through two panels
SN74LS390N realizes 4 times 10 frequency dividings, generates the square wave of 1kHz, 100Hz, 10Hz, 1Hz respectively.Frequency is relatively low, is convenient for extracurricular meat
Eye observation level height, because being shown after class for waveform without oscillograph.
Unit three：Monopulse generator.Two rest-set flip-flops export two-way positive pulse, two-way negative pulse respectively, for single step
Step-by-step counting is used.
Unit four：2 decade counters.Input clock pulse realizes that 2 8421BCD codes count, and light emitting diode is aobvious
Show the ends the Q state of 8 triggers, observable carry rule, and exports 2 8421BCD code signals.
Unit five：8 binary counters.Input clock pulse realizes 8 binary countings, diode displaying 8
The ends the Q state of a trigger, observable carry rule, and export 8 binary signals.
Unit six：2 decimal system number decoding monitors.Receive 2 8421BCD code signals, with two numeral methods.
Unit seven：Logic state indicator.8 logical signals can be inputted, its low and high level of diode displaying serves as
Logic pen substitutes the effect of oscillograph to a certain extent.
Unit eight：System power supply power supply interface.Power module is separately set, and power interface passes to all element circuits, and reserves
Ten positive and negative isopotential points, in case needed for experiment.Each unit circuit is both provided with independent power switch.
In the present embodiment, a unit：Fixed logic condition generator and the function of radix-minus-one complement converter are can to export two
4 bits (or 2 8421BCD codes) of a tape symbol position, can be exported with true form, can also Inverse code output, be easy to implement
The application experiment of two arbitrary addition and subtractions of binary number or the application experiment of full adder or comparator, can be with digital-scroll technique
Decimal system summand and addend.The circuit is mainly by digital display circuit, single-pole double-throw switch (SPDT), 74LS86N XOR gate chips etc.
Composition.The height of 10 single-pole double-throw switch (SPDT) S4-S13 difference control logic level, by S4-S11 this 8 single-pole double-throw switch (SPDT)s
No. 2 pins are coupled with an input terminal of two panels 74LS86N XOR gates, by No. 2 of S12 and S13 this 2 single-pole double-throw switch (SPDT)s
Pin is coupled with the remaining input terminal of two panels 74LS86N XOR gates, for controlling 74LS86N XOR gates output true form or anti-
Code, represents the sign bit for two addends for carrying out follow-up signed magnitude arithmetic(al).If just for the sake of generating 8 low and high levels (such as
Give counter preset number), then S12 and S13 need to only be thrown in ground terminal, be exported as true form；If in order to generate signed magnitude arithmetic(al)
Two addends and its sign bit, addend are that just, sign bit is " 0 ", and S12 and S13 are thrown in ground terminal, then are by XOR gate output
True form；Addend is negative, and sign bit is " 1 ", and S12 and S13 are thrown in 5V power ends, then is radix-minus-one complement by XOR gate output.Two add
Several sign bits also will output.The element circuit schematic diagram is as shown in Figure 2.
In the present embodiment, Unit two：Be 10KHZ, 1KHZ based on 555 clock pulse generator generation frequency,
The square-wave signal of 100HZ, 10HZ, 1HZ.The circuit be mainly by 555 constitute oscillating circuit, SN74LS00N NAND gates,
The compositions such as SN74LS390N decade counter chips.Resistance R19, R20 and electricity of oscillating circuit charge and discharge are made up of adjusting
The parameter for holding C5, realizes the square wave oscillation of 10kHz.Obtained 10kHz square waves are added to two panels SN74LS390N decimal system meters
4 times 10 frequency dividings are done on number chip, generate the square wave of 1kHz, 100Hz, 10Hz, 1Hz respectively.And in circuit diagram by two with it is non-
Input terminal SW, I N that door is drawn, primarily to the flexibility of enhancing circuit, if SW=0, and add a frequency in IN feet at this time
Rate is FinExternal clock pulses, then F0 is identical with externally input pulse frequency, then carry out 4 times divided by 10 operations, point
The output frequency for not obtaining each point is F4=(1/10000) Fin, F3=(1/1000) FinF2=(1/100) Fin, F1=(1/
10)Fin, F0=Fin.The circuit diagram of the module is as shown in Figure 3.
In the present embodiment, Unit three：The function of monopulse generator is to generate two groups of single pulse sources being independent of each other.
The generation for being controlled two groups of single pulses respectively using two buttons is often pressed a button and just will produce a pulse.Circuit master
It to be made of resistance, button and SN74LS00N NAND gates, control the generation of pulse by button S2 and S3 respectively.The circuit arteries and veins
The characteristic of rest-set flip-flop is mainly utilized in the generation of punching, using the output end of two NAND gates as the input of other side's NAND gate
End, thus constitutes rest-set flip-flop.When button S2 is in original state, it is equivalent to R=0, S=1 of the rest-set flip-flop, then
Q=1, Q=0 are exported, when button is pressed, the state of rest-set flip-flop changes R=1, S=0, then exports Q=0, Q=1,
It can thus be seen that primary bounce has occurred in the state of output Q, the generation of button control pulse is just realized in this way.Module electricity
Road figure as shown in Figure 4
In the present embodiment, Unit four：2 decade counters carry out decade counter to input signal, and utilize 8
Two 8421BCD codes of diode displaying.The circuit unit mainly by resistance, SN74LS390N decade counters,
The compositions such as SN74LS240N phase inverters.SN74LS390N includes two panels decade counter, counts from 0 to 99 totally 100 states,
CLK is the clock signal that input counts, and CLR is to count clear terminal, and output signal 1QD, 1QC, 1QB, 1QA represent the meter of units
Number, 2QD, 2QC, 2QB, 2QA represent the counting of tens.By the chip data of 74LS390N it is found that clock to be counted is believed
Number CLK is connected to first input terminal 1CKA, and 1QA is connected to first input terminal 1CKB, 1QD and is connected to second input terminal
2CKA, 2QA are connected to second input terminal 2CKB, and circuit is exactly the purpose for realizing 100 frequency dividings.And R10, R11 in circuit,
R12, D19, Q1 form reset circuit, and when CLR does not receive any signal, CLR=1, Q1 conducting, this represents 74LS390N's
Clear terminal is 0, and chip normally counts；And if when CLR=0, Q1 cut-off, this represent 74LS390N clear terminal be 1, chip is done
It counts and resets work.The circuit diagram of the unit is as shown in Figure 5.
In the present embodiment, Unit five：8 binary counters carry out binary counting to input signal, and utilize 8
Diode displaying binary number.Principle is similar to 2 decade counters, and difference is only to use binary counter
SN74LS393.CLK be input count clock signal, CLR be count clear terminal, output signal 4QD, 4QC, 4QB, 4QA,
3QD, 3QC, 3QB, 3QA represent 8 bits.The circuit diagram of the module is as shown in Figure 6.
In the present embodiment, Unit six：Two decimal numbers are shown phase by 2 decimal system number displays on charactron
The number answered.The circuit is mainly made of charactron, SN74LS47N decoders etc..And using the seven of common-anode in circuit
Segment numeral pipe, 74LS47 are seven-segment decoders, and decoder input is 4 binary-coded decimals, is exported as the low level corresponding to seven sections,
A certain section of output therein is 0, and charactron is corresponded to section and lighted by expression, indicates that corresponding section is extinguished for 1, it can be by input terminal DCBA
Numerical value conversion shown on charactron at corresponding numerical chracter.Such as to show numerical value 0001=1, then must
The two LED of b, c must be allowed to light, it is seen that be only number 1, and decoder 74LS47 is just responsible for becoming 0,001 1 decoding
Device.The circuit diagram of the unit is as shown in Figure 7.
In the present embodiment, Unit seven：The function of logic state indicator acts as the effect of logic pen, to a certain degree
The upper display for substituting oscillograph.The low and high level for representing 8 road binary numbers can be shown simultaneously.The circuit mainly by exclusion,
The compositions such as 88 latch of SN74HC373N, SN74LS240N phase inverters.74HC373N is state latch chip, and
SN74LS240N includes 8 phase inverters, respectively drives D3-D108 LED.Signal to be shown is defeated by 2 to 9 terminals of interface P3
Enter, shown by D3-D10, logic 1 (i.e. high level) is represented when LED light is bright, does not work and represent logical zero (i.e. low level).Interface
The ends EN of P3 are the enabled control terminal of 74HC373N makes LE=0 as EN=0, at this moment the output end Q of 74HC373NNNot with defeated
Enter end variation, plays the purpose for latching original state.Therefore in normal use circuit, it should which the ends EN is hanging.The module
Circuit diagram is as shown in Figure 8.
In the present embodiment, Unit eight：The external power supply for switching to DC5V, 1A by AC220V power supplies of system power supply power supply interface
Adapter is whole system module for power supply.What power supply interface module was mainly made of DC5V sockets, button, light emitting diode etc..
The break-make of power supply is controlled using button S1, diode displaying power work is normal, and P1 and P2 are respectively the 5V direct currents reserved
The wire jumper that both ends are connected to jumper cap can be used to carry out grafting whenever necessary for power interface and grounding ports.The circuit of the module is former
Reason figure is as shown in Figure 9.
In the present embodiment, simulation bread board is Experimental Area, and the major function of the module is to provide experimental place, grafting
By empirical numerical integrated chip and auxiliary element.The structure for simulating bread board imitates common bread board.Intermediate two rows pad is used for
It is inserted into digital integration chip pin, each pin is connected to other 3 pads of vertical setting of types.Per vertical setting of types connection, horizontally-arranged be not connected to.Simulation
The pre-terminated port of independent 22 connections per horizontally-arranged 3 is also devised with below bread board, preparation access capacitance, resistance etc. are common
Component makes experimental circuit that can flexibly change.Unlike common bread board：It is between the terminal of simulation bread board connection
It is welded on same pcb board, contact pin of ining succession above each pad, the wire jumper of jumper cap is connected to by both ends, and to carry out unicom all
Interface improves many than common plastics bread board in the reliability of unicom, while remaining the flexibility of bread board.
The pcb board wiring diagram of the digital circuit Comprehensive Experiment plate of the present embodiment is as shown in Figure 10.
The simulation bread board of the present embodiment takes the mode that top layer, bottom alternately connect up, and not only insulate, while circuit is again
There is certain intensity.Discrete component prefecture is devised on the downside of simulation bread board, simulation bread board is welded on one with whole pcb board
It rises, the wire jumper that jumper cap is connected to by both ends carrys out unicom total interface, makes simulation bread board than common plastics bread board in unicom
Reliability on improve many, while remaining the flexibility of bread board.The portable type digital circuit synthesis of the present embodiment is real
It tests plate in the form of 8 binary systems or 2 8421BCD are metric to occur, is for the first time in this field.Fixation in the present embodiment
Logic state generator and radix-minus-one complement converter are the functions of never occurring in similar patent, are easy to implement two arbitrary binary systems
Several addition and subtraction experiments or the application experiment of full adder or the application experiment of comparator, or add to the data terminal of data selector
Fixed level, or give two integrated counter preset numbers.Each module in the present embodiment is owned by independent power switch, with
Just the saving energy, blocking element are charged for a long time, enhance the durability of circuit.
It is noted that the utility model protection is hardware configuration, it is not claimed as design Communication software.With
Upper is only a preferable embodiment in the utility model embodiment.But the utility model is not limited to above-mentioned embodiment party
Case, all any equivalent changes done by the utility model and modification, generated function is without departing from this programme
When range, the scope of protection of the utility model is belonged to.
Claims (5)
1. a kind of 8 bit digital circuit synthesis experiment plate of portable type, it is characterised in that：Including pcb board, it is provided on the pcb board
Bread board, fixed logic condition generator is simulated with radix-minus-one complement converter, based on 555 clock pulse generator, pulse to occur
Device, 2 decade counters, 8 binary counters, 2 decimal system number displays, logic state indicator, system supply
Electric power interface；
The fixed logic condition generator is with radix-minus-one complement converter to two 4 bits are defeated with true form or radix-minus-one complement respectively
Go out, and exports 2 8421BCD codes of two sign bits or output：
It is described that the square wave of 10kHz is exported using the oscillation of 555 chips based on 555 clock pulse generator, and pass through two panels
SN74LS390N realizes 4 times 10 frequency dividings, generates the square wave of 1kHz, 100Hz, 10Hz, 1Hz respectively；
The monopulse generator exports two-way positive pulse, two-way negative pulse respectively with two rest-set flip-flops, for single step pulse meter
Number is used；
2 decade counters use the ends the Q state of 8 triggers of diode displaying, and export 2 8421BCD
Code signal, to realize 2 decade counters；
8 binary counters use the ends the Q state of 8 triggers of diode displaying, and export 8 binary system letters
Number, to realize 8 binary countings；
2 decimal system number displays receive 2 8421BCD code signals, and two charactrons is used in combination to be shown；
Logic state indicator diode displaying low and high level；
The system power supply power supply interface and the simulation bread board, fixed logic condition generator and radix-minus-one complement converter are based on
555 clock pulse generator, monopulse generator, 2 decade counters, 8 binary counters, 2 decimal numbers
Code display, logic state indicator are connected.
2. 8 bit digital circuit synthesis experiment plate of a kind of portable type according to claim 1, it is characterised in that：The system
Power supply interface is reserved with ten positive and negative isopotential points, in case needed for experiment.
3. 8 bit digital circuit synthesis experiment plate of a kind of portable type according to claim 1, it is characterised in that：The simulation
The terminal of bread board connection is welded on same pcb board, is welded with contact pin above each pad, wire jumper is connected to by both ends
The wire jumper of cap carrys out unicom total interface.
4. 8 bit digital circuit synthesis experiment plate of a kind of portable type according to claim 1, it is characterised in that：The simulation
Bread board is provided with discrete component prefecture in such a way that top layer, bottom alternately connect up on the downside of the simulation bread board.
5. 8 bit digital circuit synthesis experiment plate of a kind of portable type according to claim 1, it is characterised in that：The simulation
Bread board, fixed logic condition generator and radix-minus-one complement converter, based on 555 clock pulse generator, monopulse generator, 2
Position decade counter, 8 binary counters, 2 decimal system number displays, logic state indicators are both provided with independence
Power switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720724145.5U CN207690363U (en) | 2017-06-21 | 2017-06-21 | A kind of 8 bit digital circuit synthesis experiment plate of portable type |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720724145.5U CN207690363U (en) | 2017-06-21 | 2017-06-21 | A kind of 8 bit digital circuit synthesis experiment plate of portable type |
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|---|---|
| CN207690363U true CN207690363U (en) | 2018-08-03 |
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|---|---|---|---|
| CN201720724145.5U Expired - Fee Related CN207690363U (en) | 2017-06-21 | 2017-06-21 | A kind of 8 bit digital circuit synthesis experiment plate of portable type |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109637311A (en) * | 2019-01-10 | 2019-04-16 | 长江大学 | A kind of Teaching Digital Circuit Practical training equipment |
| CN114120775A (en) * | 2020-08-28 | 2022-03-01 | 济南浪潮高新科技投资发展有限公司 | Electronic experiment simulation system based on VR |
| CN114743445A (en) * | 2022-05-19 | 2022-07-12 | 杭州企茏电子科技有限公司 | Spliced A/D and system conversion demonstration system |
| CN114839527A (en) * | 2022-07-04 | 2022-08-02 | 国网辽宁省电力有限公司 | Circuit breaker detection device with power supply |
-
2017
- 2017-06-21 CN CN201720724145.5U patent/CN207690363U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109637311A (en) * | 2019-01-10 | 2019-04-16 | 长江大学 | A kind of Teaching Digital Circuit Practical training equipment |
| CN114120775A (en) * | 2020-08-28 | 2022-03-01 | 济南浪潮高新科技投资发展有限公司 | Electronic experiment simulation system based on VR |
| CN114743445A (en) * | 2022-05-19 | 2022-07-12 | 杭州企茏电子科技有限公司 | Spliced A/D and system conversion demonstration system |
| CN114743445B (en) * | 2022-05-19 | 2024-04-05 | 杭州企茏电子科技有限公司 | Spliced A/D and system conversion demonstration system |
| CN114839527A (en) * | 2022-07-04 | 2022-08-02 | 国网辽宁省电力有限公司 | Circuit breaker detection device with power supply |
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