CN114743445A - Spliced A/D and system conversion demonstration system - Google Patents
Spliced A/D and system conversion demonstration system Download PDFInfo
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- CN114743445A CN114743445A CN202210555461.XA CN202210555461A CN114743445A CN 114743445 A CN114743445 A CN 114743445A CN 202210555461 A CN202210555461 A CN 202210555461A CN 114743445 A CN114743445 A CN 114743445A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09B—EDUCATIONAL OR DEMONSTRATION APPLIANCES; APPLIANCES FOR TEACHING, OR COMMUNICATING WITH, THE BLIND, DEAF OR MUTE; MODELS; PLANETARIA; GLOBES; MAPS; DIAGRAMS
- G09B23/00—Models for scientific, medical, or mathematical purposes, e.g. full-sized devices for demonstration purposes
- G09B23/06—Models for scientific, medical, or mathematical purposes, e.g. full-sized devices for demonstration purposes for physics
- G09B23/18—Models for scientific, medical, or mathematical purposes, e.g. full-sized devices for demonstration purposes for physics for electricity or magnetism
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Abstract
The invention discloses a spliced A/D and system conversion demonstration system, which comprises: the device comprises an external signal-voltage conversion unit, an operational amplifier comparator cascade unit, a diode coding unit, a level matching unit and a nixie tube display unit; each unit is detachably spliced through a wiring terminal, and through splicing, the demonstration system can dynamically convert external data acquired by an external signal sensor into numbers to be displayed and simultaneously perform decimal/binary/hexadecimal dynamic conversion demonstration. The invention realizes A/D conversion and system conversion by disassembling and assembling circuit hardware, can better adapt to the entrance study of beginners, and lays a solid foundation for the later study of the operation of a singlechip.
Description
Technical Field
The invention belongs to the technical field of electronic technology teaching aids, and relates to a spliced A/D and system conversion demonstration system which is based on a logic circuit and an operational amplifier comparator circuit, is combined with a special professional chip and nixie tube display, and realizes A/D conversion and nixie tube system dynamic conversion through splicing combination.
Background
With the continuous change and development of the internet and big data industry, teaching materials, courses and demonstration devices of some basic knowledge become new blank points at present, and because of being closely combined with the modern education such as new internet, big data and the like, a large number of talents which are connected with the current market economy can be cultured in an accelerated way. The invention provides a door entry demonstration instrument suitable for the current elementary electronic technology, so that a user can deepen the understanding of A/D conversion and system conversion through a hardware circuit.
Disclosure of Invention
The invention aims to provide a spliced A/D and system conversion demonstration system aiming at the defects of the prior art; the method can be applied to classroom teaching or demonstration of digital circuits, logic circuits, binary conversion and the like.
The technical scheme adopted by the invention is as follows:
a spliced A/D and system conversion demonstration system comprises: the device comprises an external signal-voltage conversion unit, an operational amplifier comparator cascade unit, a diode coding unit, a level matching unit and a nixie tube display unit;
wherein: the external signal-voltage conversion unit is used for converting acquired external signal data into voltage signals and transmitting the voltage signals to the operational amplifier comparator cascade unit, the operational amplifier comparator cascade unit forms high level output according to the input voltage signals, only one path of high level output is formed when the voltage signals are input once, and the operational amplifier comparator cascade unit can form n paths of high level output according to all the input voltage signals; the n paths of high level outputs correspond to 1-n numbers, and the diode coding unit utilizes a diode circuit to realize that each path of high level is input and then outputs the high level on a binary digit number corresponding to the high level; the level matching unit is used for performing level matching conversion on the output signal of the diode coding unit so as to meet the display requirement of the nixie tube and outputting the output signal to the nixie tube display unit; the nixie tube display unit comprises at least two of a decimal unit, a binary unit and a hexadecimal unit;
each unit is detachably spliced through a wiring terminal, and through splicing, the demonstration system can dynamically convert external data acquired by an external signal sensor into numbers to be displayed and simultaneously perform decimal/binary/hexadecimal dynamic conversion demonstration.
In the above technical solution, further, the external signal-voltage conversion unit includes an external signal sensor, and the external signal for collecting is gravity, pressure, temperature, humidity, light intensity, or concentration.
Furthermore, the operational amplifier comparator cascade unit may adopt a plurality of operational amplifier chips cascaded to form a voltage comparator with at least n high level outputs.
Furthermore, the diode coding unit utilizes the combination of complete diodes to realize that each path of input high level outputs high level on the binary digit number corresponding to the high level.
Furthermore, a CD4511 chip is adopted in the decimal unit to realize decimal nixie tube display by binary coding.
The beneficial effects of the invention are:
the invention can lead a user to feel a digital circuit and a logic circuit more intuitively and deepen the understanding of the scale conversion rule in the manual splicing process by connecting and combining the units in a detachable splicing mode, avoids the use of a singlechip technology which is difficult to be understood by a beginner, realizes A/D conversion and scale conversion by disassembling and assembling circuit hardware, can better adapt to the entrance study of the beginner, and lays a solid foundation for the later study of the operation of the singlechip.
Drawings
FIG. 1 is a schematic diagram of a specific structure of the tiled type A/D and scale conversion demonstration system of the present invention;
fig. 2 is a schematic structural diagram of an external signal-voltage conversion unit (gravity-voltage conversion unit);
FIG. 3 is a schematic diagram of a LM 3244 comparison circuit;
FIG. 4 is a schematic diagram of a cascade unit structure of an operational amplifier comparator;
FIG. 5 is a view showing the connection between a decimal unit and a binary unit of the nixie tube;
FIG. 6 is a schematic diagram of a diode coding unit;
FIG. 7 is a schematic diagram of a structure of a level matching unit;
FIG. 8 is a schematic diagram of a display structure of a nixie tube in a decimal unit;
FIG. 9 is a schematic diagram of a display structure of a nixie tube in a binary unit;
Detailed Description
The technical solution of the present invention is further described in detail with reference to the following specific examples.
The invention discloses a spliced A/D and system conversion demonstration system, which comprises: the device comprises an external signal-voltage conversion unit, an operational amplifier comparator cascade unit, a diode coding unit, a level matching unit and a nixie tube display unit;
wherein: the external signal-voltage conversion unit is used for converting acquired external signal data into voltage signals and transmitting the voltage signals to the operational amplifier comparator cascade unit, the operational amplifier comparator cascade unit forms high level output according to the input voltage signals, only one path of high level output is formed when the voltage signals are input once, and the operational amplifier comparator cascade unit can form n paths of high level output according to all the input voltage signals; the n paths of high level outputs correspond to 1-n numbers, and the diode coding unit utilizes a diode circuit to realize that each path of high level is input and outputs the high level on a binary digit number corresponding to the high level corresponding number according to a binary conversion rule; the level matching unit is used for performing level matching conversion on the output signal of the diode coding unit so as to meet the display requirement of the nixie tube and outputting the output signal to the nixie tube display unit; the nixie tube display unit comprises at least two of a decimal unit, a binary unit and a hexadecimal unit;
each unit is detachably spliced through a wiring terminal, and through the splicing, the demonstration system can dynamically convert external data acquired by an external signal sensor into numbers to display and simultaneously perform decimal/binary/hexadecimal dynamic conversion demonstration.
According to an embodiment of the present invention, the external signal data in the present invention may be any one of gravity, pressure, temperature, humidity, light intensity, concentration, and the like, and the external signal data in the detected specific range may be converted into a linear voltage signal through the external signal-voltage converting unit, and the linear voltage signal forms high level outputs on different bits through the operational amplifier comparator cascade unit, so that the external signals with different sizes are corresponding to different numbers for dynamic display.
According to an embodiment of the present invention, the operational amplifier comparator cascade unit in the present invention may adopt a plurality of operational amplifier chips cascaded to form a voltage comparator with at least n high level outputs. n may be determined according to the specific presentation needs.
According to an embodiment of the present invention, the diode coding unit in the present invention only uses the combination of diodes to realize the coding of 1-n high level inputs, corresponding to the high level on the output binary digit number.
The following description is made of a decimal/binary conversion demonstration in which the external signal is gravity.
Fig. 1 is a schematic diagram showing a specific structure of the splicing type a/D and scale conversion demonstration system in this example; comprises the following steps:
an external signal-voltage conversion unit, as shown in fig. 2, in the figure, a Dc-Dc conversion mode is adopted, so that a voltage signal converted by gravity is an independent voltage signal, and has no direct current connection with a digital display circuit and an operational amplifier comparator cascade circuit in the present example, wherein JP3 inputs a 5V direct current voltage, a B0512-1W module converts and outputs a 12V direct current working voltage, the working voltage is applied to a JP 1500 g-1kg strain gauge gravity sensor, the output voltage is input to two LM358 operational amplifier circuits through R2 and R6, and the signal output is at a JP2 terminal. In order to make the circuit simple and clear, only one lm358 operational amplifier circuit chip is adopted, and stable linear voltage with output of 0.5-1V is obtained.
An operational amplifier comparator cascade unit, as shown in fig. 3, which is an LM324 four operational amplifier comparison circuit, wherein pins 1 and 2 of J1 in the figure are voltage signals Vi input by an external signal-voltage conversion unit, when Vi is greater than VR20, U1D in the figure outputs high level, and outputs about 3 volts, i.e., D0, through R17 and R18; when Vi is larger than VR15, U1C outputs high level, and outputs about 3 volts through R12 and R13, namely D1, and simultaneously turns on Q4 and turns off D0 through R19; when Vi is greater than VR10, in the figure, U1B outputs a high level, and outputs about 3 volts through R7 and R8, that is, D2, and at the same time, Q3 is turned on through R14, and D1 and D0 are turned off. When Vi is greater than VR5, in the figure, U1A outputs a high level, and outputs about 3 volts through R2 and R1, that is, D3, and at the same time, Q2 is turned on through R9, and D2, D1 and D0 are turned off. D0, D1, D2 and D3 … … Dn outputs can be output as long as a plurality of lm324 circuit boards are cascaded at the same time. The cascading method in this example is shown in fig. 4, and 12 high-level outputs can be formed through cascading of three lm324 chips.
The diode coding unit completely adopts diodes to realize coding of input different high levels, so that high level output is formed on binary digits corresponding to the high level digits, in the example, as shown in figure 6, decimal numbers 1-9 and binary dynamic conversion are taken as an example, only the first 9 of 12 high level outputs after three lm324 chips are cascaded are taken in the example, the high level outputs correspond to 1-9, and each high level input is coded by utilizing the unidirectional conduction action of the diodes, so that four-digit states of D3, D2, D1 and D0 are obtained at an output end, and the four-digit states correspond to the input high levels, namely 1-0001, 2-0010, 3-0011, 4-0100, 5-0101, 6-0110, 7-0111, 8-1000 and 9-1001 in the example.
The level matching circuit lm324 is a four-operational amplifier chip, four operational amplifiers can be designed into four comparison circuits, and due to the characteristics and design requirements of the lm324 chip, the high level output by the lm324 is only 2.8-3.2V, and is too large in difference with the level (taking CD4511 as an example, 5V working voltage, generally more than 4.5V is required to be high level) of digital tube display circuits for changing numbers, so in the example, as shown in fig. 7, an npn triode 8050 and a pnp triode 8550 are adopted as level matching conversion, so that any comparator output in the lm324 can have corresponding digital display, and the accuracy of digital display signals of the circuits is ensured.
The nixie tube display unit comprises a decimal unit and a binary unit in the example, and the signals matched by the level matching unit are input into the decimal unit and the binary unit together; FIG. 8 shows a display of a charactron in a decimal cell implemented using a CD4511, where CD4511 is a 4-line-7-segment latch decoder/driver (BCD input), i.e., pin 7 input D0, pin 1 input D1, pin 2 input D2, and pin 6 input D3. When the 7 th pin inputs high level, the nixie tube displays '1'; when the 1 st pin inputs high level, the nixie tube displays '2'; when the 2 nd pin inputs high level, the nixie tube displays '4'; when the 6 th pin inputs high level, the nixie tube displays '8'. Meanwhile, when the 7 th pin and the 1 st pin input high level simultaneously, the nixie tube displays '3'; when the 2 nd pin and the 1 st pin input high level simultaneously, the nixie tube displays '6'; when the 1 st, 2 nd and 7 th pins input high level at the same time, the nixie tube displays '7'; when the high level is input to the pins 6 and 7 at the same time, the nixie tube displays '9'. Thus, decimal nixie tube display (within 1-9) is realized by binary coding on a CD4511 chip. Fig. 9 is a graph of a nixie tube in binary unit, where R2, 4.7k is connected to high level, the nixie tube shows '1', and the nixie tube shows '0' when connected to low level. Therefore, four such nixie tubes may be provided in the binary unit, with p6 connected to D0 by splicing in the nixie tube circuit at position D0; the p6 in the nixie tube circuit at the position D1 is connected with D1; the p6 in the nixie tube circuit at the position D2 is connected with D2; the p6 in the nixie tube circuit at position D3 is connected to D3. Therefore, the decimal display circuit and the binary circuit are connected through splicing and splitting, and the dynamic linking and conversion of the decimal circuit and the binary circuit are realized.
Through the assembly and disassembly of all units in the demonstration system, the most basic application foundation can be laid for a user to learn to use the single chip microcomputer, accumulate preliminary knowledge for the programming of the single chip microcomputer and the matching of peripheral hardware circuits of the single chip microcomputer.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the present invention.
Claims (5)
1. A spliced A/D and system conversion demonstration system is characterized by comprising: the device comprises an external signal-voltage conversion unit, an operational amplifier comparator cascade unit, a diode coding unit, a level matching unit and a nixie tube display unit; wherein: the external signal-voltage conversion unit is used for converting acquired external signal data into voltage signals and transmitting the voltage signals to the operational amplifier comparator cascade unit, the operational amplifier comparator cascade unit forms high level output according to the input voltage signals, only one path of high level output is formed when the voltage signals are input once, and the operational amplifier comparator cascade unit can form n paths of high level output according to all the input voltage signals; the n paths of high level outputs correspond to 1-n numbers, and the diode coding unit utilizes a diode circuit to realize that each path of high level is input and then outputs the high level on a binary digit number corresponding to the high level; the level matching unit is used for performing level matching conversion on the output signal of the diode coding unit so as to meet the display requirement of the nixie tube and outputting the output signal to the nixie tube display unit; the nixie tube display unit comprises at least two of a decimal unit, a binary unit and a hexadecimal unit;
each unit is detachably spliced through a wiring terminal, and through the splicing, the demonstration system can dynamically convert external data acquired by an external signal sensor into numbers to display and simultaneously perform decimal/binary/hexadecimal dynamic conversion demonstration.
2. The spliced A/D and scale conversion demonstration system according to claim 1, wherein the external signal-voltage conversion unit comprises an external signal sensor, and the external signal for collection is gravity, pressure, temperature, humidity, light intensity or concentration.
3. The tiled A/D and scale conversion demonstration system according to claim 1, wherein the operational amplifier comparator cascade unit is formed by cascading a plurality of operational amplifier chips to form a voltage comparator with at least n high level outputs.
4. The tiled ad and am presentation system of claim 1, wherein the diode coding unit utilizes a combination of complete diodes to realize that each input channel of high level outputs high level on the binary digit number corresponding to the high level.
5. The tiled A/D and decimal conversion presentation system according to claim 1, wherein a CD4511 chip is adopted in the decimal unit to realize decimal nixie tube display by binary coding.
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| CN202210555461.XA CN114743445B (en) | 2022-05-19 | 2022-05-19 | Spliced A/D and system conversion demonstration system |
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| CN202210555461.XA CN114743445B (en) | 2022-05-19 | 2022-05-19 | Spliced A/D and system conversion demonstration system |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101394183A (en) * | 2008-10-30 | 2009-03-25 | 上海大学 | A/D direct computing conversion, A/D cascade converter and use thereof |
| CN203325271U (en) * | 2013-07-22 | 2013-12-04 | 曹丽 | Teaching demonstrator for binary numbers |
| CN206003409U (en) * | 2016-05-16 | 2017-03-08 | 重庆电子工程职业学院 | A kind of single-chip microcomputer experiment system |
| CN207690363U (en) * | 2017-06-21 | 2018-08-03 | 厦门大学嘉庚学院 | A kind of 8 bit digital circuit synthesis experiment plate of portable type |
| CN212460931U (en) * | 2020-07-27 | 2021-02-02 | 肖义军 | Real standard equipment of piece together combination formula digital circuit |
| CN214504765U (en) * | 2021-01-14 | 2021-10-26 | 赤峰学院 | Digital system conversion demonstration device |
| CN113990158A (en) * | 2021-11-16 | 2022-01-28 | 中国民航大学 | Building block type electricity counting experiment device |
-
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- 2022-05-19 CN CN202210555461.XA patent/CN114743445B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101394183A (en) * | 2008-10-30 | 2009-03-25 | 上海大学 | A/D direct computing conversion, A/D cascade converter and use thereof |
| CN203325271U (en) * | 2013-07-22 | 2013-12-04 | 曹丽 | Teaching demonstrator for binary numbers |
| CN206003409U (en) * | 2016-05-16 | 2017-03-08 | 重庆电子工程职业学院 | A kind of single-chip microcomputer experiment system |
| CN207690363U (en) * | 2017-06-21 | 2018-08-03 | 厦门大学嘉庚学院 | A kind of 8 bit digital circuit synthesis experiment plate of portable type |
| CN212460931U (en) * | 2020-07-27 | 2021-02-02 | 肖义军 | Real standard equipment of piece together combination formula digital circuit |
| CN214504765U (en) * | 2021-01-14 | 2021-10-26 | 赤峰学院 | Digital system conversion demonstration device |
| CN113990158A (en) * | 2021-11-16 | 2022-01-28 | 中国民航大学 | Building block type electricity counting experiment device |
Non-Patent Citations (1)
| Title |
|---|
| 樊辉娜;: "关于七段数码显示模块设计", 南昌高专学报, no. 06, pages 108 - 109 * |
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