CN210005638U - Daughter board control device and burn-in daughter board - Google Patents
Daughter board control device and burn-in daughter board Download PDFInfo
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- CN210005638U CN210005638U CN201920245812.0U CN201920245812U CN210005638U CN 210005638 U CN210005638 U CN 210005638U CN 201920245812 U CN201920245812 U CN 201920245812U CN 210005638 U CN210005638 U CN 210005638U
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Abstract
The embodiment of the application discloses an seed board control device and a burn-in daughter board, the daughter board control device comprises a control circuit board and a controller, wherein the control circuit board is used for being installed on the daughter board circuit board and electrically connected with the daughter board circuit board, the controller is arranged on the control circuit board and used for sending an excitation signal to a chip to be tested, sending a control signal to a temperature supply device and receiving a detection signal corresponding to the daughter board circuit board, the daughter board control device can independently burn-in test on the chip to be tested on the daughter board circuit board, wiring design on the daughter board circuit board is simplified, interference of wiring on signal transmission is reduced, and test requirements on different chips to be tested can be met through combination with different daughter board circuit boards.
Description
Technical Field
The application relates to a chip aging test, in particular to an seed board control device and an aging daughter board.
Background
The burn-in test is non-destructive tests which only induce circuits with potential defects and do not cause new failure mechanisms or change failure distribution of the circuits after integral screening, and if the burn-in test is not performed, many semiconductor finished products have many problems in the using process due to defects of devices, manufacturing processes and the like.
In the related technology, a plurality of chips to be tested are placed on the same burn-in board, the burn-in boards are placed in a burn-in incubator to be heated in a system , and the burn-in boards are connected with a power supply outside the burn-in incubator and a functional circuit through a high-temperature-resistant connector and a high-temperature-resistant lead, so that the connection relationship of the leads among the boards is complex, unstable and easy to make mistakes, signal transmission is interfered, the requirements of independent control cannot be met aiming at different chips to be tested, and the compatibility is poor.
SUMMERY OF THE UTILITY MODEL
In view of this, the present application provides an seed board control device and a burn-in board, which aim to implement independent control on a chip to be tested.
The technical scheme of the embodiment of the application is realized as follows:
, the embodiment of the present application provides a daughter board control device for individually controlling chips to be tested disposed on a daughter board circuit board, wherein the daughter board circuit board is provided with a temperature supply device for providing a burn-in temperature environment for the chips to be tested, the daughter board control device includes a control circuit board for being mounted on the daughter board circuit board and electrically connected to the daughter board circuit board, and a controller disposed on the control circuit board for sending an excitation signal to the corresponding chips to be tested, sending a control signal to the temperature supply device, and receiving a corresponding detection signal sent by the daughter board circuit board.
In a second aspect, an embodiment of the present application provides types of aging daughter boards, which include a daughter board circuit board, where the daughter board circuit board is provided with a interface circuit and a second interface circuit, the interface circuit is used to connect to a chip to be tested, the second interface circuit is used to connect to a temperature supply device, and the daughter board circuit board is provided with the daughter board control device according to any of the aforementioned embodiments .
In the technical scheme provided by the embodiment of the application, the daughter board control device is arranged on the daughter board circuit board through the control circuit board, and the daughter board control device has expansibility, universality and recoverability; the daughter board control device can be combined with different daughter board circuit boards so as to meet the test requirements of different chips to be tested; the daughter board control device adopts a plug-in modular design, so that the wiring design on the daughter board circuit board is simplified, the interference of wiring on signal transmission is reduced, and the daughter board control device can be recycled.
Drawings
FIG. 1 is a schematic diagram of a daughter board circuit board according to an embodiment of the present application ;
FIG. 2 is a schematic structural diagram of a daughter board control apparatus according to an embodiment of the present application ;
FIG. 3 is a schematic diagram of a mill run in an embodiment of the present application .
Detailed Description
The present invention is further described in the detailed description with reference to the drawings and the detailed description, it is to be understood that the embodiments are provided solely for the purpose of illustration and not as a definition of the limits of the application.
The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application, the terminology used herein "and/or" includes any and all combinations of or more of the associated listed items.
Referring to fig. 1, a th mounting area 111 for mounting the daughter board control device, a second mounting area 112 for mounting a burn-in socket, and a th connector 12 for electrically connecting with a motherboard circuit board are arranged on a daughter board circuit board 11, or more daughter board circuit boards 11 may be arranged on the motherboard circuit board in , a chip to be tested is mounted on the daughter board circuit board 11 through the burn-in socket, a containing area for containing the chip to be tested and a pogo pin socket located at the bottom of the burn-in socket are arranged in the burn-in socket, the pogo pin of the pogo pin socket corresponds to a pin of the chip to be tested, a th interface circuit (not shown) for connecting with the chip to be tested is arranged in the burn-in socket, the th interface circuit includes contacts corresponding to the pogo pins of the chip to be tested, after the chip to be tested is mounted, the pins of the chip to be tested are connected with the second interface circuit 8678 on the daughter board circuit board 11 through springs, and the burn-in socket is used for providing a temperature for the burn-in-test circuit board, and the burn-in-test device, and the burn-in-temperature-to-test-to-test-to-test-to.
In the embodiment of the present application, please refer to fig. 2 in combination, the daughter board control apparatus 2 includes: a control circuit board 21 mounted on the daughter board circuit board 11 and electrically connected to the daughter board circuit board 11; and the controller is arranged on the control circuit board 21 and used for sending an excitation signal to the chip to be tested, sending a control signal to the temperature supply device and receiving a detection signal corresponding to the daughter board circuit board. The controller controls the temperature supply device to provide proper aging temperature for the chips to be tested in the aging seat through the control signal, so that the chips to be tested are independently heated, the controller sends an excitation signal to control the internal units of the chips to be tested to work at the corresponding aging temperature, and receives a detection signal corresponding to the daughter board circuit board 11, and then the working state corresponding to the chips to be tested on the daughter board circuit board 11 is determined.
In this embodiment, the daughter board control device 2 is installed on the daughter board circuit board 11 through the control circuit board 21, and the daughter board control device 2 can independently perform burn-in test on the chip to be tested on the daughter board circuit board 11 and can independently control the chip to be tested. Through the combination with different daughter board circuit boards, can satisfy the test demand to the chip that awaits measuring of difference. When the daughter board circuit board 11 or the daughter board control device 2 fails, only the failed part needs to be replaced, which is convenient for maintenance.
In some embodiments , the controller disposed on the control Circuit board 21 includes a field programmable array FPGA22, a microprocessor MCU23, the control Circuit board 21 is disposed with a second connector 24, the control Circuit board 21 is electrically connected to the daughter board Circuit board 11 through the second connector 24, the FPGA22 is communicatively connected to the daughter board Circuit board 11, the MCU23 is communicatively connected to both the FPGA22 and the daughter board Circuit board 11, the MCU23 is configured to control the daughter board Circuit board 11, receive the control signal sent by the FPGA22, control the working state of the temperature supply device, control the power-on sequence of the chip to be tested, receive the detection signal corresponding to the daughter board Circuit board 11 and upload the FPGA22, the FPGA22 is configured to send a stimulus signal to the corresponding chip to be tested to control the internal unit of the chip to be tested to work, determine the Test result corresponding to the chip to be tested according to the output signal corresponding to the internal unit of the JTAG chip under the stimulus signal, send the control signal to the MCU23 and receive the detection signal corresponding to the daughter board Circuit 11 through the JTAG chip to be tested, the CPU chip as the chip to be tested, the CPU 22 loads the stimulus signal, and receives the Test result of the CPU chip under the CPU interface, the CPU interface, the read and read the CPU interface, the CPU, the interface.
The MCU23 communicates with the FPGA22 through an SPI bus interface or a parallel communication interface, receives a control signal issued by the FPGA, and controls the working state of the daughter board circuit board according to the control signal, in embodiments, the FPGA22 issues the control signal according to control information sent by the motherboard circuit board, the control information includes or more of information such as a heating device for starting and stopping the burn-in base, a heat dissipation device for starting and stopping the burn-in base, single CPU shell temperature offset (base temperature) setting, whole cabinet CPU shell temperature offset (offset temperature) setting and the like, the MCU23 also receives a detection signal corresponding to the daughter board circuit board and uploads the detection signal to the FPGA22, and the working state corresponding to a chip to be tested on the daughter board circuit board 11 is further determined.
By adopting the working mode of the cooperation of the MCU and the FPGA, the MCU can realize the data configuration of the FPGA, thereby saving a configuration storage circuit of the FPGA, simplifying the circuit and saving the hardware cost.
The control circuit board 21 is further provided with a power circuit 25, the power circuit 25 obtains the direct current power provided by the daughter board 11 through the second connector 24, and converts the direct current power into a suitable working voltage to supply the suitable working voltage to the FPGA22 and the MCU23, in embodiment, the power circuit 25 converts the direct current DC12V power to output DC3V3 and dc1v2, optionally, the control circuit board 21 is provided with a DC12V debugging power interface 251 to facilitate individual debugging of the daughter board control devices.
In embodiments, the daughter board control device 2 further includes a voltage sampling module 26, where the voltage sampling module 26 is connected to the MCU23 and is configured to detect a working voltage of the chip to be tested and transmit the working voltage to the MCU 23. in the related art, a burn-in test performs a high temperature test on the chip first, and then tests an electrical characteristic of the chip, so that an influence of a high temperature environment on a working performance of the chip cannot be determined.
In , the daughter board circuit board is provided with a temperature sensor, and the daughter board control device further includes an analog-to-digital converter 29, where the analog-to-digital converter 29 is connected to the MCU23 and is configured to convert a sensing signal collected by the temperature sensor into a digital signal and transmit the digital signal to the MCU23, it should be noted that the MCU23 may control the temperature supply device according to a control signal, and optionally, the MCU23 may further control the temperature supply device according to the temperature collected by the temperature sensor.
In , the temperature supply device includes a heating device corresponding to the chip to be tested, the daughter board control device includes a heating control unit 27 connected to the controller for controlling the operating state of the heating device, the heating control unit 27 is connected to the MCU23, the heating control unit 27 may be a MOS transistor or other switching circuit, and the heating control unit 27 sends a heating control signal to control the operation of the heating device according to a heating enable signal (EN) sent by the MCU23, optionally, the MCU23 compares the set temperature threshold with the temperature detected by the temperature sensor, and generates a heating enable signal according to the comparison result, thereby implementing the control of the heating device.
In embodiments, optionally, the temperature supply device further includes a heat dissipation device corresponding to the chip to be tested, the daughter board control device further includes a heat dissipation control unit 28 connected to the controller for controlling an operating state of the heat dissipation device, the heat dissipation control unit 28 is connected to the MCU23, the heat dissipation control unit 28 may be a MOS transistor or another switch circuit, and the heat dissipation control unit 28 sends a heat dissipation control signal to control the operation of the heat dissipation device according to a heat dissipation enable signal (EN) sent by the MCU23, and optionally, the MCU23 compares a set second temperature threshold with a temperature detected by the temperature sensor, and generates a heat dissipation enable signal according to a comparison result, thereby implementing control of the heat dissipation device.
In embodiments, the FPGA22 has operating voltages of DC3V3 and DC1V2, the FPGA is powered by the power supply circuit 25, the FPGA22 downloads a developed and debugged FPGA program through JTAG, the FPGA22 can generate a clock signal CLK by the MCU23 and can also generate a clock by an external reserved crystal oscillator, the FPGA22 can generate a reset signal RST by the MCU23 and can also be reset manually by the outside, the FPGA22 is connected with a configuration circuit and is used for pulling up or pulling down pins necessary for normal operation of the FPGA according to an FPGA user manual, the FPGA22 receives control of the FPGA configuration pins by the MCU23, the FPGA22 can be connected with a Flash memory, after the FPGA22 is normally powered on, the MCU23 sends a clock signal (CLK) and a Reset Signal (RST) to the FPGA22, and the FPGA22 reads the FPGA configuration file from the Flash memory through an SPI bus interface and loads the FPGA configuration file into the FPGA 22.
In , optionally, the daughter board control device further includes a indicator lamp 221, a indicator lamp 221 connected to the FPGA22 for indicating an operating state of the FPGA22, specifically, when the program loading of the FPGA22 is completed, the DONE pin outputs a high level, the program loading indicator lamp is turned on, when the FPGA22 operates normally, the smart pin outputs a low level, and the operating state indicator lamp is turned on.
In , the FPGA22 transmits the detection information corresponding to the chip to be tested to the burn-in motherboard via 4 pairs of high-speed differential signals (CLK P/N, CS P/N, DI P/N, DO P/N), the detection information including or more of information such as chip shell temperature, test result of whether the chip is working normally, chip operating voltage, ambient temperature of the burn-in socket, etc. the FPGA22 outputs the excitation signal to the chip to be tested, for example, the excitation signal includes timing required by the chip to be tested, chip control signal, I/O pin excitation signal, and special pin excitation signal (I/O pins of the FPGA are all connected to the second connector 24, and pins for loading the excitation signal or receiving the chip output signal are reserved when testing different chips).
In , the FPGA22 receives control information of the burn-in motherboard via 4 pairs of high-speed differential signals, where the control information includes information such as a heating device for starting and stopping the burn-in socket, a heat dissipation device for starting and stopping the burn-in socket, a single chip shell temperature offset (base temperature) setting, and a chip shell temperature offset (offset temperature) setting of the entire cabinet, and the FPGA22 issues a control signal to the MCU23 according to the control information.
The FPGA22 is communicated with the MCU23 through an SPI bus interface or a parallel communication interface, receives detection signals corresponding to the daughter board circuit board acquired by the MCU, wherein the detection signals comprise or more of information such as chip shell temperature, working voltage of a chip, ambient temperature of a burn-in seat and the like, the FPGA22 receives output signals of an I/O pin and a special pin of the chip, processes and analyzes the output signals, judges whether functions of internal units of the chip are normal or not, and further obtains a test result whether the internal units of the chip are normal or not.
In , the power circuit 25 provides the MCU23 with DC3V3 working power, the MCU23 generates a clock from an internal crystal oscillator, an external crystal oscillator is reserved, the MCU23 supports external manual reset and dog software reset, the MCU23 downloads and updates an MCU program through a serial port (UART) to meet the control requirements of different burn-in tests, and optionally, the MCU23 can control the configuration pins of the FPGA 22.
The MCU23 communicates with the FPGA22 through an SPI bus interface or a parallel communication interface and transmits acquired detection signals corresponding to the daughter board circuit board to the FPGA22, wherein the detection signals corresponding to the daughter board circuit board comprise or more of information such as chip shell temperature, whether the chip works normally, working voltage of the chip, ambient temperature around an aging seat and the like.
The MCU23 is communicated with the FPGA22 through an SPI bus interface or a parallel communication interface, and controls the working state of the daughter board circuit board after receiving control information of the daughter board circuit board from the motherboard circuit board, wherein the control information comprises or more of information such as a heating device for starting and stopping the aging seat, a heat dissipation device for starting and stopping the aging seat, a single CPU shell temperature offset (base temperature) and an offset (offset temperature) of the CPU shell of the whole cabinet.
The MCU23 controls the working state of the voltage sampling module 26 through the SPI bus, receives the working voltage of the chip collected by the voltage sampling module 26 and judges whether the working voltage is normal or not. The MCU23 transmits the real-time voltage and the judgment result to the FPGA22 through the SPI bus or a parallel communication interface. The MCU23 resets the signal and/or control module logic output to the voltage sampling module 26.
The MCU23 can compare the temperature information collected in real time with the aging temperature range set by the user, and send heating enabling signals to the heating control unit according to different conditions. When the temperature of the chip shell is lower than the temperature set by a user, the MCU23 sends an effective enabling signal to the heating control unit, and the heating device heats at constant temperature. When the temperature of the chip shell is more than or equal to the temperature set by the user or the environmental temperature is more than 85 ℃, the MCU23 sends an invalid enabling signal to the heating control unit, and the heating device stops heating.
The MCU23 can send a heat dissipation enabling signal to the heat dissipation control unit to control the operating state of the heat dissipation device. For example, taking the cooling fan as an example, when the temperature of the chip shell is greater than or equal to the upper limit of the cooling temperature set by the user, the MCU23 sends a cooling effect enable signal to the cooling control unit, and the cooling fan on the burn-in seat rotates; when the temperature is lower than the lower limit of the heat dissipation temperature set by the user, the MCU23 sends an invalid enable signal to the heat dissipation control unit, and the heat dissipation fan on the aging base stops rotating.
In embodiments, the daughter board control device optionally further comprises a second indicator light 231 connected to the MCU23 for indicating the operating status of the chip to be tested, specifically, the second indicator light 231 may comprise or more of an operation indicator light, a HEATING indicator light, a SAMPLING indicator light, a power-on indicator light, a temperature indicator light, and a self-test indicator light, for example, the chip operates normally, the ALIVE pin outputs a low level, the operation indicator light is on, the HEATING device is HEATING, the HEATING pin outputs a low level, the HEATING indicator light is on, the voltage SAMPLING module operates normally, the SAMPLING pin outputs a low level, the SAMPLING indicator light is on, the chip is powered on, the PWRGOOD pin outputs a low level, the power-on indicator light is on, the chip temperature is within a user-specified temperature range, the TEMPOK pin outputs a low level, the temperature indicator light is on, the burn system self-test is completed, the DEBUG pin outputs a low level, and the self-test indicator light is on.
In , the control circuit board 21 has a plurality of fixing holes 211, such as a plurality of fixing holes 211, formed on the periphery of the control circuit board, and the control circuit board 21 is fixed on the -th mounting region 111 of the daughter board 11 through the fixing holes 211.
The embodiment of the present application further provides types of hardened daughter boards, please refer to fig. 3, where the hardened daughter board 1 includes a daughter board circuit board 11, the daughter board circuit board 11 is provided with a th interface circuit and a second interface circuit, the th interface circuit is connected to a chip to be tested, the second interface circuit is connected to a temperature supply device, and the daughter board circuit board 11 is provided with the daughter board control device according to any of the embodiments .
Specifically, referring to fig. 1 again, the daughter board circuit board 11 is provided with a th mounting area 111 for mounting the daughter board control device 2, a second mounting area 112 for mounting the burn-in socket, and a th connector 12 for electrically connecting with the mother board circuit board, which may be or more daughter board circuit boards 11.
Referring to fig. 3, in the embodiment, a chip to be tested is mounted on a daughter board circuit board 11 through a burn-in socket 3, a receiving area for receiving the chip to be tested and a pogo pin socket located at the bottom of the burn-in socket are disposed in the burn-in socket 3, the pogo pin of the pogo pin socket corresponds to the pin of the chip to be tested, a second mounting area 112 is disposed with a interface circuit (not shown) connected to the chip to be tested, the interface circuit includes contacts corresponding to the pogo pins of the pogo pin socket, after the chip to be tested is mounted in place, the pin of the chip to be tested is connected to a interface circuit on the daughter board circuit board 11 through the pogo pin socket, a temperature supply device for providing a burn-in temperature environment for the chip to be tested is further disposed on the burn-in socket 3, and a second interface circuit (not shown) is disposed on the second mounting area 112, and the temperature supply device is connected to the daughter board.
The daughter board control device 2 receives control information transmitted by the daughter board circuit board 11 through 4 pairs of high-speed differential signals (CLK P/N, CS P/N, DIP/N, DO P/N) (the control information can be sent by the aging motherboard and transmitted through the daughter board circuit board 11), the control information comprises or more of information such as a heating device for starting and stopping the aging base, a heat dissipation device for starting and stopping the aging base, a single chip shell temperature offset (base temperature), a chip shell temperature offset (fset temperature) of the whole cabinet and the like, the daughter board control device 2 sends a control signal to the aging base 3 according to the control information, for example, the daughter board control device 2 sends a heating control signal to the heating device on the aging base or the heat dissipation control signal to the heat dissipation device on the aging base, the excitation control device 2 sends a corresponding signal to the aging base or the excitation signal to the chip on the aging base, and generates corresponding detection information of the aging chip, namely, the normal detection result of the aging base, the CPU, the excitation signal 633, and the corresponding detection result of the aging base, the chip, and the detection result of the aging base, wherein the aging base, the excitation signal, and the excitation signal of the excitation chip, and the excitation signal of the excitation of the aging base, and the chip are detected by the chip, and the excitation signal of.
This embodiment smelts the daughter board through with the combination of smelting the mother board always, sets up a plurality of daughter boards always on mother board circuit board, can realize the test of smelting alone heating and synchronous ageing of a plurality of chips that await measuring, and through carrying out independent control, mutual noninterference to each chip, can be according to the nuance real-time adjustment of the discrete consumption of every chip test temperature that smelts.
Optionally, the temperature supply device further comprises a heat dissipation device corresponding to the chip to be tested, and the heat dissipation device can be a heat dissipation fan arranged in the aging base, and the working state of the heat dissipation fan is controlled through the daughter board device, so that the control precision of the aging temperature is improved.
In embodiments, the burn-in daughter board further includes a temperature sensor electrically connected to the daughter board circuit board for detecting a shell temperature corresponding to the chip to be tested, optionally, the temperature sensor is disposed in the accommodation of the burn-in base for detecting a chip shell temperature corresponding to the chip to be tested, in embodiments, the burn-in daughter board further includes a temperature acquisition chip for detecting an ambient temperature around the burn-in base, the temperature sensor and the temperature acquisition chip are used for synchronously monitoring the chip shell temperature and the ambient temperature around the burn-in base, the daughter board circuit board 11 is provided with a temperature acquisition circuit 15, the temperature sensor acquires the chip shell temperature and/or the ambient temperature around the burn-in base in real time and converts the temperature into a thermoelectric force, and the thermoelectric force is transmitted to the temperature acquisition circuit 15 on the daughter board circuit board, and the temperature acquisition circuit 15 transmits the thermoelectric force acquired by the temperature sensor to the daughter board control device 2 through filtering processing, so that the daughter board control device 2 generates a control signal according to the temperature signal.
In this embodiment, a daughter board circuit board 11 is provided with a power module 13, the power module 13 receives a direct current power provided by a mother board circuit board and supplies the converted direct current power to a daughter board control device 2, the daughter board circuit board 11 is provided with a power interface 16, the power interface 16 receives the direct current power provided by the mother board circuit board and supplies the converted direct current power to a burn-in stand 3, optionally, the power module 13 adopts a DC-DC power module, in the example, the power module 13 includes 6 paths of DC-DC power modules, wherein, 5 paths of the power modules are 12V input and 0.8V-17V/6A output, and the other 1 path of the power modules are 12V input and 0.7V-3.6V/30A output to supply power to a core power of a chip.
In , optionally, a voltage observation point 14 for detecting the operating voltage of the chip to be tested is provided on the daughter board circuit 11, the operating voltage of the chip to be tested can be detected by cooperating with the voltage observation point 14 on the daughter board circuit 11 through a measurement device such as an oscilloscope, in addition to being automatically detected by the daughter board control device, so as to facilitate manual detection and verification of whether the operating voltage of the chip to be tested is normal.
In , the daughter board circuit board 11 further has a plurality of second fixing holes 113, for example, a plurality of second fixing holes 113 opened on the periphery of the daughter board circuit board 11, and the daughter board circuit board 11 is fixed to the mother board circuit board through the second fixing holes 113.
The chip to be tested in the embodiment of the application can be a CPU chip or an integrated circuit chip, and the daughter board control device is arranged on the daughter board circuit board and can independently conduct aging test on the chip to be tested on the daughter board circuit board, so that the wiring design on the daughter board circuit board is simplified, the interference of wiring on signal transmission is reduced, and the test requirements on different chips to be tested can be met through the combination with different daughter board circuit boards.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
- The utility model provides an seed board controlling means for to set up the chip that awaits measuring on the daughter board circuit board and control, set up on the daughter board circuit board and be used for the chip that awaits measuring provides the temperature supply device who smelts the temperature environment always, its characterized in that, daughter board controlling means includes:the control circuit board is used for being mounted on the daughter board circuit board and electrically connected with the daughter board circuit board;and the controller is arranged on the control circuit board and used for sending an excitation signal to the corresponding chip to be tested, sending a control signal to the temperature supply device and receiving a corresponding detection signal sent by the daughter board circuit board.
- 2. The daughter board control apparatus as claimed in claim 1, wherein said controller comprises:the field programmable array FPGA is in communication connection with the daughter board circuit board;the microprocessor MCU is in communication connection with the FPGA and the daughter board circuit board;the FPGA is used for sending the excitation signal to the corresponding chip to be tested so as to control the internal unit of the chip to be tested to work, the testing result corresponding to the chip to be tested is determined according to the output signal corresponding to the internal unit of the chip to be tested under the excitation signal, the MCU is used for receiving the control signal sent by the FPGA, controlling the working state of the temperature supply device according to the control signal, receiving the detection signal corresponding to the daughter board circuit board and uploading the detection signal to the FPGA.
- 3. The daughter board control apparatus as claimed in claim 2, wherein said detection signal includes an operating voltage of said chip to be tested, said daughter board control apparatus further comprising:and the voltage sampling module is connected with the MCU and used for detecting the working voltage of the chip to be tested and transmitting the working voltage to the MCU.
- 4. The daughter board control apparatus as claimed in claim 2, wherein said daughter board control apparatus further comprises:indicator light connected with the FPGA for indicating the working state of the FPGA and/or,and the second indicator light is connected with the MCU and used for indicating the working state of the chip to be tested.
- 5. The daughter board control apparatus as claimed in claim 2, wherein a temperature sensor is provided on said daughter board circuit board, said daughter board control apparatus further comprising:and the analog-to-digital converter is connected with the MCU and used for converting the sensing signals acquired by the temperature sensor into digital signals and transmitting the digital signals to the MCU.
- 6. The daughter board control apparatus as claimed in claim 1, wherein said temperature supplying means includes a heating means corresponding to said chip to be tested; the daughter board control apparatus includes:and the heating control unit is connected with the controller and is used for controlling the working state of the heating device.
- 7. The daughter board control apparatus as claimed in claim 6, wherein said temperature supplying means further comprises a heat sink corresponding to said chip to be tested; the daughter board control apparatus further includes:and the heat dissipation control unit is connected with the controller and used for controlling the working state of the heat dissipation device.
- The aging daughter board is characterized by comprising a daughter board circuit board, wherein a th interface circuit and a second interface circuit are arranged on the daughter board circuit board, the th interface circuit is used for connecting a chip to be tested, the second interface circuit is used for connecting a temperature supply device, and a daughter board control device as claimed in any of claims 1 to 7 is arranged on the daughter board circuit board.
- 9. The aging daughterboard as defined in claim 8, further comprising: and the temperature sensor is electrically connected with the daughter board circuit board and is used for detecting the shell temperature corresponding to the chip to be tested.
- 10. The aging daughter board of claim 8, wherein a voltage observation point for detecting an operating voltage of the chip to be tested is provided on the daughter board circuit board.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201920245812.0U CN210005638U (en) | 2019-02-26 | 2019-02-26 | Daughter board control device and burn-in daughter board |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920245812.0U CN210005638U (en) | 2019-02-26 | 2019-02-26 | Daughter board control device and burn-in daughter board |
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| CN210005638U true CN210005638U (en) | 2020-01-31 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114076859A (en) * | 2020-08-18 | 2022-02-22 | 中国科学院国家空间科学中心 | Full-temperature aging test system and method for core components for aerospace |
| CN117214676A (en) * | 2023-11-09 | 2023-12-12 | 成都梓峡信息技术有限公司 | FPGA aging test system |
-
2019
- 2019-02-26 CN CN201920245812.0U patent/CN210005638U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114076859A (en) * | 2020-08-18 | 2022-02-22 | 中国科学院国家空间科学中心 | Full-temperature aging test system and method for core components for aerospace |
| CN117214676A (en) * | 2023-11-09 | 2023-12-12 | 成都梓峡信息技术有限公司 | FPGA aging test system |
| CN117214676B (en) * | 2023-11-09 | 2024-01-23 | 成都梓峡信息技术有限公司 | FPGA aging test system |
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