CN209929298U - 芯片封装 - Google Patents
芯片封装 Download PDFInfo
- Publication number
- CN209929298U CN209929298U CN201920232454.XU CN201920232454U CN209929298U CN 209929298 U CN209929298 U CN 209929298U CN 201920232454 U CN201920232454 U CN 201920232454U CN 209929298 U CN209929298 U CN 209929298U
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- die
- signal transmission
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- transmission line
- chip package
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- 230000008054 signal transmission Effects 0.000 claims abstract description 122
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910052802 copper Inorganic materials 0.000 claims abstract description 33
- 239000010949 copper Substances 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 238000004806 packaging method and process Methods 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 abstract description 14
- 230000010355 oscillation Effects 0.000 abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 229910052710 silicon Inorganic materials 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- 238000004519 manufacturing process Methods 0.000 description 9
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- 238000000034 method Methods 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 239000011733 molybdenum Substances 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 229910000881 Cu alloy Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 3
- 229910001092 metal group alloy Inorganic materials 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 239000011295 pitch Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- BWWVXHRLMPBDCK-UHFFFAOYSA-N 1,2,4-trichloro-5-(2,6-dichlorophenyl)benzene Chemical compound C1=C(Cl)C(Cl)=CC(Cl)=C1C1=C(Cl)C=CC=C1Cl BWWVXHRLMPBDCK-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000007334 memory performance Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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Abstract
本文描述了芯片封装。所述芯片封装包括具有裸片间区域的高速数据传输线,信号传输线通过该裸片区域将第一裸片耦合到第二裸片。所述信号传输线具有的电阻值大于铜线的等效基础电阻值(EBR),这减小了传输线内的振荡。
Description
技术领域
本实用新型的实施例总体涉及芯片封装和具有该芯片封装的电子设备。具体地,涉及被形成在薄的有机再分布层中的高速裸片间连接接口,该有机再分布层被设置在芯片封装和电子设备的部件之间,用于提供部件之间的高速数据信号通信。
背景技术
电子设备,例如平板电脑、计算机、服务器、室内电信、室外电信、工业计算机、高性能计算数据中心、复印机、数码相机、智能电话、控制系统和自动柜员机等,通常采用利用芯片封装的电子部件,以增加功能和提高元件密度。传统的芯片封装包括一个或多个堆叠的组件,例如集成电路(IC)裸片、穿硅通孔(TSV)中介层,和封装基片,芯片封装本身堆叠在印刷电路板(PCB)上。IC裸片可以包括存储器、逻辑、MEMS、RF或其他IC器件。
具有硅基片的硅中介层特别有利于在封装内的IC裸片之间形成高速互连,这是由于精细的导体尺寸以及可以使用公知且可靠的半导体制造技术制造出的间距。然而,一些封装已经替换了硅中介层,而将芯片互连形成在无硅基片的再分布层(siliconsubstrate-less redistribution layer)中。传统的再分布层通常由堆叠的有机介电材料层制成,所述有机介电材料层分隔形成互连的铜线。然而,传统的再分布层制造技术不能实现在使用硅中介层时有利地获得精细的线宽和小的线间距。后果是,在薄的有机再分布层中形成的IC裸片之间的高速互连经常遭受不期望的振荡和串扰,这与材料损耗明显更高的硅中介层相反。
因此,需要一种具有改进的再分布层的芯片封装,该芯片封装在芯片封装的裸片之间提供高速的裸片间连接接口,与现有技术中常规可用的相比,其可以提高数据传输性能。
实用新型内容
本实用新型内容的实施例大体上提供芯片封装及其制造方法。与具有薄的有机中介层的传统封装相比,该芯片封装具有改进的高速数据传输性能,并且在将逻辑和(高带宽)存储器裸片共同封装到存储器设备中时特别有用。
在一个示例中,提供了一种芯片封装,其包括第一裸片、第二裸片、封装基片,和被安装在封装基片上的再分布层(RDL)。所述RDL具有连接所述第一裸片和所述第二裸片的信号传输接口。信号传输接口包括具有裸片间部分的信号传输线。信号传输线的电阻值大于铜线的等效基础电阻值。
示例可包括一个或多个以下特征:
所述信号传输线的裸片间部分具有非线性路径,所述非线性路径被限定为跨过在第二裸片和第一裸片之间限定的裸片间区域。所述信号传输线具有的电阻率大于铜的电阻率。所述信号传输线包括电阻器。所述芯片封装还包括:在所述第二裸片和第一裸片的相对侧之间限定的裸片间区域,所述裸片间区域包括:在第二裸片和第一裸片之间延伸的、邻近被形成在第二裸片一侧处的信号传输焊盘的第一区域;和在第二裸片和第一裸片之间延伸的、邻近被形成在第二裸片一侧处的接地或电源焊盘的第二区域,所述信号传输线至少部分地被布置在第二区域内。所述信号传输线的裸片间部分具有非线性路径,所述非线性路径被限定为跨过在第二裸片和第一裸片之间限定的裸片间区域。所述信号传输线具有的电阻率大于铜的电阻率。所述信号传输线的裸片间部分被布置为相对于所述第二裸片面向所述第一裸片的一侧成非正交的角度。所述信号传输线的裸片间部分具有非线性路径,所述非线性路径被限定为跨过在第二裸片和第一裸片之间限定的裸片间区域所述信号传输线具有的电阻率大于铜的电阻率。所述信号传输线是被形成在包括信号传输接口的至少两个金属层上的第一组信号传输线的一部分。所述信号传输线是限定第一通道的第一组信号传输线的一部分,所述第一组信号传输线被形成在第一金属层上;以及其中限定第二通道的第二组信号传输线被形成在第一金属层下面的第二金属层上的所述信号传输接口中。
在另一示例中,提供了一种芯片封装,其包括逻辑裸片、存储器裸片的堆叠、封装基片、在所述逻辑裸片和所述存储器裸片的堆叠之间限定的裸片间区域,以及被安装在封装基片上的再分布层(RDL)。所述裸片间区域包括在逻辑裸片和存储器裸片之间延伸、并邻近形成在逻辑裸片一侧的信号传输焊盘的第一区域,裸片间区域还包括在逻辑裸片和存储器裸片之间延伸、并邻近形成在逻辑裸片一侧的接地或电源焊盘的第二区域。所述RDL具有信号传输接口,其跨过所述裸片区域将逻辑裸片与存储器裸片的堆叠相连接。所述接口包括具有裸片间部分的第一信号传输线。所述第一信号传输线的电阻值大于铜线的等效基础电阻值。所述第一信号传输线至少部分被设置在第二区域内。
示例可包括一个或多个以下特征:
所述第一信号传输线的裸片间部分具有非线性路径,所述非线性路径被限定为跨过所述裸片间区域。所述第一信号传输线具有的电阻率大于铜的电阻率。所述第一信号传输线包括电阻器。所述信号传输接口还包括:具有裸片间部分的第二信号传输线,所述第一信号传输线的裸片间部分和所述第二信号传输线的裸片间部分被布置在所述信号传输接口的不同的层上。
在又一个示例中,提供了一种用于形成芯片封装的方法。该方法包括将一个或多个逻辑裸片和一个或多个存储器裸片堆叠安装在载体上;将所述裸片封装在模塑料中以保持存储器和逻辑裸片的位置取向和间隔;移除载体,在裸露焊盘下方形成再分布层并与裸露焊盘接触,所述再分布层包括高速信号传输接口,所述高速信号传输接口具有至少一条信号传输线,所述信号传输线的电阻值大于具有与信号传输线相同的平均截面积和长度的铜线的等效基础电阻值,所述铜线具有垂直地跨过在一个或多个逻辑裸片和一个或多个存储器裸片堆叠之间限定的裸片间区域延伸的裸片间部分;以及将再分布层电气地和机械地安装到封装基片上。
附图说明
为了能够详细地理解本实用新型的上述特征,通过参考实施例可以获得上面简要概述的本实用新型的更具体的描述,其中一些实施例在附图中显示。然而,应当看到,附图仅示出了本实用新型的典型实施例,因此不应视为限制本实用新型的范围,因为本实用新型还允许其他同等有效的实施例。
图1是被安装在印刷电路板上的集成电路芯片封装的横截面示意图。
图2是被形成在图1的芯片封装的再分布层中并且连接芯片封装的裸片的高速裸片间连接接口的侧面示意图。
图3-5是被形成在芯片封装的再分布层中并且连接芯片封装的裸片的裸片间连接接口的不同示例的顶部示意图。
图6-9是裸片间连接接口的一部分线的不同示例的示意图。
图10-11是被形成在连接芯片封装的裸片的再分布层的不同层中的裸片间连接接口的另一示例的顶部示意图。
图12是制造芯片封装的方法的流程图。
为了便于理解,在可能的情况下,使用相同的附图标记来表示附图中共有的相同元件。可以预期的是,一个实施例的元件可以有利地合并到其他实施例中。
具体实施方式
本公开内容的实施例大体上提供芯片封装和制造芯片封装的方法。与具有薄的有机中介层的传统封装相比,所述芯片封装具有改进的高速数据传输性能。所述芯片封装包括具有高速裸片间连接接口的再分布层。裸片间连接接口的线被配置为抑制振荡,因为振荡会不期望地引起噪声和功能变差。在一些示例中,与传统接口相比,裸片间连接接口的线间隔更远,因此有利地降低了串扰的可能性。上述改进在跨越短距离将第一裸片与第二裸片合并在一起的芯片封装中特别有用,例如在单个封装内具有与一个或多个逻辑裸片(诸如可编程门阵列(FPGA)裸片)通信的一个或多个HBM(高带宽存储器)裸片的应用中。
例如,基于硅的中介层(即,构建在硅基片上的中介层)通常通过利用成熟的硅通孔 (TSV)技术被用于具有HBM接口的芯片封装中。在许多下一代应用中,HBM接口中的基于硅的中介层正在被替换为不包括硅基片的再分布层,主要是为了降低制造成本。虽然硅中介层上的裸片到裸片接口有助于实现逻辑和存储器裸片之间的低延迟,这对于存储器性能是至关重要的,但是需要高的路径(routing)密度以便在有限的空间和层数内容纳大量信号输入输出(IO)。例如,在一些应用中,在两个或三个信号层上的6mm宽的空间中,大约1700个信号传输线必须从每个裸片中引出。
在传统的再分布层中,横截面尺寸的制造约束(例如迹线宽度和铜线厚度、线之间的间隙、介电层厚度、需要参考穿孔接地平面中(如果使用的话)等等)由用于实现接口的再分布层制造过程决定。结合起来,上述特性经常导致独特的串扰行为,这导致传统的再分布层表现不如硅中介层。
针对传统的再分布层,短信号线长度与驱动器复数值输出阻抗和接收器的电容性输入相组合,产生LCR槽路(tank)、欠阻尼的LC槽路谐振器(under-dampened LC-tankresonators),具有约为3-4GHz的自然的振荡频率。即使来自相邻干扰源信号的弱串扰激励也会导致平静的受害信号经历谐振振荡或振铃(ringing)。突破区域内相邻信号之间的耦合严重到足以将噪声容限降低到零。信号线中的电阻性损耗必须足以抑制这种振铃。在相对的裸片之间垂直布线的常规铜线通常不具有足够的电阻值来抑制振铃。因此,简单地将逻辑和存储器裸片用仅由DFM机械约束限制的直连接线进行连接将导致总线不能以目标数据速率操作。下面描述了本公开内容的示例,其减轻了上述不期望的振荡,并且在一些示例中,还有利地减少了信号线之间的串扰。
现在转到图1,示意性地示出了集成电路电子设备110,其具有被安装在印刷电路板 (PCB)102上的示例性集成电路芯片封装100。芯片封装100包括封装基片104,在封装基片104上安装一个或多个第一裸片106和一个或多个第二裸片108。模塑料(moldingcompound)142被设置在裸片106、108周围,以保持裸片106、108的位置取向和间隔。
至少一个第一裸片106通过设置在裸片106、108与封装基片104之间的再分布层(RDL)112中限定的一个或多个高速接口120与至少一个或多个第二裸片108通信。RDL 112由分开导电信号传输线的介电层组成,如下面进一步描述的。
尽管下面进一步描述了第一裸片106被配置为存储器裸片并且第二裸片108被配置为逻辑裸片的示例,但是本文所述的接口120和其他接口可以在任何通过再分布层连接的裸片之间被利用来减少振荡和减少在包括接口的导电信号传输线之间的串扰。因此,在下文中,第一裸片也被称为存储器裸片106,而第二裸片也被称为逻辑裸片108。
存储器裸片106被配置为高性能固态存储器设备,例如DRAM等。在图1中描绘的实施例中,尽管在单个堆叠中示出了3个存储器裸片106,但是存储器裸片106的堆叠可以包括不同数量的裸片106,并且封装100可以包括更多的存储器裸片106的堆叠。在一些示例中,堆叠中的存储器裸片106的数量可以是2、4、8、16或其他期望的数量。逻辑裸片108可以是可编程逻辑器件,例如现场可编程门阵列(FPGA)、图形处理单元(GPU)、专用集成电路(ASIC)、片上系统(SoC)、处理器或其他IC逻辑结构。逻辑裸片108 中的至少一个用作存储器裸片106的控制器。在图1所示的示例中,芯片封装100被配置为具有至少一个逻辑裸片108,其与具有至少一个存储器裸片106堆叠的高带宽存储器 (HBM)器件(例如DRAM)以FPGA形式共同封装。
在一个示例中,每个存储器裸片106包括固态存储器电路114(以虚线示出)。包括一个存储器裸片堆叠106的每个存储器裸片106的存储器电路114通过焊接连接116(例如微凸块)进行连接。存储器电路114可以包括允许通过裸片106的数据传输而同时绕过 (by-pass)电路114的数据存储元件的路径(routing)。底部存储器裸片106包括接触焊盘118。
接触焊盘118被电耦接到存储器裸片106的存储器电路114。接触焊盘118还电耦接到高速接口120,并且可选地电耦接到RDL 112内的其他电路(RDL)122。
类似地,逻辑裸片108包括固态逻辑电路124(以虚线示出)。逻辑裸片108的逻辑电路124端接(terminate)于接触焊盘126。接触焊盘126电耦接到高速接口120,并且可选地电耦接到RDL 112内的RDL电路122。
RDL 112内的RDL电路122端接于接触焊盘128。焊接连接130将RDL 112的接触焊盘128电耦接和机械地耦接到封装基片104的接触焊盘132。
封装基片104包括被耦接到接触焊盘132的封装电路134。封装电路134还端接于设置在封装基片104的相对侧上的接触焊盘136。
封装基片104的接触焊盘136电耦接和机械地耦接到PCB 102的接触焊盘144。PCB102的接触焊盘144被耦接到PCB电路140,PCB电路140被路由(route)到电子设备110 的其他封装、电源、接地或接口。
图2是在图1的芯片封装100的裸片106、108之间的RDL 112中形成的高速裸片间连接接口120的侧面示意图。在图2中,逻辑裸片108具有面向存储器裸片106的侧面204 的侧面202。侧面202、204具有基本上平行的平坦表面(面)。侧面202、204由裸片间区域206分开,接口120设置为穿过裸片间区域206。
接口120通常由被形成在包含RDL 112的介电材料层之间的多个导电信号传输线210 组成。适合于包含RDL 112的介电材料的示例包括SiO2、Si3N4等。根据下面进一步描述的选择标准,导电信号传输线210可以由铜、银、金、镍、钼、铝、氧化铟锡、铜合金和其他导电金属合金等形成。当导电信号传输线210被形成在RDL 112的不同层上时,接地层212可选地设置在线210之间。接地层212可以被耦接到逻辑裸片108的焊盘126,或者耦接到封装100的其他接地。在一个示例中,线210具有2.0μm的宽度和2.0μm的线间距。
接口120的导电信号传输线210被耦接在逻辑裸片108的焊盘126和设置在RDL 112上的存储器裸片106的焊盘118之间。每个导电信号传输线210的裸片下部分214驻留在裸片106、108下面。换句话说,每个导电信号传输线210的裸片下部分214不穿过裸片间区域206。裸片106、108下方的裸片下部分214通常限定线210的逃逸引出(escape fan-out),并且包括端接焊盘118、126的垂直部分(例如,通孔)和耦接垂直部分的水平部分,以及路由通过裸片间区域206的线210的裸片间部分218。线210的裸片间部分218 穿过裸片间区域206并且不在裸片106,108下方延伸。
包括裸片间部分218和裸片下部分214的线210具有平均截面积和电阻值。线210的电阻值大于等效基础电阻值(EBR)。EBR被定义为:具有与线210相同的平均截面积的铜线在25摄氏度时的电阻值,并具有端到端(即,焊盘126到焊盘118)的裸片间区域长度(包括在垂直于侧面202、204的方向上形成的长度延伸穿过裸片间区域206的长度)。线210可以以多种方式被配置成具有大于EBR的电阻,如下面进一步描述的,包括:选择包括线210的裸片下部分214和/或裸片间部分218的材料、选择穿过裸片间区域206的线 210的裸片间部分218的路径,以及添加电阻器等。
在图2中,两条线210被显示为在RDL 112的分离层上,例如第一金属层230和第三金属层250。然而,线210可以可替换地分布在包括RDL 112的任何一个或多个层上,例如,3、4、5甚至6个或更多的层。在图2中,接地层212被设置在第二金属层240上,第二金属层240被设置在第一和第三金属层230、250之间,以便在位于第一和第三金属层230、250中的线210之间提供屏蔽。在一个示例中,接口120具有被用于信号传输线 210的路径的RDL 112的多个层,包括每个信道的线210可以被设置在分开的层上,例如,第一信道将它全部的传输线210路径设置在第一层230,以及第二通道将它全部的传输线 210路径设置在第三层250。
图3-5是在芯片封装的裸片之间的再分布层中形成的裸片间连接接口的不同示例的顶部示意图。首先转到图3中描绘的示例,多个接触焊盘126沿着面向存储器裸片108的逻辑裸片108的侧面202的边缘被示出。图3中示出的接触焊盘126的数量仅仅用于说明的目的,因为实际的实施方案将不同,通常具有分布在多行中的更多焊盘216。一些接触焊盘126包含“X”并且用附图标号312标识,以表示接触焊盘312是用于接地或电源之一。不包含“X”的接触焊盘126用附图标号314标识,以表示焊盘314用于信号传输。成组的信号传输焊盘314通常由在侧面202的边缘处的一个或多个接地或电源焊盘312区分开。一组或多组信号传输焊盘314被配置为服务于逻辑电路124的通道,例如,一组32个焊盘包括32比特通道。
裸片间区域206可被解析成不同区域,以对应于接地或电源焊盘312的存在以及信号传输焊盘314的存在。例如,在逻辑裸片108的接地或电源焊盘312和存储器裸片106的接地或电源焊盘118(由“X”表示)之间延伸的裸片间区域206限定第一区域302。类似地,在逻辑裸片108的传输焊盘314和存储器裸片106的接触焊盘118(由不具有“X”表示)之间延伸的裸片间区域206限定第二区域304。区域302、304的数量可以根据焊盘312、314 的布局而变化。
在图3所示的示例中,每条线210的裸片间部分218保留在与传输焊盘314相关联的第一区域302中,线210从传输焊盘314发源,通常以垂直于裸片间部分218的侧面202 的直线路径越过裸片间区域206延伸。因此,线210的裸片间部分218不会穿过第二区域 304。
如上所述,线210具有的电阻值大于具有与线210平均截面积相同的包括在垂直于侧面202、204的方向上的以及延伸穿过裸片间区域206的裸片间部分的端到端(即,焊盘126到焊盘118)的长度的铜线的EBR。在一些示例中,仅线210的裸片间部分具有大于 EBR的电阻值。为了实现该电阻,选择裸片下部分214、裸片间部分218、或整个线210 的材料以具有大于铜的电阻。因此,用于线210的合适材料不包括纯铜和银,而是包括金、镍、钼、铝和氧化铟锡等。也可以使用具有大于纯铜的电阻率的铜的合金和其他金属合金。
与传统的信号总线(即,具有等于EBR的电阻的线)相比,线210的增加的电阻值有利地抑制了由相邻线内的切换所引起的振荡。因此,接口120的性能更稳健可靠,从而改善了芯片封装100以及最终产品电子设备110的性能。
图4是可被形成在芯片封装100的裸片106、108之间的RDL 112中的裸片间连接接口420的另一配置的顶部示意图。接口420的配置基本上与芯片封装100的裸片106、108 相同,除了其中通过包括被布置成与线210串联的一个或多个电阻器402,线210的电阻值大于具有与线210相同的平均截面积并且具有包括端到端(即,焊盘126至焊盘118) 的长度(包括沿垂直于侧面202、204的方向限定的长度以及延伸越过裸片间区域206的裸片间部分的长度)铜线的EBR之外。虽然电阻器402被显示为与线210的裸片间部分 218相接,但电阻器402替代地可以与线210的裸片下部分214相接,或者与线210的裸片下部分和裸片间部分214、218之间的接口相接。
电阻器402可以是点电阻器或其他合适的电阻器。点电阻器通常是与线210串联设置的材料,其电阻率大于包括线210的材料的电阻率。例如,线210可以由铜制成,而点电阻器402可以由钼制成。
图3中所示的接口420的线210通常保留在第一区域302中。另外,尽管不是必需的,但线210的裸片间部分218通常以垂直于逻辑裸片108的侧面202的直线路径延伸穿过裸片间区域206。
图5是裸片间连接接口520的另一配置的俯视示意图,其可被形成在芯片封装100的裸片106、108之间的RDL 112中。接口520被配置成基本上与上述接口120相同,除了其中一些线210具有被完全或至少部分地设置在第二区域304之内的裸片间部分218。
例如,如图5所示,线210至少发源自最靠近电源或接地焊盘312的传输焊盘314而横向地(即,沿平行于侧面202的面的方向)行进,使得至少线210的裸片间部分218中的一些或全部延伸到第二区域304中。结果,线210的裸片间部分218具有更大的间隔,有利地降低了线210之间的串扰的可能性。
通过查验从受电源限制的传输焊盘314或接地焊盘312发源的传输线210,最佳地示出了更大的间隔。在最靠近电源的传输焊盘314或接地焊盘312之间限定的距离530明显大于跨越第一区域302的距离。大于第一区域302的宽度的距离530使得包括接口520该部分的线210之间的间隔比起其他配置或利用仅仅通过第一区域302延伸的直线的传统接口间隔得更开。
在一些示例中,靠近逻辑裸片208的侧面510的线210也可以延伸超出逻辑裸片208的侧面510,以有效地增加邻近逻辑裸片208的侧面510的区域302的宽度。例如,逻辑裸片208的侧面510被示出为通过虚线508被投影到裸片间区域206。线210的裸片间部分218(由虚线以附图标号518示出)被示出为被设置在虚线508的外部,并且因此在逻辑裸片208的侧面510的外部,以有效地增加逻辑裸片208的侧面510处的第一区域302 的宽度,并因此允许线210之间具有更大的间隔。
包括图5中所示的接口520的线210的裸片间部分218总的被示出为在垂直于逻辑裸片108的侧面202的直线路径中跨越裸片间区域206延伸。然而,包括接口520的线210 的裸片间部分218可替代地是非直线形的,以增加裸片间部分218的有效长度,从而增加电阻。在一些实施例中,包括接口520的线210的增加的间距提供了足够的串扰改善,从而在可接受振荡量的应用中可以省略增加裸片间部分218的电阻以大于EBR。在其他示例中,线210的总电阻值可以通过提供线210的裸片下部分214的额外长度来实现,该额外长度是有效地使线210的裸片间部分218横向间隔开所需的。
在一个示例中,线210的电阻值大于与线210相同的平均截面积和包括在垂直于侧面 202、204的一个方向上限定的长度以及延伸穿过裸片间区域206的裸片间部分的端到端(即,焊盘126到焊盘118)长度的铜线的EBR。可以通过利用电阻器(例如图4中所示的电阻器402)来实现大于EBR的电阻,或者通过选择线210的裸片间部分218的材料使其大于铜的电阻。上面已经参照图3讨论了用于线210的合适材料。
在另一个示例中,线210的一部分或全部可以由铜或适合用作信号传输线的其他导电材料制成,除了其中线210的裸片间部分218的长度大于跨越裸片间区域206的距离(从侧面202到侧面204)。通过利用穿过裸片间区域206的非线性路径,可以使得线210的裸片下部分214和/或裸片间部分218更长,如下面进一步讨论的。
图6-9是裸片间连接接口的信号传输线210的裸片间部分的不同示例的示意图。裸片间连接接口可以是这里描述的任何裸片间连接接口。参考图6-9描述的任何信号传输线210 可以包含电阻器,例如参照图4描述的电阻器402。替换地或另外地,参照图6-9描述的任何信号传输线210可以具有位于第二区域304内的部分,如参照图5所描述的。
现在转向图6,图6示出了延伸跨越在逻辑裸片108和存储器裸片106之间限定的裸片间区域206的传输线210的裸片间部分602。虚线600示出的直线路径被显示为在裸片106、108的侧面202、204之间垂直延伸。信号传输线210的裸片间部分602是非直线性的,因此比与虚线600共线的传输线长。因此,即使在芯片间部分602由铜制成的示例中,信号传输线210的裸片间部分602的电阻也大于EBR,这有效地减少了线210内不期望的振荡。
在图6中描绘的示例中,信号传输线210的裸片间部分602是弯曲的。例如,信号传输线210的裸片间部分602是弧形的,例如,位于虚线600的单侧。可以预期可以使用其他非直线性形状。还可以想到,线210的裸片下部分214的一些或全部也可以是弯曲的。
图7示出了延伸穿过逻辑裸片108和存储器裸片106之间限定的裸片间区域206的传输线210的另一个裸片间部分702。虚线600被显示为被显示为在裸片106、108的侧面202、204之间垂直延伸。信号传输线210的裸片间部分702也是非线性的,因此比与虚线600共线的传输线长。然而,与图6的信号传输线210的裸片间部分602不同,图7中描绘的信号传输线210的裸片间部分702具有在虚线600的两侧延伸的路径。
在一个示例中,信号传输线210的裸片间部分702具有平滑波形,例如正弦波形。正弦波形的波长小于裸片106、108之间限定的裸片间区域206的距离的两倍。在其他示例中,信号传输线210的裸片间部分702具有等于或小于裸片间区域206的距离的波长。也可以设想,线210的裸片下部分214的一些或全部也可以具有平滑的波形。
因此,即使在其中裸片间部分702由铜制造的示例中,信号传输线210的裸片间部分 702的电阻也大于EBR,这有效地减少了线210内的不期望的振荡。
图8-9示出了延伸穿过逻辑裸片108和存储器裸片106之间限定的裸片间区域206的传输线210的裸片间部分800、900。虚线600被显示为在裸片106、108的侧面202、204 之间垂直延伸。信号传输线210的裸片间部分800、900也是非直线性的,因此比与虚线 600共线的传输线长。然而,不同于图6的信号传输线210的裸片间部分602,而类似于图7的信号传输线210的裸片间部分702,图8-9上描述的信号传输线210的裸片间部分 800、900具有在虚线600的两侧延伸的路径。
在图8所示的示例中,信号传输线210的裸片间部分800具有阶梯波形,例如方波。在图9所示的示例中,信号传输线210的裸片间部分900具有Z字形或锯齿形波形。阶梯波形和锯齿波形的波长小于跨越裸片106、108之间限定的裸片间区域206的距离的两倍。在其他示例中,信号传输线210的裸片间部分800、900具有等于或小于跨越裸片间区域 206的距离的周期波长。还可以预期线210的裸片下部分214的一些或全部也可以具有阶梯或锯齿波形。
因此,即使在其中裸片间部分800、900由铜制造的示例中,信号传输线210的裸片间部分800、900的电阻值也大于EBR,这有效地减少了线210内部的不期望的振荡。
图10-11是在被设置在芯片封装100的裸片106、108之间的RDL 112的不同层中形成的裸片间连接接口1020的另一示例的顶部示意图。如图10中示出的,信号传输线210 被设置在RDL 112的第一层,例如图2中描绘的第一层230的,而传输线210被设置在 RDL 112的另一层中,例如图2中描绘的第三层250。
现在参考图10,信号传输线210被设置成相对于逻辑裸片108的侧面202的表面成非正交的角度1010。因此,路由通过裸片间区域206的线210的裸片间部分218比起路由垂直地穿过裸片间区域206的类似的线,具有更大的长度因此有更大的电阻值。因之,线210 的裸片间部分218具有的电阻值大于具有与线210相同的平均截面积和端到端长度(包括垂直于侧面202、204的方向上限定的长度以及延伸穿过裸片间区域206的裸片间部分的长度)的铜线的EBR。
线210的裸片间部分218可以具有穿过裸片间区域206的直线或非直线路径。图6-9中示出了非直线路径的一些示例。线210的裸片间部分218或其他部分可以可选地包括电阻器,例如图4中所示的电阻器402。导电信号传输线210可以由铜、银、金、镍、钼、铝、氧化铟锡、铜合金和其他导电金属合金等形成。
角度1010越远离90度,线210越长,因此电阻越大。然而,角度1010距离90度越远,线210越近,因此更容易受到串扰的影响。为了改善防止串扰的性能,接口1020的一些信号传输线210可以设置在不同的层上,如图11所示。在图11上,信号传输线210 被设置成相对于逻辑裸片108的侧面202的面成非正交角度1110。因此,通过将线210散布在RDL 112的不同层上,每层的线210的数量减少,这允许被形成在每层上的线210有更大间距。在每层中形成的线210的更大的间隔使得抗串扰性能增强。在一个示例中如图 11中所示的,用于第一通道的所有线210被形成在图10中所示的RDL 112的第一层中,而用于第二通道的所有线210被形成在RDL 112的不同层中。
图12是制造芯片封装(例如上述芯片封装100)的方法1200的流程图。方法1200在步骤1202开始:在载体上安装一个或多个逻辑裸片108和一个或多个存储器裸片106的堆叠。在步骤1204,将裸片106、108封装在模塑料142中以保持裸片106、108的位置取向和间隔。在步骤1206,移除载体以暴露裸片106、108的焊盘118、126。
在步骤1208,诸如RDL 112的再分布层被形成在裸片106、108下方并与裸片106,108 的暴露焊盘118、126接触。再分布层112包括高速信号传输接口,例如上述的接口120、420、520、1020,或具有其他合适配置的其他接口。信号传输接口的信号传输线210被配置为具有大于EBR的电阻。例如,再分布层112可以由线210形成,线210由电阻率大于铜的材料制成。在另一个示例中,再分布层112的线210可以包括电阻器402。在另一个示例中,再分布层112的线210可以横向地走线,这样,布线穿过裸片间区域206的线210 的裸片间部分218穿过裸片间区域206所限定的区域,裸片间区域206位于接地或电源焊盘之前。在又一个示例中,再分布层112的线210可以具有非直线路径,例如但不限于参考图6-9所示和所描述的那样。在又一个示例中,再分布层112的线210可以具有跨越裸片间区域206形成的路径,该路径取向为相对于逻辑裸片108的侧面202的面成非正交的角度。
在步骤1210,将RDL 112电气地和机械地安装到封装基片104,从而将封装电路134连接到裸片106、108的电路124、114。安装有裸片106、108的封装基片104形成芯片封装100。在一个示例中,芯片封装100被配置为HBM器件,其具有与在逻辑裸片108上的控制器共同封装的一个或多个存储器裸片106的堆叠。
在步骤1212,封装基片104被电气地和机械地安装到印刷电路板102,从而将PCB电路140连接到裸片106、108的电路124、114并形成芯片封装100。
因此,已经描述了具有改进的高速裸片间连接接口的芯片封装。高速裸片间连接接口被配置为抑制振荡,这有利地改善了噪声容限、安静切换(quiet switching)、信号传输质量和性能可靠性。在一些示例中,裸片间连接接口的信号传输线以有利地减少串扰的方式间隔开。
虽然前述内容针对本实用新型的实施例,但是可以在不脱离本实用新型的基本范围的情况下设计其他和进一步的实施例,并且本实用新型的范围由所附权利要求确定。
Claims (19)
1.一种芯片封装,其特征在于,所述芯片封装包括:
第一裸片;
第二裸片;
封装基片;
被安装在封装基片上的再分布层RDL,所述RDL具有连接所述第一裸片与所述第二裸片的信号传输接口,所述信号传输接口包括:
具有裸片间部分的信号传输线,所述信号传输线具有的电阻值大于铜线的等效基础电阻值EBR。
2.根据权利要求1所述的芯片封装,其特征在于,所述信号传输线的裸片间部分具有非线性路径,所述非线性路径被限定为跨过在第二裸片和第一裸片之间限定的裸片间区域。
3.根据权利要求1所述的芯片封装,其特征在于,所述信号传输线具有的电阻率大于铜的电阻率。
4.根据权利要求1所述的芯片封装,其特征在于,所述信号传输线包括:
电阻器。
5.根据权利要求1所述的芯片封装,其特征在于,所述芯片封装还包括:
在所述第二裸片和第一裸片的相对侧之间限定的裸片间区域,所述裸片间区域包括:
在第二裸片和第一裸片之间延伸的、邻近被形成在第二裸片一侧处的信号传输焊盘的第一区域;和
在第二裸片和第一裸片之间延伸的、邻近被形成在第二裸片一侧处的接地或电源焊盘的第二区域,所述信号传输线至少部分地被布置在第二区域内。
6.根据权利要求5所述的芯片封装,其特征在于,所述信号传输线的裸片间部分具有非线性路径,所述非线性路径被限定为跨过在第二裸片和第一裸片之间限定的裸片间区域。
7.根据权利要求5所述的芯片封装,其特征在于,所述信号传输线具有的电阻率大于铜的电阻率。
8.根据权利要求5所述的芯片封装,其特征在于,所述信号传输线包括:
电阻器。
9.根据权利要求1所述的芯片封装,其特征在于,所述信号传输线的裸片间部分被布置为相对于所述第二裸片面向所述第一裸片的一侧成非正交的角度。
10.根据权利要求9所述的芯片封装,其特征在于,所述信号传输线的裸片间部分具有非线性路径,所述非线性路径被限定为跨过在第二裸片和第一裸片之间限定的裸片间区域。
11.根据权利要求9所述的芯片封装,其特征在于,所述信号传输线具有的电阻率大于铜的电阻率。
12.根据权利要求9所述的芯片封装,其特征在于,所述信号传输线包括:
电阻器。
13.根据权利要求9所述的芯片封装,其特征在于,所述信号传输线是被形成在包括信号传输接口的至少两个金属层上的第一组信号传输线的一部分。
14.根据权利要求9所述的芯片封装,其特征在于,所述信号传输线是限定第一通道的第一组信号传输线的一部分,所述第一组信号传输线被形成在第一金属层上;以及
其中限定第二通道的第二组信号传输线被形成在第一金属层下面的第二金属层上的所述信号传输接口中。
15.一种芯片封装,其特征在于,所述芯片封装包括:
逻辑裸片;
存储器裸片的堆叠;
封装基片;
在所述逻辑裸片和所述存储器裸片的堆叠之间限定的裸片间区域,所述裸片间区域包括:
在逻辑裸片和存储器裸片之间延伸、并邻近形成在逻辑裸片一侧的信号传输焊盘的第一区域;和
在逻辑裸片和存储器裸片之间延伸、并邻近形成在逻辑裸片一侧的接地或电源焊盘的第二区域;以及
安装在封装基片上的再分布层RDL,所述RDL具有信号传输接口,所述信号传输接口将逻辑裸片与跨过所述裸片间区域的存储器裸片的堆叠连接,所述信号传输接口包括:
具有裸片间部分的第一信号传输线,所述第一信号传输线的电阻值大于铜线的等效基础电阻值EBR,所述第一信号传输线至少部分被设置在第二区域内。
16.根据权利要求15所述的芯片封装,其特征在于,所述第一信号传输线的裸片间部分具有非线性路径,所述非线性路径被限定为跨过所述裸片间区域。
17.根据权利要求15所述的芯片封装,其特征在于,所述第一信号传输线具有的电阻率大于铜的电阻率。
18.根据权利要求15所述的芯片封装,其特征在于,所述第一信号传输线包括:
电阻器。
19.根据权利要求15所述的芯片封装,其特征在于,所述信号传输接口还包括:
具有裸片间部分的第二信号传输线,所述第一信号传输线的裸片间部分和所述第二信号传输线的裸片间部分被布置在所述信号传输接口的不同的层上。
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