CN209747544U - Light emitting diode chip - Google Patents

Abstract

The application provides a light emitting diode chip, the first surface of substrate is kept away from the edge position patterning and is provided with protruding structure, that is to say, the surface of substrate of isolation trench position department does not set up protruding structure. Because the reflecting layer is arranged at the position of the isolation groove and has strong reflecting capacity, the emitted light can be reflected and emitted from the light-emitting surface of the substrate. However, the conventional LED chip has a patterned structure at the position of the isolation trench, which reduces the reflection capability of the reflective layer and reduces the light extraction capability. The surface of the substrate at the position of the isolation groove is not provided with the protruding structure, so that the problem that the reflection capability of the traditional LED chip on the reflection layer at the position of the isolation groove is poor can be solved, and the light extraction rate of the LED chip is improved. Meanwhile, the side wall of the isolation groove is provided with a plurality of inclined planes, the area of the side wall is enlarged through the inclined planes, the included angle of the internal light incident on the side wall is increased, light can be increased, and the brightness of the light-emitting diode chip is improved.

Description

Light emitting diode chip

Technical Field

The present application relates to the field of semiconductor technology, and more particularly, to a light emitting diode chip.

Background

Light Emitting Diodes (LEDs) convert electrical energy into Light energy, which emits visible Light of various colors such as yellow, green, blue, and infrared and ultraviolet invisible Light. Compared with incandescent lamps and neon lamps, the LED has the advantages of low working voltage and current, high reliability, long service life, convenience in adjusting the luminous brightness and the like.

with the increasing approach of LED lamp market explosion, the research and development competition of LED packaging technology is also very intense. At present, the GaN-based LED chip mainly has a forward mounting structure and a flip-chip structure. Light emitted by the forward mounting structure is emitted out through the P-GaN region and the transparent electrode, the structure is simple, but the P, N electrode is positioned on the same side, current flows through the N-GaN layer transversely, so that current crowding is caused, the local heating amount is high, and the driving current is limited; second, sapphire has poor thermal conductivity, severely impeding heat dissipation. The flip-chip LED chip can solve the heat dissipation problem of the forward-mounted LED chip due to current crowding. However, the conventional flip LED chip has low light extraction efficiency, thereby causing low light emitting efficiency of the LED.

SUMMERY OF THE UTILITY MODEL

In view of this, it is necessary to provide a light emitting diode chip with high light extraction efficiency, aiming at the problem of low light extraction efficiency of the conventional flip LED chip.

The application provides a light emitting diode chip which comprises a substrate, an N-type semiconductor layer, a protruding structure and an isolation groove. The substrate is provided with a first surface and a second surface which are opposite, and the first surface is provided with a plurality of protruding structures in a patterning mode far away from the edge position to form a patterned substrate. The N-type semiconductor layer is arranged on the first surface and is surrounded with the edge of the first surface to form an isolation groove, the protruding structures are not arranged in the isolation groove, and the side wall of the isolation groove is provided with a plurality of inclined planes. And an N-type semiconductor table board is arranged on the edge surface of the N-type semiconductor layer close to the isolation groove, and an N-type electrode is arranged on the N-type semiconductor table board. The surface of the N-type semiconductor layer, which is far away from the substrate, is sequentially provided with a light emitting layer, a P-type semiconductor layer and a current expansion layer, and the N-type electrode and the light emitting layer are arranged on the surface of the N-type semiconductor layer at intervals. And a P-type electrode is arranged on the surface of the current expansion layer, which is far away from the P-type semiconductor layer. The reflecting layer is arranged on the isolation groove, the current expanding layer is far away from the surface of the P-type semiconductor layer and the surface of the N-type semiconductor mesa, and the P-type electrode and the N-type electrode are exposed.

In one embodiment, the raised structure is a conical structure.

In one embodiment, the angle between adjacent slopes is a positive angle.

In one embodiment, the led chip further comprises a P-type pad and an N-type pad. The P-type welding disc is arranged on the surface of the P-type electrode and covers the P-type electrode to realize electric connection. The N-type welding disc is arranged on the surface of the N-type electrode and covers the N-type electrode to realize electric connection.

In one embodiment, the raised structures are silicon dioxide, titanium dioxide, or tri-titanium pentoxide.

In one embodiment, the sidewall has three slopes.

In one embodiment, the surface of the sidewall is a curved surface.

In one embodiment, the width of the isolation trench is 3 μm to 12 μm.

In one embodiment, the height of the raised structures is 1 μm to 2 μm.

in one embodiment, the raised structure material is silicon dioxide or titanium dioxide.

the application provides a light emitting diode chip as described above, the first surface is provided with the protruding structure in a patterned manner far from the edge position, that is, the surface of the substrate at the position of the isolation groove is not provided with the protruding structure. Because the reflecting layer is arranged at the position of the isolation groove and has strong reflecting capacity, the emitted light can be reflected and emitted from the light-emitting surface of the substrate. However, the conventional LED chip has a patterned structure at the position of the isolation groove, which reduces the reflection capability of the reflective layer and reduces the light extraction capability. Therefore, the problem that the reflection capability of the traditional LED chip on the reflecting layer of the isolation groove is poor can be solved by not arranging the protruding structure on the surface of the substrate at the isolation groove, and the light extraction rate of the LED chip is improved.

Meanwhile, the side wall of the isolation groove is provided with a plurality of inclined surfaces, the area of the side wall is enlarged through the inclined surfaces, the included angle of the internal light incident on the side wall is increased, light extraction is increased, light emitting of the side wall surface of the isolation groove is increased, and the brightness of the light emitting diode chip is improved.

Drawings

Fig. 1 is a schematic view of an overall structure of a light emitting diode chip provided in the present application;

Fig. 2 is a schematic diagram of a slope of a sidewall of an led chip provided in the present application.

Description of the reference numerals

The light emitting diode chip comprises a light emitting diode chip 100, a substrate 10, a first surface 110, a second surface 120, a protruding structure 130, an N-type semiconductor layer 20, an isolation groove 50, a sidewall 510, a slope 511, an N-type semiconductor mesa 40, an N-type electrode 720, a P-type semiconductor layer 30, a current spreading layer 60, a P-type electrode 710, a reflective layer 80, a P-type pad 910 and an N-type pad 920.

Detailed Description

in order to make the objects, technical solutions and advantages of the present application more apparent, the present application is further described in detail below by way of embodiments and with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings). In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present application and for simplicity in description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be considered as limiting the present application.

In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

Referring to fig. 1-2, the present application provides a light emitting diode chip 100 including a substrate 10, an N-type semiconductor layer 20, an isolation trench 50, an N-type semiconductor mesa 40, a light emitting layer, a P-type semiconductor layer 30, a current spreading layer 60, a P-type electrode 710, and a reflective layer 80. The substrate 10 has a first surface 110 and a second surface 120 opposite to each other, and the first surface 110 is patterned with a plurality of protruding structures 130 away from the edge position to form a patterned substrate. The N-type semiconductor layer 20 is disposed on the plurality of protruding structures 130 of the first surface 110, an isolation groove 50 is formed by surrounding the edge of the N-type semiconductor layer 20 and the edge of the first surface 110, the protruding structures 130 are not disposed in the isolation groove 50, and a sidewall 510 of the isolation groove 50 has a plurality of inclined surfaces 511. The edge surface of the N-type semiconductor layer 20 close to the isolation groove 50 is provided with an N-type semiconductor mesa 40, and the N-type semiconductor mesa 40 is provided with an N-type electrode 720. The surface of the N-type semiconductor layer 20 away from the substrate 10 is sequentially provided with a light emitting layer, a P-type semiconductor layer 30 and a current spreading layer 60, and the N-type electrode 720 and the light emitting layer are arranged on the surface of the N-type semiconductor layer 20 at an interval. The surface of the current spreading layer 60 away from the P-type semiconductor layer 30 is provided with a P-type electrode 710. The reflective layer 80 is disposed in the isolation trench 50, the current spreading layer 60 is away from the surface of the P-type semiconductor layer 30 and the N-type semiconductor mesa 40, and exposes the P-type electrode 710 and the N-type electrode 720.

the first surface 110 is patterned with raised structures 130 away from the edge positions, that is, the surface of the substrate 10 at the positions of the isolation grooves 50 is not provided with the raised structures 130. Since the reflective layer 80 is disposed at the position of the isolation groove 50, and the reflective layer 80 has a strong reflective capability, the emitted light can be reflected and emitted from the light-emitting surface of the substrate 10. However, the conventional LED chip is provided with a patterned structure at the position of the isolation groove 50, which results in a decrease in the reflection capability of the reflective layer 80 and a decrease in the light extraction capability. Therefore, the surface of the substrate 10 at the position of the isolation groove 50 is not provided with the protruding structure 130, so that the problem of poor reflection capability of the conventional LED chip at the position of the isolation groove on the reflective layer can be solved, and the light extraction rate of the LED chip 100 is improved.

Moreover, the patterned plurality of protrusion structures 130 are disposed between the substrate 10 and the N-type semiconductor layer 20, so that the dislocation density of the epitaxial material of the N-type semiconductor layer 20 can be effectively reduced, the non-radiative recombination of the light emitting layer is reduced, the reverse leakage current is reduced, and the service life of the light emitting diode chip 100 is prolonged. Meanwhile, the plurality of bump structures 130 disposed on the first surface 110 can also enable light emitted from the light emitting layer to be scattered multiple times through the interface between the N-type semiconductor layer 20 and the substrate 10, so as to change the exit angle of total reflection light, increase the probability that light of the light emitting diode chip 100 (flip-chip LED) exits from the substrate 10, and thus improve the light extraction efficiency. Therefore, by disposing the plurality of protruding structures 130 between the substrate 10 and the N-type semiconductor layer 20 and not disposing the protruding structures 130 in the isolation grooves 50, the luminance of the light emitted from the LED chip 100 can be greatly improved compared to a conventional LED chip, the reverse leakage current is reduced, and the lifetime of the LED chip 100 is also prolonged.

Meanwhile, the sidewall 510 of the isolation trench 50 is provided with a plurality of inclined planes 511, at this time, the area of the sidewall 510 is increased by the plurality of inclined planes 511, and the included angle of the internal light incident on the sidewall 510 is increased, so that the light extraction is increased, the sidewall surface of the isolation trench 50 emits more light, and the brightness of the light emitting diode chip is improved.

in one embodiment, the raised structure 130 is a conical structure.

The convex structure 130 is a cone structure, so that light emitted by the light emitting layer is scattered multiple times through the interface between the N-type semiconductor layer 20 and the substrate 10, the exit angle of total reflection light is better changed, the probability that light of the light emitting diode chip 100 exits from the substrate 10 is improved, and the light extraction efficiency is improved.

In one embodiment, the raised structure 130 material is titanium oxide such as silicon dioxide or titanium dioxide.

The substrate 10 is a sapphire substrate, and the protrusion structure 130 is a titanium oxide such as silicon dioxide or titanium dioxide. The titanium oxide such as silicon dioxide or titanium dioxide has better etching method and selection ratio, selective area reservation and patterned structure removal can be carried out during preparation, and light extraction can be better carried out or light path change and light extraction can be increased compared with the patterned structure of the sapphire substrate. In order to achieve maximum light extraction. Therefore, a plurality of patterned protruding structures 130 are arranged between the substrate 10 and the N-type semiconductor layer 20, and the protruding structures 130 are not arranged on the surface of the substrate 10 at the position of the isolation groove 50, so that the reflection capability of the reflection layer 80 is improved, the light extraction capability is improved, the problem that the reflection capability of the reflection layer at the position of the isolation groove of the traditional flip-chip LED chip is poor is solved, and the light extraction efficiency is improved.

In one embodiment, the angle between adjacent slopes 511 is a positive angle.

The inclined planes 511 may be the same or different, and the positive angle formed between adjacent inclined planes 511 may also be different, thereby increasing the light emitting area. The plurality of slopes 511 form the sidewalls 510 with different shapes, so that internal light can enter the sidewalls 510 to generate different incident angles, more light can be extracted, and more total reflection can be avoided. When the reflective layer 80 can be coated on the isolation trench 50, better insulation is performed. If the angle is negative, the insulation cannot be covered and insulated, and leakage occurs. The shape of the light-emitting surface of the sidewall 510 of the isolation groove 50 is changed, so that the light-emitting area of the sidewall 510 is increased. The plurality of inclined planes 511 can change the incident angle of light rays in the chip to the side wall 510, and can also change the light-emitting angle of the side surface of the chip, so that the light-emitting number is increased, and the brightness of the light-emitting diode chip 100 is improved.

in one embodiment, the led chip further includes a P-type bonding pad 910 and an N-type bonding pad 920. The P-type pad 910 is disposed on the surface of the P-type electrode 710, and covers the P-type electrode 710 for electrical connection. The N-type bonding pad 920 is disposed on the surface of the N-type electrode 720, and covers the N-type electrode 720 to achieve electrical connection.

In one embodiment, the sidewall 510 of the isolation trench 50 may have two slopes 511 or three slopes 511 or a plurality of slopes 511 or arcs, etc. The plurality of slopes 511 form the sidewalls 510 with different shapes, so that internal light can enter the sidewalls 510 to generate different incident angles, more light can be extracted, and more total reflection can be avoided.

In one embodiment, the width of the isolation trench 50 is 3 μm to 12 μm.

if the width of the isolation trench 50 is too narrow, the glue may remain, and if the width of the isolation trench 50 is too wide, the isolation trench occupies more light-emitting area, which affects brightness, so the width of the isolation trench 50 is selected to be in a range of 3 μm to 12 μm.

In one embodiment, the height of the protrusion structures 130 is 1 μm to 2 μm.

By setting the height of the protruding structure 130 to be 1 μm-2 μm, the dislocation density of the epitaxial material of the N-type semiconductor layer 20 can be effectively reduced, so that the non-radiative recombination of the light emitting layer is reduced, the reverse leakage current is reduced, and the service life of the light emitting diode chip 100 is prolonged. Meanwhile, the light can be scattered for many times through the arrangement of the height, the emergence angle of the total reflection light is changed, the probability that the light of the light emitting diode chip 100 (flip-chip LED) is emergent from the substrate 10 is increased, and the light extraction efficiency is improved.

in one embodiment, the reflective layer 80 is a distributed bragg reflector.

In one embodiment, the light emitting diode chip 100 is a flip-chip LED chip. A method for manufacturing the light emitting diode chip 100 includes the following steps:

S10, providing the substrate 10;

S20, sequentially preparing a plurality of patterned protruding structures 130 on the first surface of the substrate 10, and sequentially preparing the N-type semiconductor layer 20, the light emitting layer, and the P-type semiconductor layer 30 on the basis of the plurality of protruding structures 130 to form an LED wafer; wherein, the plurality of protruding structures 130 are titanium pentoxide, silicon dioxide, DBR, or the like.

S30, performing Inductively Coupled Plasma (ICP) etching on the LED wafer by using the MESA layer as a mask to form the N-type semiconductor MESA 40; wherein, the mesa layer: on an LED wafer, the isolation pattern between devices, also referred to as a mesa.

s40, performing ICP etching with the first isolation trench pattern layer as a mask until the plurality of protruding structures 130 are exposed out of the plurality of protruding structures 130 on the first surface 110 of the substrate 10 to form the isolation trench 50, where the surface of the sidewall 510 of the isolation trench may be a single inclined surface, or may be two or more inclined surfaces 511 or arc surfaces; the narrow width of the isolation trench 50 may cause glue residue, and the wide width of the isolation trench 50 may cause occupation of a large amount of light emitting area and influence on brightness, so the width of the isolation trench 50 is selected to be in a range of 3 μm to 12 μm.

S50, spin-coating a photoresist by using a single-layer photoresist coating or a double-layer photoresist coating, exposing and developing to form a second isolation trench pattern layer, and performing Wet Etching (Wet Etching) with the second isolation trench pattern layer as a mask to etch away the plurality of Patterned protrusion structures 130 (PSS) in the isolation trenches; the photoresist spin coating thickness is 7 um-12 um, so that the poor step coverage capability of the photoresist caused by over-thin photoresist is avoided, the poor uniformity caused by over-thick photoresist is avoided, and the width dimension of the isolation groove has large difference.

S60, preparing the current spreading layer 60 (current blocking layer and transparent conductive layer) on the LED wafer;

S70, forming the P-type electrode 710 on the surface of the current spreading layer 60 away from the substrate 10, and forming the N-type electrode 720 on the N-type semiconductor mesa 40;

S80, preparing a Distributed Bragg Reflector (DBR) and leaking out the P-type electrode 710 and the N-type electrode 720;

S90, preparing the P-type pad 910 on the surface of the P-type electrode 710, and preparing the N-type pad 920 on the surface of the N-type electrode 720 to achieve electrical connection.

In the step S50, since the protruding structure 130 is titanium oxide, silicon dioxide, or DBR, etc., the protruding structure 130 in the isolation trench 50 can be selectively removed by wet etching, so that the reflective layer in the isolation trench is a plane, and the brightness is better when mirror reflection is formed, thereby achieving the purpose of maximum light extraction, improving the light extraction efficiency of the LED to improve the external quantum efficiency thereof, and further improving the light emitting efficiency of the LED.

the technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

the above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A light emitting diode chip, comprising:

The substrate (10) is provided with a first surface (110) and a second surface (120) which are opposite, the first surface (110) is provided with a plurality of protruding structures (130) in a patterning mode far away from the edge position, and a patterned substrate is formed;

The N-type semiconductor layer (20) is arranged on the plurality of convex structures (130) on the first surface (110), the edge of the N-type semiconductor layer (20) and the edge of the first surface (110) surround to form an isolation groove (50), the convex structures (130) are not arranged in the isolation groove (50), and the side wall (510) of the isolation groove (50) is provided with a plurality of inclined surfaces (511);

An N-type semiconductor table top (40) is arranged on the edge surface, close to the isolation groove (50), of the N-type semiconductor layer (20), and an N-type electrode (720) is arranged on the N-type semiconductor table top (40);

A light emitting layer, a P-type semiconductor layer (30) and a current spreading layer (60) are sequentially arranged on the surface, far away from the substrate (10), of the N-type semiconductor layer (20), and the N-type electrode (720) and the light emitting layer are arranged on the surface of the N-type semiconductor layer (20) at intervals;

the surface of the current spreading layer (60) far away from the P-type semiconductor layer (30) is provided with a P-type electrode (710);

And the reflecting layer (80) is arranged in the isolation groove (50), the current spreading layer (60) is far away from the surface of the P-type semiconductor layer (30) and the N-type semiconductor mesa (40), and the P-type electrode (710) and the N-type electrode (720) are exposed.

2. The light-emitting diode chip as claimed in claim 1, characterized in that the raised structure (130) is a conical structure.

3. The light-emitting diode chip as claimed in claim 1, characterized in that the material of the raised structure (130) is silicon dioxide, titanium dioxide or titanium pentoxide.

4. The light-emitting diode chip as claimed in claim 1, characterized in that the angle between adjacent slopes (511) is a positive angle.

5. The light emitting diode chip of claim 1, wherein the light emitting diode chip further comprises:

The P-type bonding pad (910) is arranged on the surface of the P-type electrode (710) and covers the P-type electrode (710) to realize electric connection;

And the N-type bonding pad (920) is arranged on the surface of the N-type electrode (720) and covers the N-type electrode (720) to realize electric connection.

6. The light-emitting diode chip as claimed in claim 1, characterized in that the side wall (510) has three bevels (511).

7. The light-emitting diode chip as claimed in claim 1, characterized in that the surface of the side wall (510) is a curved surface.

8. The light-emitting diode chip as claimed in claim 1, characterized in that the width of the isolation trenches (50) is between 3 μm and 12 μm.

9. The light-emitting diode chip as claimed in claim 1, characterized in that the height of the relief structure (130) is between 1 μm and 2 μm.

10. The light-emitting diode chip as claimed in claim 1, characterized in that the reflective layer (80) is a distributed bragg reflector.