CN209546012U - A kind of optimization structure for multi-load DDRX interconnection daisy topology - Google Patents

Abstract

The utility model discloses one of High Speed PCB Design Technology fields for the optimization structure of multi-load DDRX interconnection daisy topology, several loads are equipped on the output major trunk roads at driving end, it is connected between two neighboring load by intermediate traces, the characteristic impedance for exporting major trunk roads is less than the characteristic impedance of intermediate traces.The utility model by adjusting daisy topology trunk and component cabling characteristic impedance, so that the characteristic impedance of signal path is reached unanimity, improve impedance continuity, to effectively mitigate the reflection of signal, the influence for reducing capacitive load effect, improves signal integrity.

Description

A kind of optimization structure for multi-load DDRX interconnection daisy topology

Technical field

The utility model relates to High Speed PCB Design Technology fields, in particular to a kind of mutual for multi-load DDRX The even optimization structure of daisy topology.

Background technique

Printed circuit board (Printed Circuit Board, pcb board) is also known as printed circuit board, is the object of electronic product The important component of reason support and signal transmission.With DDR (Double Data Rate Synchronous Dynamic Random Access Memory) technology update upgrading, signal rate constantly promotes, and the non-ideal effects of interconnecting link are more next It is more significant, in the case where being mainly manifested in multi-load.

Since branch and supported chip are more, the influence of capacitive load is inevitable: firstly, common via hole is in capacitive 's；Secondly there are parasitic capacitance (about 0.33~0.44pF) on chip package；Furthermore Die (chip dies, unencapsulated preceding shape Formula) on there are parasitic capacitance (about 0.77~2.12pF).All these capacity effects can all reduce having for signal transmission path Imitate characteristic impedance.

Conventional method by each section of same signal walk line traffic control be identical characteristic impedance value (such as 50 ohm of single ended line, it is poor 100 ohm of separated time), due to the influence of capacitive load, the validity feature impedance of signal path can change, and lead to signal path Impedance it is discontinuous, in turn result in the reflection of signal, (" X " indicates the DDR skill in different generations to constrain high speed multi-load DDRX Art) interconnection design realization.

Drawbacks described above is worth improving.

Summary of the invention

In order to overcome the shortcomings of existing technology, the utility model provides one kind and opens up for multi-load DDRX interconnection daisy chain The optimization structure flutterred.

Technical solutions of the utility model are as described below:

A kind of optimization structure for multi-load DDRX interconnection daisy topology, is equipped on the output major trunk roads at driving end Several are loaded, and are passed through intermediate traces between the two neighboring load and are connected, which is characterized in that the spy of the output major trunk roads Levy the characteristic impedance that impedance is less than the intermediate traces.

According to the utility model of above scheme, which is characterized in that the characteristic impedance of the output major trunk roads is in described Between 0.7-0.9 times of characteristic impedance of cabling.

According to the utility model of above scheme, which is characterized in that when the load is 4 DDR particles, the output master The characteristic impedance of the characteristic impedance of the arterial highway intermediate traces is 5 ohm small.

According to the utility model of above scheme, which is characterized in that when the load is 8 DDR particles, the output master The characteristic impedance of the characteristic impedance of the arterial highway intermediate traces is 10 ohm small.

According to the utility model of above scheme, which is characterized in that the output major trunk roads line width is greater than the centre and walks The line width of line.

According to the utility model of above scheme, which is characterized in that the characteristic impedance of branch's cabling where the load Greater than the characteristic impedance of the intermediate traces.

Further, the characteristic impedance of branch's cabling is 1.1-1.2 times of the characteristic impedance of the intermediate traces.

Further, the output major trunk roads line width is greater than the line width of the intermediate traces, the line width of branch's cabling Less than the line width of the intermediate traces.

According to the utility model of above scheme, the beneficial effect is that, the utility model is by adjusting daisy topology The characteristic impedance of trunk and component cabling makes the characteristic impedance of signal path reach unanimity, improves impedance continuity, from And effectively mitigate the reflection of signal, the influence of capacitive load effect is reduced, signal integrity is improved.

Detailed description of the invention

Fig. 1 is the structural schematic diagram of the utility model.

Fig. 2 is the schematic diagram of the utility model micro-strip line impedance.

Fig. 3 is the schematic diagram of the band-like line impedence of the utility model.

1, Memory Controller Hub in the figure；2, dynamic RAM.

Specific embodiment

With reference to the accompanying drawing and the utility model is further described in embodiment:

As shown in Figure 1, a kind of optimization structure for multi-load DDRX interconnection daisy topology, the output master at driving end Arterial highway is loaded equipped with several, is passed through intermediate traces between two neighboring load and is connected.Driving end is Memory Controller Hub 1, is born Carrying is dynamic RAM 2.

The utility model is adjusted the cabling characteristic impedance of conventional daisy topology difference section by changing line width, makes The impedance of signal path reaches unanimity, and improves the impedance continuity of signal path, to achieve the purpose that reduce signal reflex. Wherein, the characteristic impedance for exporting major trunk roads is Z₁, the characteristic impedance of intermediate traces is Z₀, the characteristic impedance of branch's cabling is Z₂。

Embodiment one:

In the present embodiment, the characteristic impedance Z of adjustment output major trunk roads₁Less than the characteristic impedance Z of intermediate traces₀, i.e., in lamination In the case where determination, reduce the characteristic impedance Z of output major trunk roads₁.Specifically, the characteristic impedance Z of output major trunk roads₁It is walked for centre The characteristic impedance Z of line₀0.7-0.9 times of (i.e. Z₁=(0.7-0.9) Z₀)。

In the present embodiment, the characteristic impedance Z of branch's cabling₂With the characteristic impedance Z of intermediate traces₀It is equal in magnitude.

Preferably, the purpose of reduction major trunk roads impedance is realized by increasing the line width of major trunk roads.

When load is 4 DDR particles, the characteristic impedance Z of major trunk roads is exported₁Compared with the characteristic impedance Z of intermediate traces₀Small 5 Europe Nurse；When load is 8 DDR particles, the characteristic impedance Z of major trunk roads is exported₁Compared with the characteristic impedance Z of intermediate traces₀It is 10 ohm small.

In an application example, veneer in the prior art single-ended line impedence on normal control pcb board is 50 ohm In the case where, the characteristic impedance of the major trunk roads of echo signal daisy topology, intermediate traces and branch's cabling, which is consistent, (not to be done Capacitive load compensation), there are biggish deviations in simulation waveform；And the characteristic impedance Z that major trunk roads will be exported₁Control is 42 Europe Nurse, the characteristic impedance of other sections of cablings remain unchanged and (have capacitive load compensation), and the deviation of simulation waveform is relatively small.It does and holds Property compensation eye figure have bigger eye high, increase 180mV or so than not doing capacitive compensation, be equivalent to the system for improving 12% Allowance preferably improves the integrality of signal.

Embodiment two

As more excellent scheme, the characteristic impedance Z of adjustment output major trunk roads₁Less than the characteristic impedance Z of intermediate traces₀, meanwhile, The characteristic impedance Z of branch's cabling where loading₂Greater than the characteristic impedance Z of intermediate traces₀, i.e., in the case where lamination determines, increase Add the characteristic impedance Z of output major trunk roads₁, reduce the characteristic impedance Z of branch's cabling₂.Specifically, the characteristic impedance of output major trunk roads Z₁For the characteristic impedance Z of intermediate traces₀0.7-0.9 times of (i.e. Z₁=(0.7-0.9) Z₀), the characteristic impedance Z of branch's cabling₂For in Between cabling characteristic impedance Z₀1.1-1.2 times of (i.e. Z₂=(1.1-1.2) Z₀)。

Preferably, the present embodiment controls the characteristic impedance value of corresponding line by controlling the line width of corresponding cabling, specifically Output major trunk roads line width be greater than the line widths of intermediate traces, the line width of branch's cabling is less than the line width of intermediate traces.

As Figure 2-3, during by controlling characteristic impedance value of the line width of corresponding cabling to control corresponding line, Under the premise of lamination determines (veneer lamination determines that Er, T, H are determined therewith), according to micro-strip line impedance and strip line impedometer Formula is calculated, can realize impedance adjustment by increaseing or decreasing corresponding trace width (W in formula).It includes surface layer line The band-like line impedence of micro-strip line impedance and internal layer cabling.

(1) calculation formula of micro-strip line impedance Z are as follows:

0.1 < W/H < 0.2,1 < Er < 15

Wherein, Z indicates characteristic impedance；E_rIndicate dielectric constant；W indicates trace width；T indicates that cabling copper is thick；H indicates The spacing of line and neighboring reference plane.

(2) calculation formula of strip line impedance Z are as follows:

W/H < 0.35, T/H < 0.25

Wherein, Z indicates characteristic impedance；E_rIndicate dielectric constant；W indicates trace width；T indicates that cabling copper is thick；H indicates phase Spacing between adjacent reference planes.

Above two calculation formula is the state of the art, and it is the protection scope of the utility model that it, which is not, Derivation process is no longer described in detail.

It should be understood that for those of ordinary skills, it can be modified or changed according to the above description, And all these modifications and variations all should belong to the protection scope of the appended claims for the utility model.

Illustrative description is carried out to the utility model patent above in conjunction with attached drawing, it is clear that the reality of the utility model patent It is now not subject to the restrictions described above, as long as being carried out using the method concept and technical solution of the utility model patent various Improve, or it is not improved the conception and technical scheme of the utility model patent are directly applied into other occasions, in this reality With in novel protection scope.

Claims (8)

1. a kind of optimization structure for multi-load DDRX interconnection daisy topology, if being equipped on the output major trunk roads at driving end Dry loads, and passes through intermediate traces between the two neighboring load and connects, which is characterized in that the feature of the output major trunk roads Impedance is less than the characteristic impedance of the intermediate traces.

2. the optimization structure according to claim 1 for multi-load DDRX interconnection daisy topology, which is characterized in that institute 0.7-0.9 times for stating characteristic impedance of the characteristic impedance of output major trunk roads for the intermediate traces.

3. the optimization structure according to claim 1 for multi-load DDRX interconnection daisy topology, which is characterized in that institute State load be 4 DDR particles when, it is described output major trunk roads the characteristic impedance intermediate traces characteristic impedance it is 5 ohm small.

4. the optimization structure according to claim 1 for multi-load DDRX interconnection daisy topology, which is characterized in that institute State load be 8 DDR particles when, it is described output major trunk roads the characteristic impedance intermediate traces small 10 Europe of characteristic impedance Nurse.

5. the optimization structure according to claim 1 for multi-load DDRX interconnection daisy topology, which is characterized in that institute State the line width that output major trunk roads line width is greater than the intermediate traces.

6. the optimization structure according to claim 1 for multi-load DDRX interconnection daisy topology, which is characterized in that institute The characteristic impedance for stating branch's cabling where load is greater than the characteristic impedance of the intermediate traces.

7. the optimization structure according to claim 6 for multi-load DDRX interconnection daisy topology, which is characterized in that institute 1.1-1.2 times for stating characteristic impedance of the characteristic impedance of branch's cabling for the intermediate traces.

8. the optimization structure according to claim 6 for multi-load DDRX interconnection daisy topology, which is characterized in that institute The line width that output major trunk roads line width is greater than the intermediate traces is stated, the line width of branch's cabling is less than the line of the intermediate traces It is wide.