CN206272947U - A kind of printed circuit board (PCB) - Google Patents
A kind of printed circuit board (PCB) Download PDFInfo
- Publication number
- CN206272947U CN206272947U CN201621267014.0U CN201621267014U CN206272947U CN 206272947 U CN206272947 U CN 206272947U CN 201621267014 U CN201621267014 U CN 201621267014U CN 206272947 U CN206272947 U CN 206272947U
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- CN
- China
- Prior art keywords
- holding wire
- pcb
- circuit board
- printed circuit
- area
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn - After Issue
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Abstract
The utility model discloses a kind of printed circuit board (PCB), disclosed printed circuit board (PCB) includes the fixed plate body of laminated thickness, chip, holding wire and some ground hole are provided with the plate body, when the point on the holding wire on plate body and ground pitch-row are from less than predeterminable range, it is defined as the location point for needing to empty, its corresponding reference layer sets etched-off area in the holding wire location point for needing to empty.In design early stage, it is determined that after chip model and lamination setting are set on printed circuit board (PCB), by the vertical intersection in signal with ground hole, sub-fraction is emptied on the reference stratum of holding wire, so that the liftoff hole of thermal compensation signal line-spacing is relatively closely and to the influence of rising edge.Can eliminate that holding wire is relatively near with ground hole and the influence that brings, ensure that the sequential of DDR, such that it is able to formulate the relative loose coiling specification of a bit, and the workload of wiring installation teacher need not be increased, reduce design difficulty and time cost.
Description
Technical field
The utility model is related to computer hardware technology field, more particularly to a kind of printed circuit board (PCB).
Background technology
The DDR of Feiteng processor beneath chips（Internal memory）Sequential be directly connected to DDR can normal work, to computer
Performance impact it is very big.At present, when DDR coilings are carried out, due to the limitation of Feiteng processor beneath chips wiring space, can not
The presence Fanout for avoiding（It is fanned out to）Coiling.In order to ensure the sequential of DDR, it is ensured that the normal work of DDR is, it is necessary in DDR coilings
When to carrying out strict limitation on length of arrangement wire, such as 10mil is no more than with group signal isometric error, to ensure DDR with organizing letter
Number wait when.Wiring installation teacher is in order to ensure sequential, it is necessary to observe wiring specification, it is necessary to devote a tremendous amount of time around isometric
It is that requirement engineering teacher has rich experience and careful enough, patience around isometric work, therefore increase workload, increase in work
Plus time cost is inevitable.
Even if but ensure that same group signal lead is isometric, the sequential of DDR can not be can guarantee that.Because have ignored holding wire
The influence that distance ground hole is closely brought excessively.In the DDR Fanout coilings of Feiteng processor beneath chips, due to wiring space
Limitation, cable run distance ground hole is nearer, and the reference which results in part cabling becomes many, and the loss of signal reduces, the rising edge of signal
Slow down, the nearer cabling in distance ground hole uploads delivery signal, and than being uploaded with other normal cablings of group, delivery signal is slow, and this may lead
Beyond standard when causing the isometric of part cabling but waiting, this can destroy the sequence problem of DDR so that DDR cisco unity malfunctions are in volume
Determine frequency.
Therefore how to ensure the sequential of DDR, and the workload of wiring installation teacher need not be increased, as this area skill
Art personnel's problem demanding prompt solution.
Utility model content
The technical problems to be solved in the utility model is the drawbacks described above for overcoming prior art to exist, there is provided one kind printing
Circuit board, ensure that the sequential of DDR, and need not increase the workload of wiring installation teacher.
The utility model provides a kind of printed circuit board (PCB), including the fixed plate body of laminated thickness, is set on the plate body
Chip, holding wire and some ground hole are equipped with, when the point on the holding wire on plate body and ground pitch-row are from less than predeterminable range, it is determined that
It is the location point that needs are emptied, in the holding wire location point for needing to empty, its corresponding reference layer sets etched-off area.
Preferably, the predeterminable range is 2 times of line widths of holding wire.
Preferably, the holding wire location point correspondence reference layer specially nearest ground of distance signal line for needing to empty
Layer.
Preferably, the sheet material influence etched-off area position of the printed circuit board (PCB), shape and area.
Preferably, etched-off area position, shape and area determine to be specially：According on determination printed circuit board (PCB), chip is set
Model, laminated thickness, the outgoing line linewidth of beneath chips and line spacing, set up with via, hole and holding wire simulation model；
, it is necessary to be drawn according to the initial value of etched-off area on the holding wire location point emptied its corresponding reference layer in simulation model
Vacancy is managed, and on being carried out without ground hole influence simulation model, the signal model for having the simulation model of ground hole influence and emptying after treatment
Simulation analysis；Signal parameter of contrast when influence without ground hole and signal parameter when thering is ground hole to influence but empty treatment, and
And constantly the position of adjustment etched-off area, shape and area are iterated optimization, optimal compensation situation are found, so as to obtain most
The position of suitable etched-off area, shape and area.
By the vertical intersection in signal with ground hole, sub-fraction is emptied on the reference stratum of holding wire, so as to compensate
Holding wire distance ground hole is relatively closely and to the influence of rising edge.The influence that holding wire relatively closely brings with ground hole can be eliminated, can
Ensure the sequential of DDR, such that it is able to formulate the relative loose coiling specification of a bit, and the work of wiring installation teacher need not be increased
Amount, reduces design difficulty and time cost.
Brief description of the drawings
Fig. 1 is the printed circuit board (PCB) schematic diagram of single Via signal line；
It is the printed circuit board (PCB) schematic diagram in the ground hole of 4mil apart from cabling spacing that Fig. 2 is 3；
Fig. 3 empties a square on Fig. 2 for the first that the utility model is provided below the cabling neighboringly position in hole
The printed circuit board (PCB) schematic diagram of shape block；
It without ground hole without emptying structure and having 3 is the ground pore model emulation insertion loss of 4mil apart from cabling spacing that Fig. 4 is
Comparison diagram；
Fig. 5 be without ground hole without empty structure and have 3 apart from cabling spacing for the ground pore model emulation rising edge of 4mil prolongs
Slow curve comparison figure；
Fig. 6 be without ground hole without empty structure and have 3 apart from cabling spacing for the model that the ground hole and having of 4mil is emptied is imitated
True insertion loss comparison diagram；
Fig. 7 be without ground hole without empty structure and have 3 apart from cabling spacing for the model that the ground hole and having of 4mil is emptied is imitated
True rise edge delay curve comparison figure.
Specific embodiment
In order that those skilled in the art more fully understand the technical solution of the utility model, below in conjunction with the accompanying drawings to this
Utility model is described in further detail.
Referring to Fig. 1 to Fig. 7, Fig. 1 is the printed circuit board (PCB) schematic diagram of single Via signal line, and Fig. 2 is 3 apart between cabling
Away from the printed circuit board (PCB) schematic diagram in the ground hole for 4mil, Fig. 3 is neighbouring in cabling on Fig. 2 for the first that the utility model is provided
A printed circuit board (PCB) schematic diagram for rectangular block is emptied in the position lower section in ground hole, Fig. 4 be without ground hole without empty structure and have 3 away from
It is the ground pore model emulation insertion loss comparison diagram of 4mil from cabling spacing, Fig. 5 is without emptying structure and have 3 distances without ground hole
Cabling spacing is the ground pore model emulation rise edge delay curve comparison figure of 4mil, and Fig. 6 is without emptying structure and have 3 without ground hole
Apart from cabling spacing is for the ground hole of 4mil and has the model emulation insertion loss comparison diagram emptied, Fig. 7 is without emptying knot without ground hole
Structure and have 3 apart from cabling spacing for 4mil ground hole and have the model emulation rise edge delay curve comparison figure emptied.
The utility model provides a kind of printed circuit board (PCB), including the fixed plate body 1 of laminated thickness, on the plate body 1
Chip, holding wire 2 and some ground hole 4, via 3 are provided with, when the point on the holding wire 2 on plate body 1 with ground hole 4 apart from being less than
During predeterminable range, it is defined as the location point for needing to empty, its corresponding reference layer is set in the holding wire location point for needing to empty
Etched-off area 5.
The region that the utility model is primarily present is to the outlet region below Feiteng processor chip package, before design
Phase, after the chip model that is set on printed circuit board (PCB) is selected, can be obtained between the signal pins of chip by chip handbook
Spacing, after the laminated thickness of design determines, to ensure the impedance of signal lead, the outgoing line linewidth of beneath chips is with line spacing then
Can determine whether, because the signal pins of chip are fixed, i.e., the point on holding wire is fixed with the position in ground hole with spacing, in this way,
Can determine that the nearer location point in holding wire distance ground hole.When the point on the holding wire on printed circuit board (PCB) with ground pitch-row from being less than
During predeterminable range, it is defined as the location point for needing to empty.By the vertical intersection in signal with ground hole, in the reference of holding wire
Sub-fraction is emptied on stratum, so that the liftoff hole of thermal compensation signal line-spacing is relatively closely and to the influence of rising edge.Can eliminate holding wire with
The influence that ground hole is relatively near and brings, ensure that the sequential of DDR, such that it is able to formulate the relative loose coiling specification of a bit, and
The workload of wiring installation teacher need not be increased, design difficulty and time cost is reduced.
When the point on the holding wire on printed circuit board (PCB) and ground pitch-row are from less than predeterminable range, it is defined as needing what is emptied
Location point.The location point that needs are emptied can be multiple.
Etched-off area is at least one, location point one etched-off area of correspondence that can be emptied with each needs, it is also possible to if
Dry location point one etched-off area of correspondence for needing to empty, etched-off area position, shape and area can be determined by emulating.
Fig. 4 is insertion loss comparison diagram, and wherein solid line is the insertion loss of the normal cabling without the influence of ground hole, and dotted line is increasing
3 insertion loss influenceed for the ground hole of 4mil apart from cabling spacing, the insertion loss have been added to be specially signal by one section
After transmission line, a loss of energy.Fig. 5 is rise edge delay curve map, and wherein solid line is without emptying under structure without ground hole
Delay curve, dotted line is have the delay curve under 3 ground pore structures.
Find out from Fig. 4 and Fig. 5, behind addition ground hole, the insertion loss of signal diminishes, and signal quality slightly has lifting, and letter
Number rising edge slowed down about 1ps, required in general DDR coiling specifications, with group holding wire delay variance no more than 2ps,
And the 3 ground hole that has been only many, then the error of 1ps can be caused to the delay of signal, substantially increase the difficulty of coiling.
Fig. 6 is insertion loss comparison diagram, and wherein solid line is the insertion loss of the normal cabling without the influence of ground hole, and point short-term is
It is the ground hole influence of 4mil apart from cabling spacing to have 3, and dotted line is have 3 apart from the ground hole influence that cabling spacing is 4mil and carry out
Reference layer empties the insertion loss of the cabling for the treatment of.Fig. 7 is rise edge delay curve map, and wherein solid line is without emptying without ground hole
Delay curve under structure, dotted line is the delay curve for having 3 ground holes and increase to empty under structure.
Find out from Fig. 6 and Fig. 7, after structure is emptied in increase, insertion loss obtains certain compensation, time delay with it is initial
Structure without ground hole is compared and also has certain optimization, and the rise edge delay in figure is substantially eliminated.
In further scheme, the predeterminable range is 2 times of line widths of holding wire.
If the line width that the point on holding wire is less than 2 times with the vertical range in ground hole 4, then the loss of signal reduces, letter
Number rising edge slow down, the nearer holding wire in distance ground hole uploads delivery signal and uploads delivery signals than other the normal cablings with group
Slowly, then need to carry out emptying treatment.
In further scheme, the holding wire location point correspondence reference layer specially distance signal for needing to empty
The nearest stratum of line.
The plate body 1 of printed circuit board (PCB) include plurality of conductive layers, the dielectric layer that is located between the two neighboring conductive layer with
And stratum, the conductive layer is provided with holding wire and some ground hole, described ground hole through the plate body thickness and with it is described
Layer electrical connection.The reference layer of holding wire location point its nearest stratum as holding wire that needs are emptied, if empty
Holding wire location point stratum up and down distance it is consistent or roughly the same, then upper and lower stratum is the holding wire that this is emptied
The reference layer of location point.
If desired the holding wire location point emptied has upper and lower two reference layers, then etched-off area may be located at two-layer ginseng
Examine wherein one layer of layer, it is also possible to be respectively provided with etched-off area on two-layer reference layer.
Etched-off area 5 determines to be specially：Chip model, laminated thickness, chip are pre-seted according on determination printed circuit board (PCB)
The outgoing line linewidth of lower section and line spacing, set up with via, hole and holding wire simulation model；In simulation model, it is necessary to
Carried out emptying treatment according to the initial value of etched-off area on the holding wire location point emptied its corresponding reference layer, and to without ground hole
The signal model for influence simulation model, having the simulation model of ground hole influence and emptying after treatment carries out simulation analysis；Contrast is without ground
Signal parameter when hole influences and the signal parameter for having the influence of ground hole but when empty treatment, and constantly adjust etched-off area
Position, shape and area be iterated optimization, optimal compensation situation is found, so as to obtain the position of most suitable etched-off area
Put, shape and area.
Emulated according to simulation model, signal parameter when contrast influences without ground hole influences but drawn with there is ground hole
Signal parameter when vacancy is managed, and constantly the position of adjustment etched-off area, shape and area are iterated optimization, find optimal
Compensation situation, so that it is determined that the position of most suitable etched-off area, shape and area.
Referring to Fig. 3, Fig. 3 draws on Fig. 2 for the first that the utility model is provided below the cabling neighboringly position in hole
An empty printed circuit board (PCB) schematic diagram for rectangular block；
Holding wire distance ground hole is nearer, and line capacitance is walked equivalent to increase holding wire, is emptied by reference layer, increases
To compensate influence of the hole to holding wire of the loop inductance of big holding wire.But etched-off area can not infinitely increase, in chip
The region of lower section, outlet is more, and layout area is nervous, and etched-off area can equally be restricted, and, excessive empties area
（It is primarily referred to as width）, the line width line spacing of cabling can be caused bigger, then can cause that cable run distance ground hole is nearer, due to ground hole
Limitation, then the region emptied in reference layer, its length can not be too big, due to the presence in ground hole, cannot just be drawn near ground hole
Vacancy is managed, and ground hole is usually note copper hole, if emptied near ground hole, can cause that ground hole deforms in the pad of reference layer,
Cause other influences difficult to the appraisal.It is thus appropriate to increase the area for emptying rectangle, including length, width, loop electricity can be caused
Sense increase, is more beneficial for reducing influence of the near ground hole to signal.
Preferably, the sheet material influence etched-off area position of the printed circuit board (PCB), shape and area.Set on printed circuit board (PCB)
After putting chip model and laminated thickness determination, the sheet material of printed circuit board (PCB) determines the line width of holding wire cabling in printed circuit board (PCB)
Line spacing, the line width line spacing of holding wire cabling, then can determine holding wire whether distance ground Kong Yi safe range beyond, when
Point on holding wire on printed circuit board (PCB) with ground pitch-row from less than predeterminable range when, then need to carry out emptying treatment, thus print
The sheet material of printed circuit board influences indirect etched-off area position, shape and area.
A kind of printed circuit board (PCB) provided by the utility model is described in detail above.It is used herein specifically
Individual example is set forth to principle of the present utility model and implementation method, and the explanation of above example is only intended to help and understands this
The core concept of utility model.It should be pointed out that for those skilled in the art, it is new this practicality is not departed from
On the premise of type principle, some improvement and modification can also be carried out to the utility model, these are improved and modification also falls into this reality
With in new scope of the claims.
Claims (5)
1. a kind of printed circuit board (PCB), it is characterised in that including the fixed plate body of laminated thickness, core is provided with the plate body
Piece, holding wire and some ground hole, when the point on the holding wire on plate body and ground pitch-row are from less than predeterminable range, are defined as needs
The location point emptied, in the holding wire location point for needing to empty, its corresponding reference layer sets etched-off area.
2. printed circuit board (PCB) according to claim 1, it is characterised in that the predeterminable range is 2 times of line widths of holding wire.
3. printed circuit board (PCB) according to claim 2, it is characterised in that the holding wire location point correspondence that the needs are emptied
Reference layer is specially the nearest stratum of distance signal line.
4. printed circuit board (PCB) according to claim 3, it is characterised in that area is emptied in the sheet material influence of the printed circuit board (PCB)
Domain position, shape and area.
5. according to Claims 1-4 any one printed circuit board (PCB), it is characterised in that etched-off area is specifically by following step
It is rapid to determine：According on determination printed circuit board (PCB), chip model, laminated thickness, the outgoing line linewidth of beneath chips and line spacing are set,
Set up with via, hole and holding wire simulation model；In simulation model, it is necessary to the holding wire location point emptied its correspondence
Reference layer on empty treatment according to the initial value of etched-off area, and on without ground hole influence simulation model, there is the ground hole to influence
Simulation model and empty treatment after signal model carry out simulation analysis；Signal parameter of contrast when being influenceed without ground hole with have ground
Signal parameter when hole influences but empty treatment, and constantly the position of adjustment etched-off area, shape and area are changed
Generation optimization, finds optimal compensation situation, so as to obtain position, shape and the area of most suitable etched-off area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621267014.0U CN206272947U (en) | 2016-11-24 | 2016-11-24 | A kind of printed circuit board (PCB) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621267014.0U CN206272947U (en) | 2016-11-24 | 2016-11-24 | A kind of printed circuit board (PCB) |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206272947U true CN206272947U (en) | 2017-06-20 |
Family
ID=59040551
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621267014.0U Withdrawn - After Issue CN206272947U (en) | 2016-11-24 | 2016-11-24 | A kind of printed circuit board (PCB) |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206272947U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106358364A (en) * | 2016-11-24 | 2017-01-25 | 湖南长城银河科技有限公司 | Printed circuit board and Fanout wiring method |
| CN109299534A (en) * | 2018-09-20 | 2019-02-01 | 深圳市博科技股份有限公司 | A kind of modeling method and device of printed circuit board |
| CN109936913A (en) * | 2017-12-19 | 2019-06-25 | 三星电子株式会社 | Printed circuit board, memory module and the storage system including memory module |
| CN111123065A (en) * | 2018-10-30 | 2020-05-08 | 浙江宇视科技有限公司 | Method and device for inspecting printed circuit board wiring |
-
2016
- 2016-11-24 CN CN201621267014.0U patent/CN206272947U/en not_active Withdrawn - After Issue
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106358364A (en) * | 2016-11-24 | 2017-01-25 | 湖南长城银河科技有限公司 | Printed circuit board and Fanout wiring method |
| CN109936913A (en) * | 2017-12-19 | 2019-06-25 | 三星电子株式会社 | Printed circuit board, memory module and the storage system including memory module |
| CN109936913B (en) * | 2017-12-19 | 2024-06-04 | 三星电子株式会社 | Printed circuit board, memory module and memory system including the same |
| CN109299534A (en) * | 2018-09-20 | 2019-02-01 | 深圳市博科技股份有限公司 | A kind of modeling method and device of printed circuit board |
| CN111123065A (en) * | 2018-10-30 | 2020-05-08 | 浙江宇视科技有限公司 | Method and device for inspecting printed circuit board wiring |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20170620 Effective date of abandoning: 20230428 |
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| AV01 | Patent right actively abandoned |
Granted publication date: 20170620 Effective date of abandoning: 20230428 |