CN220653602U - DDRX interconnection equal-arm branch topological structure with trunk impedance sectionally controlled - Google Patents
DDRX interconnection equal-arm branch topological structure with trunk impedance sectionally controlled Download PDFInfo
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Abstract
The utility model discloses a DDRX interconnection equal-arm branch topological structure controlled by trunk impedance segmentation, which comprises a main chip, wherein the main chip is connected with trunk wires, the trunk wires are connected with at least two branch wires, each branch wire is connected with a load chip, the trunk wires are divided into a first trunk wire section and a second trunk wire section, the first trunk wire section is close to the main chip, the second trunk wire section is close to the branch wires, the characteristic impedance of the second trunk wire section and the characteristic impedance of the branch wires are the same, and the characteristic impedance of the first trunk wire section is smaller than the characteristic impedance of the second trunk wire section. The utility model improves the signal integrity and achieves the aim of improving the signal quality by carrying out sectional control on the characteristic impedance of the wiring of the trunk part of the equal-arm branch topology.
Description
Technical Field
The utility model relates to the technical field of PCB design, in particular to a DDRX interconnection equal-arm branch topological structure with main impedance sectional control.
Background
Printed circuit boards (Printed Circuit Board, PCB boards), also known as printed circuit boards, are an important component of the physical support and signal transmission of electronic products. With the update and upgrade of DDR (Double Data RateSynchronous Dynamic Random Access Memory) technology, the non-ideal effect of the interconnection link is more and more remarkable, mainly in the case of multiple loads, because of the branches and the more loaded chips, the influence of the capacitive load is unavoidable, firstly, the common via is capacitive, secondly, the parasitic capacitance (about 0.33-0.44 pF) on the chip package, and furthermore, the parasitic capacitance (about 0.77-2.12 pF) on Die (chip Die, form before packaging), all of which can reduce the effective characteristic impedance of the signal transmission path, resulting in the discontinuity of the impedance of the signal path and further the reflection of the signal, thereby restricting the realization of high-speed multiple-load DDRX ("X" represents DDR technology of different generations) interconnection design.
At present, in the existing multi-load DDRX interconnection equal-arm branch topology (as shown in fig. 1), each section of wiring of the same signal is controlled to have the same characteristic impedance value (usually, the single-end line impedance is controlled to be 50 ohms), and actually, due to the influence of capacitive load, the effective characteristic impedance of a signal path can be changed, so that the impedance of the signal path is discontinuous, and further, the signal is reflected, so that the signal quality of a near-end load chip is affected.
The above disadvantages are to be improved.
Disclosure of Invention
In order to solve the problems that signal path impedance is discontinuous, signal reflection is caused and signal quality of a near-end load chip is affected in multi-load DDRX interconnection equal-arm branch topology in the prior art, the utility model provides a DDRX interconnection equal-arm branch topology structure with trunk impedance sectionally controlled.
The technical scheme of the utility model is as follows:
the utility model provides a DDRX interconnection equal arm branch topological structure of trunk impedance sectional control, includes the main chip, the main chip is connected with the trunk and walks the line, the trunk is walked the line and is connected with two at least branches and walks the line, every branch walks the line and is connected with a load chip, the trunk walks the line and divide into first trunk and second trunk and walk the line segment, first trunk is walked the line segment and is close to the main chip, second trunk is walked the line segment and is close to the branch and walks the line, second trunk walk the line segment the characteristic impedance of branch and walk the line is the same, the characteristic impedance of first trunk is walked the line segment and is less than the characteristic impedance of second trunk and walk the line segment.
According to the DDRX interconnection equal-arm branch topological structure controlled by the trunk impedance section of the scheme, the characteristic impedance of the second trunk wiring section and the characteristic impedance of the branch wiring are both 50 ohms, and the characteristic impedance of the first trunk wiring section is 30-48 ohms.
Further, when the number of the load chips is 2, the characteristic impedance of the first trunk line segment is 48 ohms; when the number of the load chips is 4, the characteristic impedance of the first main wiring section is 40 ohms; when the number of the load chips is 8, the characteristic impedance of the first main line segment is 30 ohms.
According to the DDRX interconnection equal-arm branch topological structure with the main impedance sectionalized control, the branch wirings comprise a first-stage branch wiring and a second-stage branch wiring, the main wirings are connected with at least two first-stage branch wirings, each first-stage branch wiring is connected with at least two second-stage branch wirings, each second-stage branch wiring is connected with one load chip, and the characteristic impedance of the second main wiring section, the first-stage branch wirings and the characteristic impedance of the second-stage branch wirings are the same.
Further, the characteristic impedance of the second main line segment, the first branch line segment and the second branch line segment is 50 ohms, and the characteristic impedance of the first main line segment is 30-48 ohms.
Further, when the number of the load chips is 4, the characteristic impedance of the first trunk line segment is 40 ohms; when the number of the load chips is 8, the characteristic impedance of the first main line segment is 30 ohms.
According to the DDRX interconnection equal-arm branch topological structure controlled by the trunk impedance section, the lengths of the first trunk line segment and the second trunk line segment are the same.
According to the DDRX interconnection equal-arm branch topological structure controlled by the trunk impedance segment, the ratio of the characteristic impedance of the first trunk line segment to the characteristic impedance of the second trunk line segment is controlled to be 0.7:1.
according to the DDRX interconnection equal-arm branch topological structure controlled by the main impedance section, the number of branch wirings is even.
According to the DDRX interconnection equal-arm branch topological structure controlled by the main impedance section of the scheme, the length and the width of each branch wire are the same.
According to the DDRX interconnection equal-arm branch topological structure with the main impedance sectionally controlled by the scheme, through holes are formed in two ends of the main wiring, and through holes are formed in one end of the primary branch wiring.
Compared with the prior art, the utility model has the beneficial effects that:
according to the DDRX interconnection equal-arm branch topological structure, the main wiring is divided into the first main wiring section and the second main wiring section (the total length is kept unchanged), and the characteristic impedance of the main wiring of the equal-arm branch topological is controlled in a segmentation mode, so that signals passing through the main wiring section and signals reflected to the main wiring section are reflected to the main wiring section to generate opposite positive and negative reflections to offset each other, accumulation of reflected signals at a near-end load chip is effectively reduced, redundant energy of back-and-forth reflection oscillation in the topology is reduced, signal integrity is improved, and the purpose of improving signal quality is achieved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings that are needed in the embodiments or the description of the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present utility model, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a multi-load DDRX interconnection equal-arm branch topology in the prior art, wherein Z0 represents characteristic impedance of each section of wiring;
fig. 2 is a schematic structural diagram of a branch topology structure of DDRX interconnection equal arms controlled by trunk impedance segmentation in embodiment 1 of the present utility model, where Z0 and Z1 represent characteristic impedance of each segment of wiring;
FIG. 3 is a signal receiving waveform diagram of the load chip of FIG. 1;
FIG. 4 is a signal receiving waveform diagram of the load chip of FIG. 2;
fig. 5 is a schematic structural diagram of a branch topology structure of DDRX interconnection equal arms controlled by trunk impedance segmentation in embodiment 2 of the present utility model, where Z0 and Z1 represent characteristic impedance of each segment of wiring;
FIG. 6 is a diagram showing a microstrip line impedance calculation structure;
fig. 7 is a diagram showing a structure of calculating the stripline impedance.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the utility model is further described in detail below with reference to the accompanying drawings and embodiments. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, it is stated that the embodiments described below are only for explaining the present utility model and are not intended to limit the present utility model.
It should be noted that, the terms "disposed," "connected," and the like should be understood in a broad sense, and for example, may be fixedly connected, detachably connected, or integrated; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The direction orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship which is commonly put when the product of the application is used, or the orientation or positional relationship which is commonly understood by those skilled in the art, or the orientation or positional relationship which is commonly put when the product of the application is used, only for convenience of description of the application and simplification of description, and is not intended to indicate or imply that the device or element to be referred must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the application. The terms "first," "second," and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features.
Example 1
Referring to fig. 2, the embodiment provides a main impedance sectionally controlled DDRX interconnection equal-arm branch topological structure, which comprises a main chip Memory Controller, wherein the main chip Memory Controller is connected with a main branch line L1, the main branch line L1 is connected with at least two primary branch lines L2, the length and the width of each primary branch line L2 are the same, each primary branch line L2 is connected with at least two secondary branch lines L3, the length and the width of each secondary branch line L3 are the same, each secondary branch line L3 is connected with a load chip DRAM, both ends of the main branch line L1 are provided with via holes via, and one end of the primary branch line L2, which is close to the secondary branch line L3, is provided with via holes via. The main line L1 is divided into a first main line L11 and a second main line L12, the lengths of the first main line L11 and the second main line L12 are the same (the sum of the first main line L11 and the second main line L12 is consistent with that before segmentation), the first main line L11 is close to the main chip Memory Controller, the second main line L12 is close to the first branch line L2, the characteristic impedance Z0 of the second main line L12, the first branch line L2 and the second branch line L3 is the same as 50 ohms, the characteristic impedance Z1 of the first main line L11 is smaller than the characteristic impedance Z0 of the second main line L12, and the characteristic impedance Z1 of the first main line L11 is 30-48 ohms.
In this embodiment, the trunk wiring L1 is divided into the first trunk wiring L11 and the second trunk wiring L12 (the total length remains unchanged), so that the characteristic impedance of the trunk wiring of the equal-arm branch topology is controlled in a segmented manner, so that the signal passing through the place and the signal reflected to the place are reflected to generate opposite positive and negative reflections to cancel each other, thereby effectively reducing the accumulation of the reflected signal at the near-end load chip, reducing the redundant energy of the back-and-forth reflection oscillation in the topology, improving the signal integrity, and achieving the purpose of improving the signal quality.
Fig. 3 is a signal receiving waveform diagram of a load chip DRAM in the existing topology scheme, and fig. 4 is a signal receiving waveform diagram of the load chip DRAM after the characteristic impedance of the first main line segment L11 is adjusted to 40 ohms while the characteristic impedance of the second main line segment L12 is kept unchanged by 50 ohms.
In a preferred embodiment, the characteristic impedance Z1 of the first trunk line segment L11 is adjusted according to the number of the driven load chip DRAMs, the number of the load chip DRAMs is increased, the characteristic impedance Z1 of the first trunk line segment L11 is smaller, and meanwhile, the line width of the first trunk line segment L11 should be reasonably adjusted in consideration of the wiring space. Under the condition that the characteristic impedance Z0 of the second main line segment L12, the first branch line segment L2 and the second branch line segment L3 is controlled to be 50 ohms, when the number of the load chips DRAM is 4, the characteristic impedance Z1 of the first main line segment L11 is adjusted to be 40 ohms; when the number of the load chips DRAM is 8, the characteristic impedance Z1 of the first main line segment L11 is adjusted to be 30 ohms.
In a preferred embodiment, the ratio of the characteristic impedance Z1 of the first main trace L11 to the characteristic impedance of the second main trace L12Z0 is controlled to be 0.7: and 1, the characteristic impedance of the signal path tends to be consistent, the impedance continuity is improved, and the signal integrity is improved.
In a preferred embodiment, the number of the first-stage branch wirings L2 and the second-stage branch wirings L3 is even, so that the characteristic impedance of the signal path can be further made to be consistent, and the impedance continuity can be improved.
Example 2
Referring to fig. 5, the present embodiment provides a main impedance sectionally controlled DDRX interconnection equal-arm branch topology structure, which includes a main chip Memory Controller, the main chip Memory Controller is connected with a main trace L1, the main trace L1 is connected with at least two branch traces L3, the length and width of each branch trace L3 are the same, each branch trace L3 is connected with a load chip DRAM, and both ends of the main trace L1 are provided with via holes via. The trunk line L1 is divided into a first trunk line segment L11 and a second trunk line segment L12, the lengths of the first trunk line segment L11 and the second trunk line segment L12 are the same (the sum of the first trunk line segment L11 and the second trunk line segment L12 is consistent with that before segmentation), the first trunk line segment L11 is close to the main chip Memory Controller, the second trunk line segment L12 is close to the branch line L3, the characteristic impedance Z0 of the second trunk line segment L12 and the branch line segment L3 are the same and are both 50 ohms, the characteristic impedance Z1 of the first trunk line segment L11 is smaller than the characteristic impedance Z0 of the second trunk line segment L12, and the characteristic impedance Z1 of the first trunk line segment L11 is 30-48 ohms.
In this embodiment, the trunk wiring L1 is divided into the first trunk wiring L11 and the second trunk wiring L12 (the total length remains unchanged), so that the characteristic impedance of the trunk wiring of the equal-arm branch topology is controlled in a segmented manner, so that the signal passing through the place and the signal reflected to the place are reflected to generate opposite positive and negative reflections to cancel each other, thereby effectively reducing the accumulation of the reflected signal at the near-end load chip, reducing the redundant energy of the back-and-forth reflection oscillation in the topology, improving the signal integrity, and achieving the purpose of improving the signal quality.
In a preferred embodiment, the characteristic impedance Z1 of the first trunk line segment L11 is adjusted according to the number of the driven load chip DRAMs, the number of the load chip DRAMs is increased, the characteristic impedance Z1 of the first trunk line segment L11 is smaller, and meanwhile, the line width of the first trunk line segment L11 should be reasonably adjusted in consideration of the wiring space. Under the condition that the characteristic impedance Z0 of the second main line segment L12 and the branch line segment L3 is controlled to be 50 ohms, when the number of the load chip DRAM is 2, the characteristic impedance Z1 of the first main line segment L11 is adjusted to be 48 ohms; when the number of the load chips DRAM is 4, the characteristic impedance Z1 of the first main wiring section L11 is adjusted to 40 ohms; when the number of the load chips DRAM is 8, the characteristic impedance Z1 of the first main line segment L11 is adjusted to be 30 ohms.
In a preferred embodiment, the number of the branch lines L3 is even, so that the characteristic impedance of the signal paths tends to be uniform, and the impedance continuity is improved.
In a PCB design, in order to reduce or increase the characteristic impedance (Zo) of a trace, on the premise of determining the stack (the stacks of different veneers may differ, which means that Er, T, H in the calculation formula of the characteristic impedance of the trace are different, if the stack of veneers is determined, er, T, H is determined accordingly), according to the calculation formulas of microstrip line impedance and strip line impedance, impedance adjustment may be achieved by increasing or decreasing the corresponding width of the trace (W in the formula):
as shown in fig. 5, microstrip line impedance (skin line):
(Validwhen 0.1<W/H<2.0and1<Er<15)
zo represents a characteristic impedance; er represents the dielectric constant; w represents the width of the wiring; t represents the thickness of the wiring copper; h denotes the spacing of the trace from the adjacent reference plane.
As shown in fig. 6, the strip line impedance (inner layer routing):
(Valid·when·W/H＜0.35·and·T/H＜0.25)
here, H denotes a pitch between adjacent reference planes.
It will be understood that modifications and variations will be apparent to those skilled in the art from the foregoing description, and it is intended that all such modifications and variations be included within the scope of the following claims.
While the utility model has been described above with reference to the accompanying drawings, it will be apparent that the implementation of the utility model is not limited by the above manner, and it is within the scope of the utility model to apply the inventive concept and technical solution to other situations as long as various improvements made by the inventive concept and technical solution are adopted, or without any improvement.
Claims (10)
1. The utility model provides a DDRX interconnection equal arm branch topological structure of trunk impedance sectional control, includes the main chip, the main chip is connected with the trunk and walks the line, the trunk walks the line and is connected with two at least branches and walks the line, every branch walks the line and is connected with a load chip, its characterized in that, the trunk walks the line and divide into first trunk and walks the line with the second trunk, first trunk is walked the line and is close to the main chip, second trunk is walked the line and is close to the branch and walks the line, the second trunk walk the line with the characteristic impedance of branch and be the same, the characteristic impedance of first trunk walk the line is less than the characteristic impedance of second trunk walk the line.
2. The DDRX interconnect equal arm branch topology of claim 1, wherein the characteristic impedance of the second trunk trace and the characteristic impedance of the branch trace are both 50 ohms, and the characteristic impedance of the first trunk trace is 30-48 ohms.
3. The DDRX interconnect equal arm branch topology of claim 2, wherein when the number of load chips is 2, the characteristic impedance of the first trunk trace segment is 48 ohms; when the number of the load chips is 4, the characteristic impedance of the first main wiring section is 40 ohms; when the number of the load chips is 8, the characteristic impedance of the first main line segment is 30 ohms.
4. The DDRX interconnect equal arm branch topology of claim 1, wherein said branch trace comprises a first branch trace and a second branch trace, said main trace is connected with at least two said first branch traces, each said first branch trace is connected with at least two said second branch traces, each said second branch trace is connected with one said load chip, and the characteristic impedance of said second main trace, said first branch trace and said second branch trace are the same.
5. The DDRX interconnect equal arm branch topology of claim 4, wherein the characteristic impedance of said second trunk trace segment, said primary branch trace and said secondary branch trace are all 50 ohms, and the characteristic impedance of said first trunk trace segment is 30-48 ohms.
6. The DDRX interconnect equal arm branch topology of claim 5, wherein when the number of load chips is 4, the characteristic impedance of the first trunk trace segment is 40 ohms; when the number of the load chips is 8, the characteristic impedance of the first main line segment is 30 ohms.
7. The DDRX interconnect equal arm branch topology of claim 1, wherein said first and second trunk trace segments are the same length.
8. The DDRX interconnect equal arm branch topology of claim 1, wherein the ratio of the characteristic impedance of the first trunk trace segment to the characteristic impedance of the second trunk trace segment is controlled to be 0.7:1.
9. the DDRX interconnect equal arm branch topology of claim 1, wherein the branch traces have an even number of branches.
10. The DDRX interconnect equal arm branch topology of claim 1, wherein each of said branch traces has the same length and width.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202321866392.0U CN220653602U (en) | 2023-07-17 | 2023-07-17 | DDRX interconnection equal-arm branch topological structure with trunk impedance sectionally controlled |
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| CN202321866392.0U CN220653602U (en) | 2023-07-17 | 2023-07-17 | DDRX interconnection equal-arm branch topological structure with trunk impedance sectionally controlled |
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