CN219435332U

CN219435332U - Structure of multi-load DDRX interconnection clamshell topology trunk impedance

Info

Publication number: CN219435332U
Application number: CN202320483141.8U
Authority: CN
Inventors: 姜杰; 吴均
Original assignee: Edadoc Co ltd
Current assignee: Edadoc Co ltd
Priority date: 2023-03-14
Filing date: 2023-03-14
Publication date: 2023-07-28
Anticipated expiration: 2033-03-14

Abstract

The utility model discloses a multi-load DDRX interconnection clamshell topology trunk impedance structure, which comprises a main chip and a plurality of load chips, wherein the main chip is connected with a main link, the load chips are connected with branch links, the load chips are connected with the main link through the branch links, the load chips are symmetrically arranged on two sides of the main link, the main link is provided with a main path characteristic impedance at one end close to the main chip, the main path characteristic impedance is provided with two sections which are respectively a first main path impedance and a second main path impedance, and the first main path impedance is closer to the main chip than the second main path impedance. The utility model performs sectional control on the main path characteristic impedance of the main line of the clamshell topology trunk part, so that the signal passing through the main line and the signal reflected to the main line are mutually offset by generating positive and negative opposite reflections, thereby effectively reducing the accumulation of the reflected signal at the near-end load chip, reducing the redundant energy of back and forth reflection oscillation in the topology and improving the signal integrity.

Description

Structure of multi-load DDRX interconnection clamshell topology trunk impedance

Technical Field

The utility model relates to the technical field of memory topological structures, in particular to a multi-load DDRX interconnection clamshell topological trunk impedance structure.

Background

Printed circuit boards (Printed Circuit Board, PCB boards), also known as printed circuit boards, are an important component of the physical support and signal transmission of electronic products. Along with the update and upgrade of DDR (Double Data Rate Synchronous Dynamic Random Access Memory) technology, the signal rate is continuously improved, the non-ideal effect of the interconnection link is more and more remarkable, the main appearance is that under the condition of multiple loads, the operating rate is higher and higher due to more branches and load chips, the influence of reflection on the signal is larger and larger, and the design difficulty is increased increasingly. A common multi-load Clamshell (Clamshell) topology (as shown in fig. 1) can be symmetrically arranged on the surface and bottom layers of a PCB board (similar to a Clamshell), so that layout space can be saved greatly, and the application is becoming wider.

However, since signal reflections accumulate mostly at the first pair of DDR chips closest to the main chip, the signal quality of these two symmetrically laid out DDR chips is relatively poor, and therefore, the signal quality of the first pair of DDR chips closest to the main chip often becomes a bottleneck that limits the channel operation rate. As shown in fig. 2, one main chip drives a clamshell topology of 5 DDR chips, with the signal quality of DRAM1 and DRAM2 being the worst.

The above disadvantages are to be improved.

Disclosure of Invention

In order to solve the problem that signal quality of two DDR chips at the near end of a main chip in the existing multi-load clamshell topology is relatively poor and becomes a bottleneck for limiting the running speed of a channel, the utility model provides a multi-load DDRX interconnection clamshell topology trunk impedance structure.

The technical scheme of the utility model is as follows:

the utility model provides a structure of multi-load DDRX interconnection clamshell topology trunk impedance, includes main chip and a plurality of load chip, the main chip is connected with the main link, the load chip is connected with the branch link, the load chip pass through the branch link with the main link is connected, each the load chip pair symmetry sets up the both sides of main link, one arbitrary setting that falls in the load chip is in one side of main link, the main link is being close to the one end of main chip is provided with main link characteristic impedance, main link characteristic impedance is provided with two sections, is first main link impedance and second main link impedance respectively, first main link impedance is more close to than second main link impedance the main chip.

In the structure of the multi-load DDRX interconnection clamshell topology trunk impedance, the length of the first main path impedance is not smaller than the length of the second main path impedance.

Further, the ratio of the length of the first main impedance to the length of the second main impedance is 2:1.

In the above-mentioned structure of multi-load DDRX interconnect clamshell topology trunk impedance, the impedance value of the first main path impedance is not greater than the impedance value of the second main path impedance.

Further, a ratio of the impedance value of the first main path impedance to the impedance value of the second main path impedance is 0.63 to 0.67.

Further, a ratio of the impedance value of the first main impedance to the impedance value of the second main impedance is 0.65.

In the above structure of the multi-load DDRX interconnection clamshell topology trunk impedance, the impedance value of the first main path impedance is 33 Ω to 43 Ω.

In the structure of the multi-load DDRX interconnection clamshell topology trunk impedance, the branch links are all provided with branch impedances, and the impedance values of the branch impedances of the branch links are equal.

In the structure of the multi-load DDRX interconnection clamshell topology trunk impedance, the main link is provided with routing impedances between each pair of branch links, and the impedance values of the routing impedances are equal.

The multi-load DDRX interconnection clamshell topology trunk impedance structure has the advantages that the main link has equal wiring length between each pair of branch links.

According to the scheme, the utility model has the beneficial effects that the main characteristic impedance of the main line of the main part of the clamshell topology is controlled in a sectionalized manner, the main characteristic impedance is divided into the first main impedance and the second main impedance, so that the signal passing through the main impedance and the signal reflected to the main impedance are mutually offset by generating opposite positive and negative reflections, thereby effectively reducing the accumulation of the reflected signal at the near-end load chip, reducing the redundant energy of back-and-forth reflection oscillation in the topology, and improving the signal integrity.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings that are needed in the embodiments or the description of the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present utility model, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a prior art clam shell topology in cross section;

FIG. 2 is a schematic diagram of a prior art clamshell topology;

FIG. 3 is a signal quality diagram of a prior art clamshell topology;

FIG. 4 is a schematic diagram of the structure of the present utility model;

FIG. 5 is a signal quality diagram of the present utility model;

FIG. 6 is a diagram showing a microstrip line impedance calculation structure;

fig. 7 is a diagram showing a structure of calculating the stripline impedance.

Wherein, each reference sign in the figure: 1. a main chip; 2. a load chip; 3. a main link; 4. branching links; 5. main path characteristic impedance; 501. a first main path impedance; 502. a second main path impedance; 6. branch impedance; 7. trace impedance.

Detailed Description

In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the utility model is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model.

It will be understood that when an element is referred to as being "mounted" or "disposed" or "connected" to another element, it can be directly or indirectly on the other element. The directions or positions indicated by the terms "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are directions or positions based on the drawings, and are merely for convenience of description and are not to be construed as limiting the present technical solution. The terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features. The meaning of "multiple" is two or more, unless explicitly defined otherwise. The meaning of "a number" is one or more than one, unless specifically defined otherwise.

As shown in fig. 4, in an embodiment of the present utility model, a multi-load DDRX interconnection clamshell topology trunk impedance structure includes a main chip 1 and a plurality of load chips 2, the main chip 1 is connected with a main link 3, the load chips 2 are connected with branch links 4, the load chips 2 are connected with the main link 3 through the branch links 4, each load chip 2 is symmetrically arranged on two sides of the main link 3 in pairs, one of the load chips 2 is arbitrarily arranged on one side of the main link 3, in practical design application, the present utility model is applied to a circuit board, the main link 3 and the branch links 4 are arranged on conductive layers of the circuit board, two sides of the main link 3, namely, a top layer and a bottom layer of the circuit board, wherein the main chip 1 and the load chips 2 are arranged on the top layer or the bottom layer of the circuit board, and two load chips 2 in pairs are symmetrically arranged on the top layer and the bottom layer of the circuit board. The main link 3 is provided with a main path characteristic impedance 5 at one end close to the main chip 1, the main path characteristic impedance 5 is provided with two sections, namely a first main path impedance 501 and a second main path impedance 502, and the first main path impedance 501 is closer to the main chip 1 than the second main path impedance 502.

As shown in fig. 2, the clamshell topology of the main chip 1 driving multiple load chips 2 is very challenging, and especially the load chip 2 nearest to the main chip 1 will typically have a larger fluctuation of its signal due to the back and forth reflection of the signal of other load chips 2 later, thereby seriously affecting the signal quality. How to find a simple and effective way to reduce the accumulation of signal reflections at the near-end load chip 2, and thus reduce the signal energy reflected back and forth within the topology, and improving the signal quality is urgent.

In this example, the main characteristic impedance 5 of the main line of the clamshell topology trunk is controlled in a segmented manner, the main characteristic impedance 5 is divided into a first main impedance 501 and a second main impedance 502, so that the signal passing through the position and the signal reflected to the position are reflected to generate opposite positive and negative reflections to cancel each other, thereby effectively reducing the accumulation of the reflected signal at the position of the near-end load chip 2, reducing the redundant energy of back-and-forth reflection oscillation in the topology, and improving the signal integrity. Fig. 3 is a signal quality diagram of a conventional scheme, fig. 5 is a signal quality diagram of the present application, and comparing fig. 3 and fig. 5 can show that the eye diagram of the present application has a larger eye height, which is about 145mV more than that of the conventional method, which is equivalent to improving the signal margin by 49%.

In a preferred example, the length of the first main impedance 501 is not less than the length of the second main impedance 502. Typically, the ratio of the length of the first main impedance 501 to the length of the second main impedance 502 is 2:1.

In a preferred embodiment, the impedance value of the first main impedance 501 is not greater than the impedance value of the second main impedance 502, and generally, the ratio of the impedance value of the first main impedance 501 to the impedance value of the second main impedance 502 is 0.63 to 0.67, and preferably, the ratio of the impedance value of the first main impedance 501 to the impedance value of the second main impedance 502 is 0.65. The impedance value of the first main impedance 501 is 33 Ω to 43 Ω. The above-described optimal combination is obtained by simulation testing the clamshell topology of the main chip 1 driving the plurality of load chips 2, improving the signal quality.

As shown in fig. 4, in a preferred embodiment, the branch links 4 are provided with branch impedances 6, and the impedance values of the branch impedances 6 of the branch links 4 are equal, so that the characteristic impedance of the signal paths tends to be consistent, thereby improving the impedance continuity and improving the signal integrity.

As shown in fig. 4, in a preferred example, the main link 3 is provided with trace impedances 7 between the pair of branch links 4, and the impedance values of the trace impedances 7 are equal. The size of the wiring impedance 7 between two adjacent branch links 4 is equal, so that the characteristic impedance of the signal paths tends to be consistent, the impedance continuity is improved, and the signal integrity is improved. The main link 3 has equal wiring length between the branch paths 4, which is beneficial to reducing the extra signal loss of the load chip 2 on the back-end branch link 4 caused by inconsistent transmission line impedance.

In a PCB design, in order to reduce or increase the characteristic impedance (Z0) of the trace, on the premise of determining the stack (the stacks of different veneers may differ, which means that Er, T, H in the calculation formula of the characteristic impedance of the trace are different, if the stack of veneers is determined, er, T, H is determined accordingly), according to the calculation formula of the microstrip line impedance and the stripline impedance, the impedance adjustment may be implemented by increasing or decreasing the corresponding width of the trace (W in the formula):

as shown in fig. 6, microstrip line impedance (skin line):

(Valid when 0.1＜W/H＜2.0 and 1＜Er＜15)

z0 represents a characteristic impedance; er represents the dielectric constant; w represents the width of the wiring; t represents the thickness of the wiring copper; h denotes the spacing of the trace from the adjacent reference plane.

As shown in fig. 7, the strip line impedance (inner layer routing):

(Valid when W/H＜0.35 and T/H＜0.25)

the foregoing description of the preferred embodiments of the utility model is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the utility model.

Claims

1. The utility model provides a structure of multi-load DDRX interconnection clamshell topology trunk impedance, includes main chip and a plurality of load chip, the main chip is connected with the main link, the load chip is connected with the branch link, the load chip pass through the branch link with the main link is connected, each the load chip pair symmetry sets up the both sides of main link, one arbitrary setting that falls in the load chip is in one side of main link, the main link is being close to the one end of main chip is provided with main link characteristic impedance, its characterized in that, main link characteristic impedance is provided with two sections, is first main link impedance and second main link impedance respectively, first main link impedance is compared the second main link impedance is nearer the main chip.

2. The structure of multi-load DDRX interconnect clam shell topology trunk impedance of claim 1, wherein the length of said first main path impedance is no less than the length of said second main path impedance.

3. A multi-load DDRX interconnect clamshell topology trunk impedance structure as recited in claim 2, wherein the ratio of the length of said first main path impedance to the length of said second main path impedance is 2:1.

4. A multi-load DDRX interconnect clamshell topology trunk impedance structure as recited in claim 1, wherein an impedance value of said first main path impedance is no greater than an impedance value of said second main path impedance.

5. The multi-load DDRX interconnect clam shell topology trunk impedance structure of claim 4, wherein the ratio of the impedance value of said first main path impedance to the impedance value of said second main path impedance is 0.63 to 0.67.

6. The multi-load DDRX interconnect clam shell topology trunk impedance structure of claim 5, wherein the ratio of the impedance value of said first main path impedance to the impedance value of said second main path impedance is 0.65.

7. A multi-load DDRX interconnect clamshell topology trunk impedance structure as recited in claim 1, wherein said first main impedance has an impedance value of 33 Ω to 43 Ω.

8. A multi-load DDRX interconnect clamshell topology trunk impedance structure as recited in claim 1, wherein said branch links are each provided with a branch impedance, and wherein the impedance values of said branch impedances of each of said branch links are equal.

9. A multi-load DDRX interconnect clamshell topology trunk impedance structure as recited in claim 1, wherein said main link is provided with trace impedances between each pair of said branch links, each of said trace impedances having equal impedance values.

10. A multi-load DDRX interconnect clamshell topology trunk impedance structure as recited in claim 1, wherein said main link has equal trace lengths between each pair of said branch links.