CN209417720U - Binary system is to Gray's conversion circuit and FIFO memory - Google Patents
Binary system is to Gray's conversion circuit and FIFO memory Download PDFInfo
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- CN209417720U CN209417720U CN201920225037.2U CN201920225037U CN209417720U CN 209417720 U CN209417720 U CN 209417720U CN 201920225037 U CN201920225037 U CN 201920225037U CN 209417720 U CN209417720 U CN 209417720U
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
- G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
- G06F5/14—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations for overflow or underflow handling, e.g. full or empty flags
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30029—Logical and Boolean instructions, e.g. XOR, NOT
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/30156—Special purpose encoding of instructions, e.g. Gray coding
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/14—Conversion to or from non-weighted codes
- H03M7/16—Conversion to or from unit-distance codes, e.g. Gray code, reflected binary code
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F2205/10—Indexing scheme relating to groups G06F5/10 - G06F5/14
- G06F2205/102—Avoiding metastability, i.e. preventing hazards, e.g. by using Gray code counters
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F2205/10—Indexing scheme relating to groups G06F5/10 - G06F5/14
- G06F2205/106—Details of pointers, i.e. structure of the address generators
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
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Abstract
The presently disclosed embodiments is related to binary system to Gray's conversion circuit and FIFO memory.Disclose a kind of circuit converted for executing binary system to Gray.First binary signal indicates target value and the second binary signal is stored in register.One group of binary system candidate value is determined, wherein the equivalent Hamming distance that there is the Gray away from the second binary value to be equivalent to 1 of the corresponding Gray of each binary system candidate value.According to one in the selection binary system candidate value of the first binary signal and the second binary signal.Selected binary system candidate value is provided in the input of register.Encoded signal is generated by the way that the Gray code of the selected binary system candidate value of determination is equivalent.
Description
Technical field
The utility model relates generally to binary system to Gray's conversion circuit and relevant FIFO memory and integrated electricity
Road.
Background technique
Promote with the possible way of the data exchange in the system between the component of different frequency timing to include such as example
First in, first out described in European patent document EP2362318A1 (FIFO) memory.
It can may belong to list via such FIFO memory is accessed for the independent logical block of read/write operation
Only clock domain.Specifically, the operation of FIFO memory may include being written in response to the first clock domain and in response to
Two clock domains and be read out.
FIFO memory circuit may include memory block, for example, the register group realized with multiple registers.In addition,
FIFO memory includes: to write interface, is configurable to generate address/storage location of the instruction in the memory block of write operation and writes
Pointer；And interface is read, instruction is configurable to generate for address/storage location read pointer in the memory block of read operation.
Therefore, FIFO memory may be coupled to the first digital circuit and the second digital circuit, and the first digital circuit is configured as to writing
Incoming interface provides data to store data in memory block, and the second digital circuit is configured as access and reads interface with from storage
Read data in area.
In general, the number of storage location is limited.Therefore, writing interface should be able to determine that memory block is less than, and read
It is empty that interface, which should be able to determine memory block not,.For this purpose, usually generating control signal by comparing write pointer and read pointer.
In this respect, signal conformance can be promoted by using synchronous circuit associated with FIFO, this synchronizes electricity
Road is configured as providing synchronization between write pointer and read pointer.In addition, usually write pointer and read pointer are not as binary value
Exchange, but write pointer and read pointer are converted to Gray code from binary coding.Gray code is well known in the present art.Example
It such as, can be with reference to the U.S. Patent Application Publication No. 2008/ for constructing the Gray code of the position with given number
0013386A1, it is incorporated herein by reference for this purpose.
Therefore, this Gray code operation for synchronizing the binary coding write pointer being related in such as the first clock domain (is write
Clock signal) and second clock domain in Gray code operation (read clock signal) to obtain binary coding again write finger
Needle.Similar operation can also be executed to read pointer.
Specifically, this Gray code ensures that only single position changes in write pointer and read pointer increase.In fact, passing
In the FIFO memory of system, the write-in of each clock cycle or single storage location is read, for example, respectively responsive to by first or the
What two digital circuits provided writes or reads enable signal.For example, in this scenario, write pointer is write the clock cycle and can only be increased each
One, only change single position so as to cause the write pointer of Gray code, i.e., the Hamming distance between two continuous write pointers is most
It is 1, to reduce the failure being likely to occur in transmission process.
However, burst mode (burst mode) can also be supported by writing interface and/or reading interface, wherein can be when single
Multiple storage locations are written or read in the clock period, to write finger by the number for being likely larger than one storage location to increase
Needle or read pointer.However, this jump of binary-coded write pointer may lead to mistake during synchronization, so long as
Increment will lead to the variation of the write pointer of Gray code relative to the preceding value of the Hamming distance greater than 1.Read pointer is also deposited
In similar problem.
Utility model content
According to one embodiment, a kind of binary system is provided to Gray's conversion circuit characterized by comprising input, quilt
It is configured to receive the first binary signal；Register is configured as the second binary signal of storage；Prediction circuit is configured as
The second binary signal is received, and one group of binary system candidate value is provided, wherein the corresponding Gray of each binary system candidate value
It is equivalent with the second binary signal Gray it is equivalent have 1 Hamming distance；Moderator is configured as being believed according to the first binary system
Number and the second binary signal, select binary system candidate value in a binary system candidate value, wherein selected binary system wait
Choosing value is provided to register；And coder block, it is configured as receiving selected binary system candidate value, and selected by output
Binary system candidate value Gray code it is equivalent.
According to one embodiment, which is characterized in that the first binary signal, the second binary signal and selected two into
The Gray code of candidate value processed is equivalent respectively with the position of given number k, and prediction circuit is configured to supply given number k
Binary system candidate value.
According to one embodiment, which is characterized in that prediction circuit includes k sub-circuit, and each sub-circuit is configured as
I-th of binary system candidate value is provided at output, wherein i=1...k.
According to one embodiment, which is characterized in that prediction circuit includes the first circuit, and the first circuit is configured as reception the
Two binary signals, and the first signal is provided by the difference between computational item 2k-1 and the value of the second binary signal.
According to one embodiment, which is characterized in that sub-circuit respectively includes: input, is configured as receiving the second binary system
Signal；Second circuit is configured as generating second signal by selecting k-i most significant bit of the second binary signal；
Tertiary circuit is configured as generating third signal by selecting i least significant bit of the first signal；With the 4th circuit, quilt
It is configured to generate corresponding binary system candidate value by combination second signal and third signal.
According to one embodiment, which is characterized in that prediction circuit includes the first circuit, and the first circuit is configured as reception the
Two binary signals, and the first signal is provided by the position of the second binary signal of reversion.
According to one embodiment, which is characterized in that sub-circuit respectively includes: input, is configured as receiving the second binary system
Signal；Second circuit is configured as generating second signal by selecting k-i most significant bit of the second binary signal；
Tertiary circuit is configured as generating third signal by selecting i least significant bit of the first signal；With the 4th circuit, quilt
It is configured to generate corresponding binary system candidate value by combination second signal and third signal.
According to one embodiment, which is characterized in that moderator is associated with pretreatment circuit, and pretreatment circuit is configured as
Select one group of binary system candidate value, binary system between the value of the second binary signal and the value of the first binary signal waits
Choosing value, the value of the second binary signal indicates lower limit, and the value of the first binary signal indicates the upper limit or target value.
According to one embodiment, which is characterized in that for each binary system candidate value, it includes corresponding super for pre-processing circuit
Range circuit, each over range circuit are configurable to generate corresponding shielded signal, corresponding shielded signal instruction corresponding two
Whether system candidate value is between the upper limit and lower limit.
According to one embodiment, which is characterized in that moderator be configured as ignoring with corresponding shielded signal two into
Candidate value processed, corresponding shielded signal indicate corresponding binary system candidate value not between lower limit and the upper limit.
According to one embodiment, which is characterized in that moderator be configured as ignoring with away from the second binary signal away from
From the binary system candidate value for being greater than given maximum distance.
According to one embodiment, which is characterized in that moderator is configured as the binary system candidate value that selection has maximum value.
According to one embodiment, which is characterized in that moderator is realized using combinational logic circuit.
According to one embodiment characterized by comprising memory block, including multiple storage locations；Interface is write, is configured
To generate binary system write pointer, binary system write pointer indicates the storage location for writing data into memory block；Interface is read, is matched
It is set to and generates binary system read pointer, the instruction of binary system read pointer is for reading the storage location of data from memory block；Synchronous circuit,
It is configured as writing interface and reading to exchange binary system write pointer or binary system read pointer between interface, wherein synchronous circuit is matched
It is set to exchange Gray encoded signal；With binary system to Gray's conversion circuit, be configured as receive binary system write pointer or two into
Read pointer processed is provided to together wherein the Gray code of the binary system candidate value determined by binary system to Gray's conversion circuit is equivalent
Step circuit.
According to one embodiment, which is characterized in that binary system to Gray's conversion circuit includes: register, is configured as depositing
Store up the second binary signal；Prediction circuit is configured as receiving the second binary signal, and it is candidate to provide one group of binary system
Value, wherein the equivalent Gray with the second binary signal of the corresponding Gray of each binary system candidate value it is equivalent have 1 Hamming
Distance；Moderator is configured as selecting one in binary system candidate value according to the first binary signal and the second binary signal
A binary system candidate value, wherein the first binary signal is binary system write pointer or binary system read pointer, and wherein selected
The binary system candidate value selected is provided to register；And coder block, it is configured as receiving selected binary system candidate value, and
And the Gray code of the selected binary system candidate value of output is equivalent.
The utility model ensures the signal conformance during synchronizing.Moreover, compared with known solution, Ke Yijie
It saves area and realizes more compact.Specifically, various embodiments are based on the formula that can also directly determine binary system pointer candidate,
It can be utilized in simple, improved hardware realization.Therefore, various embodiments can by reduce component number come
Reduced circuit area is presented to occupy, while solving the problems, such as previously discussed various.
Detailed description of the invention
One or more embodiments are only described by way of non-limiting example with reference to the drawings, in which:
Fig. 1 shows the exemplary architecture of FIFO memory；
Fig. 2 shows the exemplary control circuits suitable for generating write pointer or read pointer in the FIFO memory of Fig. 1；
Fig. 3 shows the exemplary circuit for generating Gray code write pointer or read pointer；
Fig. 4 shows the timing diagram of the operation of the circuit of Fig. 3；
Fig. 5 shows another circuit for generating Gray code write pointer or read pointer；
Fig. 6 shows the timing diagram of the operation of the circuit of Fig. 5；
Fig. 7 shows the embodiment of the circuit for generating Gray code write pointer or read pointer；With
Fig. 8,9,10 and 11 show the details of operation of the circuit of Fig. 7.
Specific embodiment
In the following description, various details are provided to provide the thorough understanding to various exemplary embodiments.It can be with
Embodiment is practiced in the case where none or multiple specific details or using other methods, component, material etc..At it
In the case of him, well known structure, material and operation is not shown or described in detail to avoid the various aspects of fuzzy embodiment.
The reference of " one embodiment " or " embodiment " is meaned in this specification to combine the specific of embodiment description
Feature, structure or characteristic are included at least one embodiment.Therefore, the phrase occurred through this specification in each place
" in one embodiment " or " in embodiment " it is not necessarily all referring to identical embodiment.In addition, special characteristic, structure or spy
Property can combine in any suitable manner in one or more embodiments.
Therefore title provided herein does not explain protection Chengdu or the range of embodiment only for convenient.
As previously mentioned, the metastability of signal is in the system of such as system on chip (SoC) for including multiple clock domains
Existing general considerations when crossing clock domain, for example, when data from the first digital circuit with the first clock operation be transferred to
Different from the first clock second clock operation the second digital circuit when.Different clock signals can have different frequencies
Rate, for example, such as in asynchronous system or they can have identical frequency but have incoherent relative phase difference,
Such as in synchronization system.
For example, this is suitable for previously described write and read pointer.In order to which signal is transferred to another from the first clock domain
Clock domain, the prior art include that signal is made to pass through synchronous chain, such as the cascade D flip-flop controlled by second clock signal.
When the input signal of synchronous chain changes during foundation/retention time of trigger, naturally-occurring metastability.
Reducing the conventional method of mistake possibility as caused by metastable state is Gray code.When signal passes through clock domain,
Gray code can prevent from capturing invalid transient state (" burr (glitches) ").Non-deterministically each position of signal is adopted
Sample, to be transmitted for the clock domain.Therefore, for each position, old value or new value are propagated.Therefore, if it is more in multibit signal
Yu Yiwei changes at sampled point, then can propagate " burr " binary value (neither new being also not is old).Pass through guarantee
Only one position can change, i.e., the single Hamming distance between guarantee follow-up signal value, Gray code make only possible sampling
Value is new or old multiple bit value.Gray code with strength synchronize help to decrease or even eliminate any burr because any post
The output of storage all keeps stable.
Above-mentioned stationary problem will be described again in the example of FIFO memory now.
Specifically, Fig. 1 shows the exemplary architecture of FIFO memory 50, and FIFO memory 50 is coupled to the first clock
The first digital circuit (writing logical block) 10 of signal Clock1 operation and the second number operated with second clock signal Clock2
Circuit (reading logical block) 40.
Specifically, FIFO memory 50 includes: memory block 30, including multiple storage locations, for example, utilizing register reality
It is existing；And control circuit 20, it is configured as management write pointer and read pointer, to write visit for the storage location to memory 30
It asks and read access.
For example, writing logical block 10 can write data into via the write pointer at the frequency of clock signal Clock1 by controlling
One or more storage locations that circuit 20 currently selects, and reading logical block 40 can be via read pointer with clock signal
The frequency of Clock2 reads data from the one or more storage units currently selected by control circuit 20.
In various embodiments, control circuit 20 can be configured as to write pointer using binary coding, and read to refer to
Needle is for selecting to write storage location accordingly and reading storage location, for example, binary sequence " 100 " corresponds to decimal number 4.
In various embodiments, control circuit 20, which can be configured as, generates full signal and sky according to write pointer and read pointer
Signal.
For this purpose, control circuit 20 can be configured as through strength synchronizer (for example, register chain) come synchronous write
Pointer and/or read pointer.
It can promote consistency of the signal when passing through clock domain via the construction of control circuit 20 associated with FIFO,
The control circuit 20 is configured to supply the synchronization of Gray code pointer.When address bus counts upward or downward, Ge Leibian
Code ensures only one change.Therefore, the clock cycle is write each, write pointer can only be increased by one, otherwise be compiled using Gray
The advantages of code, may become unimportant.
For example, Fig. 2 shows the possibility embodiments of control circuit 20.
In the embodiment considered, control circuit 20 includes to be grasped by writing the clock rate C lock1 that logical block 10 provides
The the first sub-circuit 20a made and the second sub-circuit 20b operated with the second clock frequency Clock2 provided by reading logical block 40.
As previously mentioned, control circuit 20 is configurable to generate write pointer and read pointer.
In the embodiment considered, control circuit 20 includes accumulator, and accumulator includes binary adder 202 and posts
Storage 201.Specifically, content and signal 200 of the adder 202 in input receiving register 201.Therefore, adder 202 exists
It is provided at output and corresponds to the content of register 201 and the signal of the sum of signal 200, register 201 is written again.It is being examined
In the embodiment of worry, therefore the signal at the output of adder 202 can correspond to binary coding WPBWrite pointer.
For example, signal 200 can correspond to write enable signal when using traditional FIFO memory, thus make when writing
Write pointer WP when energy signal is arranged to highBIt is incremented by the 1 and write pointer WP when write enable signal is set as lowBIt keeps constant.Tool
Body, adder 202 and register 201 form a part using the clock signal Clock1 sub-circuit 20a operated.
On the contrary, signal 200 can correspond to will be when single when realizing the FIFO memory for supporting burst write mode
The number for the storage location being written in the clock period.
Similarly, sub-circuit 20b may include the accumulator realized using binary adder 222 and register 221,
Middle adder provides the reading having corresponding to the content of register 221 and the binary coding RPB of the sum of signal 200 at output
Pointer can correspond to read enable signal or indicate the multiple storage locations to be read.Specifically, adder 222 and deposit
Device 221 is formed with a part of the clock signal Clock2 sub-circuit 20b operated.
In various embodiments, control circuit 20 can also include: the first circuit 232, be configured to determine that FIFO believes entirely
Numbers 234；And/or second circuit 212, it is configured to determine that fifo empty signal 214.
In general, circuit 232 is configured as by being compared to write pointer and read pointer to generate FIFO full signal 234.
Similarly, circuit 212 is configured as by being compared to write pointer and read pointer to generate fifo empty signal 214.
Therefore, in the embodiment considered, control circuit 20 includes the electricity for write pointer to be transmitted to clock domain 20b
Road, and/or the circuit for read pointer to be transmitted to clock domain 20a.
Specifically, in various embodiments, which transmits the Gray code version of write pointer and read pointer respectively.
Specifically, the binary system write pointer WP in the embodiment considered, at the output of adder 202BIt is provided to
For binary system to Gray's conversion circuit 204, what therefore binary system to Gray's conversion circuit 204 provided Gray code at output writes finger
Needle WPG。
In the embodiment considered, the output of binary system to Gray's conversion circuit 204 is (that is, signal WPG) be provided to
Synchronous circuit 211.
For example, in one or more embodiments, synchronous circuit 211 includes multiple registers 206,208 and 210.One
In a or multiple embodiments, at least one register (for example, register 206) can be driven and extremely by clock signal Clock1
A few register (for example, register 208 and 210) can be driven by clock signal Clock2.The register of synchronous circuit 211
It may be collectively referred to as strength synchronizer (BFS).Therefore the last one register 210 of synchronous circuit 210 provides Gray at output
The write pointer WP' of codingGDelay version.
It similarly, can be by the binary system read pointer RP at the output of adder 222BBinary system is supplied to Gray's conversion
Therefore circuit 224, binary system to Gray's conversion circuit 224 provide Gray code read pointer RP at outputG.Gray code reading refers to
Needle RPGIt can be provided to synchronous circuit 231, therefore synchronous circuit 231 provides Gray code read pointer RP'GOutput postpone version
This.Also in this case, synchronous circuit 231 can use multiple registers 226,228 and 230 and realize, and wherein at least one
A register (for example, register 226) can be driven by clock signal Clock2 and at least one register is (for example, deposit
It device 228 and 230) can be driven by clock signal Clock1.
Therefore, in various embodiments, the first circuit 232 can determine FIFO full signal 234, for example, by that will postpone
Gray code read pointer RP'GConvert back binary coding and by corresponding binary system pointer and binary coding write pointer WPB
It is compared, or by the Gray code read pointer RP' of delayGWith Gray code write pointer WPGIt is compared.
Similarly, second circuit 212 can determine fifo empty signal 214, for example, by the way that finger is write in the Gray code of delay
Needle WP'GConvert back binary coding and by corresponding binary system pointer and binary coding read pointer RPBIt is compared, or will
The Gray code read pointer RP of delayGWith Gray code write pointer WP'GIt is compared.
Therefore, in general, circuit 212 and/or circuit 232 may include Gray to binary decoder.Specifically, it is being examined
In the embodiment of worry, control circuit 20 controls write pointer increment by sub-circuit 205, and sub-circuit 205 includes being coupled to signal 200
Input node, register 201, adder 202 and binary system to Gray's conversion circuit 204.Similarly, control circuit 20 controls
Read pointer increment in sub-circuit 225, sub-circuit 225 include input node, the register 221, adder for being coupled to signal 220
222 and binary system to Gray's conversion circuit 224. in various embodiments, sub-circuit 205 and sub-circuit 225 can have identical
Circuit structure.
In this respect, U.S. Patent number 9,311,975 solution party provided for realizing sub-circuit 205 and/or 225
Case.Specifically, this document describe a solution, and wherein FIFO memory 50 can be configured as permission and refer in read/write
The discontinuous of new storage location is directed toward in needle to jump.For example, write pointer can be from the data burst for writing logical block 10
As a result.Substantially, it this document propose a kind of FIFO memory 50, is configured as being directed to and writes finger from current storage location
Needle and/or read pointer determine that multiple addresses jump candidate (it can be alternatively referred to as jumping candidate or candidate).Next, FIFO
Memory 50, which can be configured as to jump in candidate from multiple addresses, selects address to jump candidate.
The embodiment of the sub-circuit 205 of the control circuit 20 of no specific data burst design is shown in Fig. 3, with explanation
Following concept: the distance between two continuous Gray's encoding indicators are not guaranteed using the Gray code enabled with data burst
(clock cycle) keeps the single Hamming distance with its preceding value.
In this exemplary embodiment, binary adder 201 includes the addition for being coupled to signal 200 and register 201
Device.Specifically, content and signal 200 of the adder 202 in input receiving register 201.Therefore, adder 202 is exporting
Place provides the signal of the content and the sum of signal 200 that correspond to register, which is written register 201 again.Considered
Embodiment in, therefore signal at the output of adder 202 can correspond to binary coding WPBWrite pointer.For
With binary coding RPBRead pointer be also such.It therefore, will be hereinafter general by the value that the summation of the two values generates
Ground is expressed as object pointer/signal PTR_target.
In the embodiment considered, object pointer PTR_target is then supplied to binary system to Gray's conversion circuit
204.In the embodiment considered, therefore the signal at the output of the output of binary system to Gray's conversion circuit 204 corresponds to
The Gray code of input value PTR_target is equivalent and will be expressed as signal PTR_gray below.
Fig. 4 shows the time diagram of the content of the aforementioned signal in the exemplary embodiment according to Fig. 3.
For example, being designated as T0Clock cycle, the value of signal PTR_target is PTR_target (T0)=(4)10,
In 10 indicate pointer values decimal representation.For example, decimal value 4 corresponds to bit sequence " 0100 " in binary coding.Letter
The value of number PTR_gray is in clock cycle T0The Gray code of the value of period signal PTR_target is equivalent, such as by using
Bit sequence including four positions, signal PTR_gray can be " 0110 "=(4)10。
In the example considered, during the identical clock cycle, the value WE of signal 200 is for example.WE(T0)=
(9)10.Therefore, in the subsequent clock cycle, it is expressed as T1, the value PTR_target that is stored in register 401 changes and uses
T0The value of the sum of the signal PTR_target and WE at place update, such as.PTR_target(T1)=PTR_target (T0)+WE
(T0)=(13)10.Therefore, when using the circuit of Fig. 3, T1The equivalent Gray of the PTR_target at place will be such as PTR_gray
(T1)=" 1011 "=(13)10, the Hamming distance apart from preceding value is greater than 1.Therefore, in subsequent synchronization chain, with PTR_
The Hamming distance of the successive value of gray signal is greater than 1, leads to possible mistake, because must transmit on clock domain more than one
Variation.
The exemplary implementation for meeting the sub-circuit 205 of control circuit 20 of U.S. Patent number 9,311,975 is shown in Fig. 5
Example.
In this exemplary embodiment, binary adder 201 again by be coupled to signal 200 and register 201 plus
Musical instruments used in a Buddhist or Taoist mass composition.Specifically, content and signal 200 of the adder 202 in input receiving register 201.Adder 202 is exporting
Place provides the signal PTR_target of the content and the sum of signal 200 that correspond to register 201, and the signal is in next clock week
Register 201 is written in phase again.
As a result PTR_target is passed to the circuit 204 for executing binary system to Gray's conversion 204.However, the circuit 204
Do not realize that straight binary system to Gray's converter 204, but executes more complicated conversion.For this purpose, by signal PTR_
Target is supplied to binary system to Gray's conversion circuit 240a.Circuit 240a includes the input for receiving binary coded signal
Node, such as signal PTR_target, and the output node of Gray encoded signal PTR_gray is provided.As described below, it is giving
In the fixed clock cycle, Gray code output signal PTR_gray not necessarily corresponds to binary coding input signal PTR_
The gray coded value of target.Therefore, in various embodiments, input node may be coupled to the output of adder circuit 202.
In the embodiment considered, binary system to Gray's conversion circuit 240a further includes another input node, is matched
It is set to and receives Gray code output signal PTR_gray, to realize the feedback control loop of output signal PTR_gray.
Specifically, according to U.S. Patent number 9,311,975, binary system to Gray's conversion circuit 240a generate have with it is current
All Gray's value/candidates of the single Hamming distance of signal PTR_gray.Next, circuit 240a determines these Gray's value/times
The binary equivalent of choosing simultaneously selects Gray's value, and binary equivalent is closest to signal PTR_target.These operations repeat one
Or multiple clock cycle, until the binary equivalent of output signal PTR_gray reaches the value of signal PTR_target.The result is that
The sequence of gray coded value PTR_gray, wherein last value PTR_gray corresponds to the Gray of binary signal PTR_target
It is equivalent.
Fig. 6 shows the time diagram of the transmission of the data in the embodiment according to Fig. 5.
For example, being designated as T0Clock cycle, the value of PTR_target signal is PTR_target (T again0)=
(4)10.The value of signal PTR_gray is in T0The Gray code of the value of PTR_target signal is equivalent during clock cycle, for example,
PTR_gray=" 0110 "=(4)10.During the same clock cycle, the value WE of signal 200 is WE (T again0)=(9)10。
T is expressed as in subsequent1Clock cycle, be stored in the signal PTR_target in register 201 value change
And use T0The value of the PTR_target and the sum of WE at place update, for example, PTR_target (T1)=PTR_target (T0)+WE
(T0)=(13)10。
Therefore it provides changing to the value of the signal PTR_target of binary system to Gray's conversion circuit 240a and being now
(13)10。
Specifically, in the embodiment considered, binary system to Gray's conversion circuit 240a is from current demand signal PTR_gray
Generate Gray's value/candidate that Hamming distance is 1, such as signal " 1110 ", " 0010 ", " 0100 ", " 0111 " show for what is considered
Example.In addition, binary system determines these Gray's value/candidate binary equivalents to Gray's conversion circuit 240a, such as " 1110 "=
(11)10, " 0010 "=(3)10, " 0100 "=(7)10, " 0111 "=(5)10For the example considered.Next, binary system is to lattice
Thunder conversion circuit 240a selects Gray's value, binary equivalent and signal PTR_target have the smallest positive distance (that is, two into
Make it is equivalent, closest to and be less than signal PTR_target), i.e. " 1110 "=(11)10For the example considered.Therefore, exist
In the example considered, circuit 240a provides PTR_gray (T at output now1)=" 1110 "=(11)10。
These operations repeat one or more clock cycle, until the binary equivalent of output signal PTR_gray reaches letter
The value of number PTR_target.The result is that (" 1110 "=(11) Gray code value sequence PTR_gray10, " 1010 "=(12)10、
" 1011 "=(13)10) wherein last value PTR_gray correspond to binary Gray's equivalent signal PTR_target.
Therefore, which ensure that the consistency of the signal in subsequent synchronisation chain really.
However, inventor has been observed that the solution is slowly (to execute for example, being formed for each candidate value
Gray to binary decoded operate) and with regard to the area of component occupancy for be expensive.
One or more embodiments of the sub-circuit 205 of the control circuit 20 according to this specification are shown in FIG. 7.Example
Such as, which can also be used in the FIFO memory for supporting data burst mode.Specifically, which also ensures that sub-circuit
Hamming distance between two continuous Gray's value PTR_gray at 205 output keeps single.
Equally in this exemplary embodiment, binary adder 202 includes being coupled to signal 200 and register 201
Adder, as previously described.Signal PTR_target at the output of adder 202, which is passed to, executes binary system to Gray's conversion
204 circuit.Specifically, in the embodiment considered, circuit 204 includes binary system to Gray conversion circuit 240b,
Input receives binary coded signal PTR_target and provides Gray encoded signal sequence PTR_gray in output end, wherein
The Gray that last gray coded value corresponds again to signal PTR_target is equivalent.
Fig. 8 shows the exemplary hardware embodiment of the sub-circuit 205 of control circuit 20.
In one or more embodiments, circuit 240b includes the input section for receiving binary signal PTR_target
It puts and for providing the output node of signal PTR_gray.
In the embodiment considered, circuit 240b further includes register 61.Specifically, in the embodiment considered,
Register 61 is configured as the binary equivalent PTRf of storage signal PTR_gray.
Specifically, in the embodiment considered, the output signal PTRf of register 61 is provided to prediction circuit 62.Tool
Body, prediction circuit 62 is configured as receiving signal PTRf in input and provides one group of binary system candidate value 63a- at output
63c, wherein the equivalent Hamming distance equivalent with the Gray of signal PTRf of the corresponding Gray of each binary system candidate value is 1.Example
Such as, it is assumed that value PTRf has binary value (4)10(corresponding to Gray's value " 0110 "), prediction circuit 62 can provide at output
Binary value (11)10(corresponding to Gray's value " 1110 "), (3)10(corresponding to Gray's value " 0010 "), (7) 10 (correspond to Gray
It is worth " 0100 "), and (5) 10 (corresponding to Gray's value " 0111 ").
In various embodiments, number of the number of binary system candidate value corresponding to the position of signal PTRf.
In general, the possible binary system candidate value 63a-63c of each value of signal PTRf can be precalculated.Therefore, in advance
Slowdown monitoring circuit 62 can realize that each value that the look-up table has been signal PTRf stores corresponding binary system and waits with look-up table
Select value set, wherein the corresponding Gray of each binary system candidate value it is equivalent with the Gray of corresponding signal PTRf is equivalent has 1
Hamming distance.
On the contrary, Fig. 8 shows one embodiment, wherein prediction circuit 62 includes multiple prediction circuit 62a-62c.Prediction electricity
Number of the number of road 62a-62c corresponding to the position of signal PTRf, wherein each prediction circuit 62a-62c provides phase at output
The binary system candidate value 63a-63c answered.
Specifically, in various embodiments, prediction circuit 62a-62c is realized with combinational logic circuit, combinational logic electricity
Road is configured as calculating corresponding binary system candidate value in real time, as described below.
In one or more embodiments, binary system candidate value 63a-64c is provided to moderator 66, and moderator 66 is matched
One be set in selection binary system candidate value 63a-63c.Therefore signal at the output of moderator 66 corresponds to next two
Binary signal PTRf, and therefore register 61 is fed in input.In addition, the signal at the output of moderator 66 is provided to
Binary system is to Gray encoder block.Specifically, in various embodiments, coder block 68 is combinational logic circuit, is being exported
Place's offer is equivalent in the Gray code of input received signal PTRf.
For example, moderator can be associated with pre- in order to select " best " binary system candidate value for Setting signal PTR_target
Processing circuit 64.For example, in various embodiments, pretreatment circuit 64 is configured as only selecting binary system candidate value 63a-63c
The binary system between the current value for indicating the signal PTRf of lower limit and the signal PTR_target for indicating the upper limit or target value
Candidate value.
For example, each binary system candidate value 63a-63c can be provided to corresponding super model in the embodiment considered
Block 64a-64c is enclosed, each over range block 64a-64c is configurable to generate corresponding shielded signal 65a-65c, corresponding shielding letter
Number 65a-65c indicates corresponding binary system candidate value between lower and upper limit.
Therefore, in the embodiment considered, moderator 66 can only consider there is instruction binary system candidate value 63a-63c
The binary system candidate value 63a-63c of corresponding shielded signal between lower and upper limit, i.e., off-limits candidate value 63a-63c
It is not taken into account.
In various embodiments, pretreatment 64/ over range block 64a-64c of circuit can also be limited (in addition to lower and upper limit
Except) to the selection with the binary system candidate value 63a-63c of the maximum distance of the current value of signal PTRf.For example, this is most
Big distance can be programmable, maximum allowable jump value to allow to be arranged.
Therefore, once by shielded signal 65a-65c (for example, when select corresponding binary system candidate value 63a-63c and
Corresponding shielded signal can be set when between the limitation of permission) subset of binary system candidate value 63a-63c is received, such as scheme
Shown, moderator 66 can choose one in the value of the subset of binary system candidate value 63a-63c.
For example, moderator 66 can choose the maximum value of the subset of binary system candidate value 63a-63c.For example, prediction circuit
62 sequences that can be incremented by (or alternatively successively decreasing) at output provide the sequence of binary system candidate value 63a-63c.Therefore,
Moderator 66 can choose the value of the subset of binary system candidate value 63a-63c, and the subset of binary system candidate value 63a-63c is tool
There is last (or alternatively first) for indicating shielded signal of the corresponding binary system candidate value 63a-63c between allowing to limit
Value.
In various embodiments, moderator 66 can be realized with combinational logic circuit, to select within the single clock cycle
Select binary system candidate value.
It will be described below the possibility implementation of prediction circuit 62 now.
In general, any binary coded value V can be indicated by the position k of given number.
By using Gray code, corresponding gray coded value V to such binary coded value VGGenerally also there is k
Position.Since candidate value should have and gray coded value VGFor 1 Hamming distance the fact, there are the possible Grays of k to compile
Code candidate value, wherein i-th of Gray code candidate has gray coded value VGInverted i-th.
Instead of executing these operations to gray coded value, the various embodiments of the disclosure are directly operated with binary value, with
Just estimate k binary coding candidate value C1...Ck。
Specifically, in various embodiments, i-th of (there is i=1...k) binary system can be calculated by solving equation
Encode candidate value:
Wherein operation " mod " corresponds to modular arithmetic, and operates " floor " and receive real number in input and mention at output
For being less than or equal to the maximum integer of input number.
Above-mentioned equation can be empirically determined, and substantially be generated by the attribute of Gray code, can pass through " mirror image "
The code of first anteposition (is used to construct Gray's code see, for example, 2008/0013386 A1 of U.S. Patent Application Publication to generate
Description).
Show how prediction circuit 62 according to equation (1) calculates the exemplary of each binary system candidate value in real time in Fig. 9
Concept map.
Specifically, in the example considered, 621 value V is expressed as in Fig. 9 to be had corresponding to decimal number V=17
Value.In the example considered, for indicating that the number of position of the decimal number V in binary coding is such as k=5.
In this example, the value that signal V then can be handled in the combinational logic of prediction circuit 62, to provide basis
One group of k=5 binary system candidate value 622-626 that equation (1) calculates.Specifically, in various embodiments, prediction circuit 62 is true
It is calmly multiple to jump candidate 622-626, i-th of candidate binary system etc. for indicating decimal number V in the i-th bit of every k position
Effect.
In the operation example considered, ten are corresponded respectively to using the binary system candidate value 622-626 that equation (1) calculates
Hex value 16,18,22,30,14.
In one or more exemplary embodiments, a class value C can be obtained by combinational logic circuit1...Ck。
Figure 10 shows the exemplary hardware embodiment 62i of i-th of prediction circuit 62a-62c, therefore provides at output
I-th of binary system candidate value 63i.
Therefore, in this exemplary embodiment, circuit 62i receives the signal PTRf value from register 61 in input,
And i-th of binary system candidate value 63i is provided at output, wherein the Gray of i-th of binary system candidate value is equivalent to be had away from signal
The Gray of PTRf is equivalent to 1 Hamming distance.
Specifically, circuit 62i realizes equation (1) for given i.
Specifically, inventor has been observed that term " floor (V/2i) " can be realized by moving to right bit manipulation.Phase
Instead, it can use shift left operation to realize and 2iMultiplication.
This is also shown in FIG. 10, and wherein circuit 62i includes right logical shift 621 and left logical shift 622.Specifically,
In the exemplary embodiment considered, right logical shift block 621 receives the signal PTRf from pointer blocks 61 simultaneously in input
And the value of the floor function of the ratio between i-th side of V and 2 is calculated for given value i.The output of right logical shift block 621 is provided
To left logical shift block 622, therefore left logical shift block 622 calculates the floor function of the ratio between 2 i power and the i power of V and 2
Product.
In general, can be operated in the value i of given circuit 62i fixed range with hardwired shift.For example, replacing clear
Realize dextroposition and move to left to operate that circuit 621 and 622 can combine in circuit 627, and circuit 627 is configured as simply in ground
The i least significant bit (LSB) of signal PTRf is set " 0 " by ground, to substantially only keep (k-i) highest of signal PTRf
Significance bit (MSB).
In the embodiment considered, circuit 62i further includes binary subtracter circuit 623, is configured as calculating
The item (2 of output valve 620 is expressed as in figurek- 1) wherein k is number for indicating the position of V to the difference-between the value of V again.
For example, binary subtracter circuit 623 can be realized with binary adding circuit in hardware realization.Specifically,
The binary subtraction of two items A and B can be realized at level of hardware using the binary addition of wherein (A+NOT (B)+1).Cause
This, binary adder 623 can receive signal PTRf in input and provide (2k+NOT (PTRf)) at output
Binary addition as a result, wherein logical operation NOT corresponds to each of signal PTRf logic inversions and terms 2kIt can
To precalculate and be fixed at level of hardware.
However, having item 2kBinary addition do not change really operation as a result, therefore, circuit 623 can export
Place simply provides NOT (PTRf).
In general, circuit 623 does not consider parameter i, thus circuit 623 can be to all prediction circuit 62a-62c it is public,
That is, circuit 623 can be not present in circuit 62i, because all identical for all prediction circuit values 620.
The output valve 620 of circuit 623 can be used as input and be transmitted to the circuit 624 for being configured as calculating modular arithmetic.
For example, in various embodiments, circuit 624 is realized with least significant bit (LSB) limiter, it is configured as only tieing up
The i least significant bit (LSB) of signal 620 is held, i.e. (k-i) each most significant bit (MSB) of signal 620 is arranged to " 0 ".
In the embodiment considered, the signal provided by circuit 621/622 and 624 is then supplied to binary addition
Device 625, to generate the value of i-th of binary system candidate value 63i.
Specifically, circuit 627 provides the signal with the i least significant bit for being set as " 0 ", and circuit 624 provides tool
There is the signal of (k-i) most significant bit (MSB) for being set as " 0 ".Therefore, adder circuit 625 can also be by selecting by electricity
(k-i) most significant bit (MSB) for the signal that road 627 provides, and select the least significant bit of the signal provided by circuit 624 Lai
Simply generate signal.
Figure 11 show realized in the case where i is considered the hardwired constant of i-th of example equation (1) the
The example hardware of i prediction circuit 62a-62c realizes the embodiment of 62i.
In this exemplary embodiment, it is similar to content described in earlier paragraphs, circuit 62i is received in input and come from
The signal PTRf value of register 61, and i-th of binary system candidate value 63i is provided at output, wherein i-th of binary system candidate value
Gray's equivalence value have the Gray away from signal PTRf be equivalent to 1 Hamming distance.
Shift circuit 627 receives the position k of PTRf signal, and the output of circuit 627 is fed as input to binary addition
Device 625.Specifically, circuit 627 only propagates (k-i) most significant bit (MSB).Signal PTRf may be minimum by the i of signal PTRf
Significance bit (LSB) is set as " 0 ".For example, in the case where k=5 and i=4, shift circuit 627 can be provided at output by
The signal of the single position composition of MSB value with PTRf.
Circuit 623 can be realized with phase inverter (or logic door), received PTRf signal in input and mentioned at output
For signal 620, the position of signal 620 is arranged to opposite logic level relative to input bit.
Again, the output valve 620 of circuit 623 can be used as input and be transmitted to the circuit 624 for being configured as calculating modular arithmetic.
For example, in various embodiments, circuit 624 receives the position k of signal 620, and the position i at the output of circuit 624 is mentioned as input
Supply binary adder 625.
Specifically, the i least significant bit (LSB) of the only transmitting signal 620 of circuit 624, and (k-i) of signal 620 is most
High significance bit (MSB) is possibly set to " 0 ".For example, circuit 624 can be mentioned in output end in the case where k=5 and i=4
For 4 signals formed of the value by last four significance bits with PTRf.
In the embodiment considered, the signal provided by circuit 627 and 624 is supplied to circuit 625 again, passes through group
Close signal from circuit 624 and 627 and generate the position k for indicating the value of i-th of binary system candidate value 63i, for example, by using by
(k-i) most significant bit that circuit 627 provides and the i-th least significant bit (LSB) provided by circuit 624.
Therefore, realized using circuit shown in Figure 11 the operation of circuit shown in Figure 10 will provide correspond to two into
I-th any of binary system candidate value 63i in candidate value 63a-63c processed.
Therefore, by using circuit shown in Figure 10 in the prediction circuit 62 of Fig. 8, prediction circuit 62 will be in output k
Place provides binary system candidate value, and one that moderator 66 will select in k binary system candidate value 63a-63c.As previously described.
Therefore, moderator provides binary value at output, which is fed to register 61 and binary system to Gray code
Device 68.
For example, as described in Fig. 7, signal PTR_target be can correspond in the context of FIFO memory
Binary value write pointer or read pointer.Therefore, in this case, circuit 240b provides gray coded value PTR_ at output
The sequence (Hamming distance between continuous Gray's value is 1) of gray, wherein last Gray's value is corresponding to signal PTR_target's
Gray code version.
Therefore, in the context of FIFO memory as shown in Figure 2, circuit shown in fig. 7 can be with synchronizer knot
It closes and uses, write pointer and/or read pointer are delivered to another clock domain.
Therefore, previously described circuit is special for supporting the FIFO memory of burst mode write operation and/or read operation
It is useful, wherein the multiple storage locations of write-in/reading during a clock cycle.In general, although signal PTR_gray (corresponds to
WPGOr RPG) not necessarily correspond to binary system Writing/Reading pointer WPBOr RPBThe value of (correspond to PTR_target), but this not generation
Table gray coded value sequence is only increased up the problem of reaching corresponding binary system Writing/Reading pointer.For example, even if reading interface
Set is still kept through readout data signal EMPTY or still keeps set even if writing interface and having been written into data-signal FULL, together
When avoid it is synchronous during mistake.
Therefore, similar to traditional FIFO memory with write/read operation, which ensures the letter during synchronizing
Number consistency.Moreover, can save area compared with known solution and realize more compact.Specifically, various implementations
Example, can be sharp in simple, improved hardware realization based on the formula that can also directly determine binary system pointer candidate
With.Therefore, the circuit area that reduction can be presented in various embodiments by reducing the number of component occupies, while solving front
The various problems discussed.
In general, can be also used for wherein must be by the conversion between the binary value of experience " jumping " for circuit previously discussed
It is converted into other arrangements of corresponding gray coded value.For example, the number bus in electronic system can only for transmitting sometimes
The amount increased or decreased, such as the output of counter, then number is transmitted between clock domain or is transmitted in the output of counter
Mode converter.Similarly it is possible to there are problems that being used for transmission sensor signal, wherein signal conformance than data transmit etc.
It is more relevant to the time.Therefore, in general, the solution can also be used in other Transmission systems, wherein using Gray code.
Without departing from basic principle, in the case where not departing from protection scope, about herein only by non-
The content of limitative examples description realizes that details and embodiment can change, it might even be possible to substantially change.
Claims (15)
1. a kind of binary system is to Gray's conversion circuit characterized by comprising
Input is configured as receiving the first binary signal；
Register is configured as the second binary signal of storage；
Prediction circuit, be configured as receive the second binary signal, and provide one group of binary system candidate value, wherein each two into
The equivalent Gray with second binary signal of the corresponding Gray of candidate value processed is equivalent have 1 Hamming distance；
Moderator is configured as selecting the binary system according to first binary signal and second binary signal
A binary system candidate value in candidate value, wherein the selected binary system candidate value is provided to the register；With
Coder block is configured as receiving the selected binary system candidate value, and exports the selected binary system
The Gray code of candidate value is equivalent.
2. circuit according to claim 1, which is characterized in that first binary signal, second binary system letter
Number and the selected binary system candidate value the Gray code it is equivalent respectively with the position of given number k, and it is described
Prediction circuit is configured to supply the binary system candidate value of given number k.
3. circuit according to claim 2, which is characterized in that the prediction circuit includes k sub-circuit, each sub-circuit
It is configured as providing i-th of binary system candidate value at output, wherein i=1...k.
4. circuit according to claim 3, which is characterized in that the prediction circuit includes the first circuit, first electricity
Road is configured as receiving second binary signal, and passes through computational item 2k- 1 with the value of second binary signal it
Between difference the first signal is provided.
5. circuit according to claim 4, which is characterized in that the sub-circuit respectively includes:
Input is configured as receiving the second binary signal；
Second circuit is configured as generating the second letter by selecting k-i most significant bit of second binary signal
Number；
Tertiary circuit is configured as generating third signal by selecting i least significant bit of first signal；With
4th circuit is configured as generating corresponding binary system candidate by combining the second signal and the third signal
Value.
6. circuit according to claim 3, which is characterized in that the prediction circuit includes the first circuit, first electricity
Road is configured as receiving second binary signal, and provides first by the position of reversion second binary signal
Signal.
7. circuit according to claim 6, which is characterized in that the sub-circuit respectively includes:
Input, is configured as receiving second binary signal；
Second circuit is configured as generating the second letter by selecting k-i most significant bit of second binary signal
Number；
Tertiary circuit is configured as generating third signal by selecting i least significant bit of the first signal；With
4th circuit is configured as generating corresponding binary system candidate by combining the second signal and the third signal
Value.
8. circuit according to claim 1, which is characterized in that the moderator is associated with pretreatment circuit, described pre-
Processing circuit is configured as selecting one group of binary system candidate value, value and described first in second binary signal
The value of the binary system candidate value between the value of binary signal, second binary signal indicates lower limit, and described
The value of first binary signal indicates the upper limit or target value.
9. circuit according to claim 8, which is characterized in that for each binary system candidate value, the pretreatment circuit
Including corresponding over range circuit, each over range circuit is configurable to generate corresponding shielded signal, corresponding shielding
Whether the corresponding binary system candidate value of signal designation is between the upper limit and the lower limit.
10. circuit according to claim 9, which is characterized in that the moderator, which is configured as ignoring, has corresponding screen
The binary system candidate value of signal is covered, corresponding shielded signal indicates corresponding binary system candidate value not in the lower limit
Between the upper limit.
11. circuit according to claim 9, which is characterized in that the moderator, which is configured as ignoring, to be had away from described the
The distance of two binary signals is greater than the binary system candidate value of given maximum distance.
12. circuit according to claim 1, which is characterized in that the moderator, which is configured as selection, has maximum value
Binary system candidate value.
13. circuit according to claim 1, which is characterized in that the moderator is realized using combinational logic circuit.
14. a kind of FIFO memory characterized by comprising
Memory block, including multiple storage locations；
Interface is write, is configurable to generate binary system write pointer, the binary system write pointer instruction is for writing data into described deposit
The storage location of storage area；
Interface is read, is configurable to generate binary system read pointer, the binary system read pointer instruction from the memory block for reading
The storage location of data；
Synchronous circuit is configured as exchanging the binary system write pointer or described between interface and the reading interface in described write
Binary system read pointer, wherein the synchronous circuit is configured as exchange Gray encoded signal；With
Binary system is configured as receiving the binary system write pointer or the binary system read pointer to Gray's conversion circuit,
In the Gray code of binary system candidate value that is determined by the binary system to Gray's conversion circuit is equivalent is provided to the synchronization
Circuit.
15. FIFO memory according to claim 14, which is characterized in that the binary system to Gray's conversion circuit packet
It includes:
Register is configured as the second binary signal of storage；
Prediction circuit is configured as receiving second binary signal, and provides one group of binary system candidate value, wherein each
The equivalent Gray with second binary signal of the corresponding Gray of binary system candidate value is equivalent have 1 Hamming distance；
Moderator is configured as selecting the binary system candidate according to the first binary signal and second binary signal
A binary system candidate value in value, wherein first binary signal is the binary system write pointer or the binary system
Read pointer, and wherein the selected binary system candidate value is provided to the register；With
Coder block is configured as receiving the selected binary system candidate value, and exports the selected binary system
The Gray code of candidate value is equivalent.
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| US6337893B1 (en) | 1999-11-04 | 2002-01-08 | Philips Electronics North America Corp. | Non-power-of-two grey-code counter system having binary incrementer with counts distributed with bilateral symmetry |
| US6314154B1 (en) * | 1999-11-04 | 2001-11-06 | Vlsi Technology, Inc | Non-power-of-two Gray-code counter and binary incrementer therefor |
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| EP1879101B1 (en) | 2006-07-11 | 2010-04-07 | STMicroelectronics Srl | A method and system for controlling data synchronization in FIFO memories, and related synchronizer |
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-
2018
- 2018-02-23 IT IT102018000003008A patent/IT201800003008A1/en unknown
-
2019
- 2019-01-24 US US16/256,449 patent/US10635394B2/en active Active
- 2019-02-14 EP EP19157120.7A patent/EP3531560B1/en active Active
- 2019-02-22 CN CN201920225037.2U patent/CN209417720U/en not_active Withdrawn - After Issue
- 2019-02-22 CN CN201910133529.3A patent/CN110187918B/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110187918A (en) * | 2018-02-23 | 2019-08-30 | 意法半导体股份有限公司 | Binary system is to Gray's conversion circuit, relevant FIFO memory, integrated circuit and method |
| CN110187918B (en) * | 2018-02-23 | 2024-03-12 | 意法半导体股份有限公司 | Binary to gray conversion circuit, associated FIFO memory, integrated circuit and method |
Also Published As
| Publication number | Publication date |
|---|---|
| IT201800003008A1 (en) | 2019-08-23 |
| US10635394B2 (en) | 2020-04-28 |
| EP3531560A1 (en) | 2019-08-28 |
| EP3531560B1 (en) | 2020-06-17 |
| US20190265947A1 (en) | 2019-08-29 |
| CN110187918A (en) | 2019-08-30 |
| CN110187918B (en) | 2024-03-12 |
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