CN209167476U - A kind of chip reset test board - Google Patents
A kind of chip reset test board Download PDFInfo
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- CN209167476U CN209167476U CN201821379893.5U CN201821379893U CN209167476U CN 209167476 U CN209167476 U CN 209167476U CN 201821379893 U CN201821379893 U CN 201821379893U CN 209167476 U CN209167476 U CN 209167476U
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Abstract
The utility model relates to a kind of chip reset test boards, comprising: microcontroller (1), digital analog converter (2), operational amplification circuit (3), level shifting circuit (4), low-dropout regulator (5) and chip to be measured (7).Chip reset test board provided by the utility model, by the way that analog signal is input to operational amplification circuit, it is used as chip power to be measured to use to after power and voltage amplification, pass through parameter configuration, more power pulse waveforms can be covered, so that chip testing is more accurate, and automatic test and batch testing can be easily achieved than more comprehensively measuring the situation of chip reset exception.
Description
Technical Field
The utility model belongs to the technical field of the electronic circuit, concretely relates to chip resets and surveys test panel.
Background
At present, with the development of science and technology, electronic chips have been widely used in various electronic products. After the chip manufacturing production is completed, the chip needs to be tested. The chip Reset means that when the chip is powered On after Power failure or Power supply low-voltage negative pulse occurs, a Power-On Reset (POR for short) operation needs to be performed.
However, in some cases, such as when the voltage is not low enough or the power supply falls and rises slowly, the chip may operate abnormally or cannot be reset. Therefore, the chip needs to be reset before mass production to ensure the stability and reliability of the operation. The traditional test is reset simply, and is usually a manual test, namely, the chip is manually powered on and off repeatedly, and whether the chip works normally or not is judged manually according to the data output by the IO output high and low level or the serial port of the chip.
However, manual testing cannot cover all power supply pulse waveforms, and the testing method cannot cover all situations, so that reliability and accuracy of data are not easy to ensure, labor is consumed, and automatic testing and batch testing are not easy to realize.
SUMMERY OF THE UTILITY MODEL
In order to solve the above-mentioned problem that exists among the prior art, the utility model provides a chip resets and surveys test panel. The to-be-solved technical problem of the utility model is realized through following technical scheme:
a chip reset test board comprising: the device comprises a microcontroller, a digital-to-analog converter, an operational amplifier circuit, a level conversion circuit, a low dropout regulator and a chip to be tested; wherein,
the level conversion circuit is connected between the microcontroller and the chip to be tested;
the microcontroller is connected with the digital-to-analog converter;
the digital-to-analog converter is connected with the operational amplification circuit;
the operational amplification circuit is connected with the chip to be tested;
the low dropout voltage regulator is connected with the microcontroller and the operational amplification circuit;
the microcontroller is provided with an interface for receiving configuration parameters of the microcontroller.
Preferably, the device further comprises a display screen, and the display screen is connected with the microcontroller.
Preferably, the interface is a serial port, and the microcontroller is connected with an upper computer through the serial port.
Preferably, the microcontroller, the digital-to-analog converter, the operational amplifier circuit, the level conversion circuit, the low dropout voltage regulator, the display screen and the chip to be tested are all arranged on a mainboard.
Preferably, the operational amplification circuit includes: the operational amplifier chip, a resistor R10, a resistor R11, a resistor R12 and a capacitor C10; wherein,
the resistor R10 and the resistor R11 are sequentially connected in series between the pin 1 of the operational amplifier chip and a ground terminal; the resistor R12 is connected in series between the output end of the digital-analog converter and the pin 3 of the operational amplifier chip;
the capacitor C10 is sequentially connected in series between the operational amplifier chip pin 8 and the grounding end;
the low dropout voltage regulator is connected between nodes formed by connecting the operational amplifier chip pin 8 and the capacitor C10 in series;
the chip to be tested is connected between nodes formed by connecting the resistor R10 and the pins 1 of the operational amplifier chip in series;
the operational amplifier chip pin 2 is connected between a node formed by connecting the resistor R10 and the resistor R11 in series;
the operational amplifier chip pin 4 is connected between the resistor R11 and a node formed by serially connecting the ground terminals.
Preferably, the operational amplifier chip is of the model MC 33202.
Preferably, the level conversion circuit includes: a first conversion circuit and a second conversion circuit; wherein,
the input end of the first conversion circuit is connected with the output end of the microcontroller;
the output end of the first conversion circuit is connected with the input end of the chip to be tested;
the input end of the second conversion circuit is connected with the output end of the chip to be tested;
and the output end of the second conversion circuit is connected with the input end of the microcontroller.
Preferably, the first conversion circuit includes: the circuit comprises a first conversion chip, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a capacitor C20, a capacitor C21 and a diode D20; wherein,
the first conversion chip pin 1 is connected to a power supply end of the microcontroller; the first conversion chip pin 2 is connected to a ground terminal; the first conversion chip pin 4 is connected to the input end of the chip to be tested;
the resistor R20 is connected in series between the first conversion chip pin 5 and a power supply end of the microcontroller; the resistor R21 is connected in series between the output end of the microcontroller and the pin 3 of the first conversion chip; the resistor R22 is connected in series between the power supply end of the chip to be tested and the first conversion chip pin 6; the resistor R23 is connected in series between the first conversion chip pin 4 and the ground terminal;
the capacitor C20 is connected in series between the first conversion chip pin 1 and the ground terminal; the capacitor C21 is connected in series between the first conversion chip pin 6 and the ground terminal;
the positive electrode of the diode D20 is connected to a node formed by the resistor R23 and the grounding end in series; the negative electrode of the diode D20 is connected to the input end of the chip to be tested.
Preferably, the second conversion circuit includes: the second conversion chip, a resistor R24, a resistor R25, a resistor R26, a resistor R27, a resistor C22, a capacitor C23 and a diode D21; wherein,
the second conversion chip pin 1 is connected to a power supply end of the microcontroller; the second conversion chip pin 2 is connected to a ground terminal; the second conversion chip pin 4 is connected to the input end of the chip to be tested;
the resistor R24 is connected in series between the first conversion chip pin 5 and the ground terminal; the resistor R25 is connected in series between the microcontroller input end (MCU RX) and the second conversion chip pin 3; the resistor R26 is connected in series between the power supply end of the chip to be tested and the second conversion chip pin 6; the resistor R27 is connected in series between the second conversion chip pin 4 and the ground terminal;
the capacitor C22 is connected in series between the second conversion chip pin 1 and the ground terminal; the capacitor C23 is connected in series between the second conversion chip pin 6 and the ground terminal;
the positive electrode of the diode D21 is connected to a node formed by the resistor R27 and the grounding end in series; the negative electrode of the diode D21 is connected to the output end of the chip to be tested.
Preferably, the first conversion chip model is SN74LVC1T 45.
The utility model has the advantages that:
the utility model provides a chip resets and surveys test panel uses as the chip power that awaits measuring after passing through analog signal input to operational amplification circuit, with analog signal's power and voltage amplification, through parameter configuration, can cover more power impulse waveforms, and data are accurate, and the realization is with low costs, and easily realizes automatic test and batch test.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic structural diagram of a chip reset test board according to the present invention;
fig. 2 is a schematic diagram of an operational amplifier circuit of a chip reset test board according to the present invention;
fig. 3 is a schematic diagram of a level shift circuit of a chip reset test board according to the present invention;
fig. 4 is a waveform diagram of an oscilloscope showing that the chip is successfully reset in the chip reset test board provided by the utility model;
fig. 5 is the utility model provides a pair of oscilloscope oscillogram that test panel chip successfully resets is reseed in chip reset.
Description of the symbols: 1. a microcontroller; 2. a digital-to-analog converter; 3. an operational amplifier circuit; 4. a level conversion circuit; 5. a low dropout regulator; 6. a display screen; 7. a chip to be tested; 8. a main board; 9. a first circuit; 10. a second circuit.
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined purpose, the following detailed description of the embodiments, structural features and effects of the present invention will be made with reference to the accompanying drawings and examples.
Example 1:
referring to fig. 1, fig. 2 and fig. 3, fig. 1 is a schematic structural diagram of a chip reset test board according to the present invention; fig. 2 is a schematic diagram of an operational amplifier circuit of a chip reset test board according to the present invention; fig. 3 is the utility model provides a level shift circuit principle schematic diagram of survey test panel is reset to chip. As shown in fig. 1, a test board for resetting a chip to be tested, includes: a Microcontroller (MCU) 1, a Digital-to-Analog Converter (DAC) 2, an operational amplifier circuit 3, a level conversion circuit 4, a low dropout regulator (LDO) 5 and a chip to be tested 7; wherein,
the level conversion circuit 4 is connected between the microcontroller 1 and the chip 7 to be tested and is used for converting and isolating the voltage between the microcontroller 1 and the chip 7 to be tested; the microcontroller 1 is connected with the digital-to-analog converter 2 and used for outputting a digital signal to the digital-to-analog converter 2; the digital-analog converter 2 is connected with the operational amplifier circuit 3 and is used for converting the digital signal into a first analog signal and outputting the first analog signal to the operational amplifier circuit 3; the operational amplification circuit 3 is connected with the chip 7 to be tested and used for receiving the first analog signal, amplifying the first analog signal to form a second analog signal and outputting the second analog signal to the chip 7 to be tested; the low dropout regulator 5 is connected with the microcontroller 1 and the operational amplification circuit 3 and is used for providing power supply for the microcontroller 1 and the operational amplification circuit 3; the microcontroller 1 is provided with an interface for receiving configuration parameters of the microcontroller 1.
Preferably, the test device further comprises a display screen 6, wherein the display screen 6 is connected with the microcontroller 1 and is used for displaying the test result of the chip 7 to be tested; the test board provided by the embodiment is used for repeatedly testing the chip to be tested, namely, repeatedly testing the chip to be tested for hundreds of times within 1 second, and the display screen 6 is used for displaying the test result of the chip to be tested, namely displaying the number of times of resetting success or failure of the test chip.
Preferably, the present embodiment provides a test board to which the chip 7 under test is connected by a chip gripper.
Specifically, the microcontroller 1, the digital-to-analog converter 2, the operational amplifier circuit 3, the level conversion circuit 4, the low dropout regulator 5, the display screen 6 and the chip 7 to be tested are all arranged on a main board.
Preferably, the main board is a PCB board.
Specifically, the external power supply of the test board is connected with the low dropout regulator 5, and supplies power to the microcontroller 1 and the operational amplifier circuit 3 after being reduced in voltage by the low dropout regulator 5.
Preferably, the microcontroller 1 outputs a digital signal, and the output digital signal is converted into an analog signal after passing through the external digital-to-analog converter 2. The microcontroller can select an XAD3001 chip, adopts a 32-bit core, comprises a DAC peripheral and can directly output an analog signal; the microcontroller may also be selected from other microcontrollers capable of outputting analog signals.
Preferably, the microcontroller 1 is provided with an interface, the interface is a serial port, and the microcontroller 1 is connected with an upper computer through the serial port and is used for configuring analog signal parameters output by the microcontroller 1, namely parameters of configuration test signals.
Preferably, the analog signal output by the microcontroller 1 may be configured by an upper computer, wherein the upper computer is connected to the microcontroller 1 through a serial port interface of the microcontroller, and then communicates with the microcontroller 1 to perform configuration parameters, that is, configure the analog signal output by the microprocessor 1. The configuration parameters are mainly used for determining the maximum output value of the analog signal output by the microcontroller 1, the rising and falling time of the negative pulse, the minimum duration time of the negative pulse, the number of the negative pulses, the test times and the like, and the configuration parameters can also be set as random configuration parameters.
Preferably, after the analog signal output by the digital-to-analog converter 2 passes through the operational amplifier circuit, the power and voltage of the analog signal are amplified and then used as the power supply of the chip to be tested, that is, the test voltage.
Preferably, as shown in fig. 2, the operational amplification circuit 3 includes: the operational amplifier chip U1, the resistor R10, the resistor R11, the resistor R12 and the capacitor C10; wherein,
the resistor R10 and the resistor R11 are sequentially connected in series between a pin 1 of the operational amplifier chip U1 and a ground terminal GND; the resistor R12 is connected in series between the digital-analog converter 2 and the U1 pin 3 of the operational amplifier chip; the capacitor C10 is sequentially connected in series between the pin 8 of the operational amplifier chip U1 and the ground end GND; the low dropout regulator 5 is connected between a node formed by connecting a pin 8 of the operational amplifier chip U1 in series with the capacitor C10; the chip 7 to be tested is connected between the resistor R10 and a node formed by connecting the pins 1 of the U1 of the operational amplifier chip in series; the pin 2 of the operational amplifier chip U1 is connected between the node formed by the resistor R10 and the resistor R11 in series; the pin 4 of the operational amplifier chip U1 is connected between the resistor R11 and a node formed by the ground GND in series.
Preferably, the model of the operational amplifier chip U1 is MC33202, the operational amplifier chip U1 is connected to the low dropout regulator 5 through a pin 8, and has supplied power to the operational amplifier chip U1, an analog signal output by the digital-analog converter 2 passes through a resistor R12 and enters the operational amplifier chip U1 through a pin 3 of the operational amplifier chip, and the operational amplifier chip U1 performs power amplification, voltage amplification, or power and voltage amplification on the analog signal, and then outputs the amplified analog signal to the chip to be tested through a pin 1 of the operational amplifier chip, so that the amplified analog signal is used for testing the chip to be tested.
Specifically, since the operating voltages of the microcontroller 1 and the chip to be tested are not the same, the level shift circuit 4 is required to perform conversion isolation on the voltages of the microcontroller 1 and the chip to be tested, that is, to convert the signal voltage of the communication between the microcontroller 1 and the chip to be tested, so as to facilitate the communication between the two.
Preferably, the level conversion circuit 4 includes: a first conversion circuit 9 and a second conversion circuit 10; the input end of the first conversion circuit 9 is the first input end of the level conversion circuit 4 and is connected with the output end of the microcontroller 1; the output end of the first conversion circuit 9 is the first output end of the level conversion circuit 4 and is connected with the input end of the chip 7 to be tested; the input end of the second conversion circuit 10 is a second input end of the level conversion circuit 4 and is connected with the output end of the chip 7 to be tested; the output end of the second conversion circuit 10 is a second output end of the level conversion circuit 4 and is connected with the input end of the microcontroller 1.
Preferably, the first conversion circuit 9 is configured to perform voltage conversion on the signal output by the microcontroller 1, so as to convert the signal into a signal suitable for the working voltage of the chip to be tested; the second conversion circuit 10 is used to convert the output signal of the chip to be tested into an operating voltage signal suitable for the microcontroller 1.
Preferably, the first conversion circuit includes: the circuit comprises a first conversion chip U2, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a capacitor C20, a capacitor C21 and a diode D20; pin 1 of the first conversion chip U2 is connected to a power supply end MCU VCC of the microcontroller 1; pin 2 of the first conversion chip U2 is connected to a ground terminal GND; the pin 4 of the first conversion CHIP U2 is connected to the input terminal CHIP RX of the CHIP 7 to be tested; the resistor R20 is connected in series between the pin 5 of the U2 of the first conversion chip and a power supply end MCU VCC of the microcontroller 1; the resistor R21 is connected in series between the output end MCUTX of the microcontroller 1 and the pin 3 of the U2 of the first conversion chip; the resistor R22 is connected in series between a power supply end CHIPVCC of the chip 7 to be tested and the pin 6 of the first conversion chip U2; the resistor R23 is connected in series between the U2 pin 4 of the first conversion chip and the ground GND; the capacitor C20 is connected in series between the U2 pin 1 of the first conversion chip and the ground end GND; the capacitor C21 is connected in series between the U2 pin 6 of the first conversion chip and the ground end GND; the positive electrode of the diode D20 is connected to a node formed by the resistor R23 and the ground end GND in series; the negative electrode of the diode D20 is connected to the input terminal CHIP RX of the CHIP 7 under test.
Preferably, the I/O interface of the microcontroller 1 is connected to the first conversion chip pin 5 for providing a direction to the first conversion chip, i.e. determining a conversion voltage direction of the first conversion chip by an input signal of the first conversion chip pin 5,
preferably, the second conversion circuit includes: the second conversion chip U3, the resistor R24, the resistor R25, the resistor R26, the resistors R27 and C22, the capacitor C23 and the diode D21; pin 1 of the second conversion chip U3 is connected to a power supply end MCU VCC of the microcontroller 1; pin 2 of the second conversion chip U3 is connected to a ground terminal GND; the pin 4 of the second conversion CHIP U3 is connected to the input terminal CHIP RX of the CHIP 7 to be tested; the resistor R24 is connected in series between the pin 5 of the first conversion chip U2 and a ground end GND; the resistor R25 is connected in series between the input end MCU RX of the microcontroller 1 and the pin 3 of the U3 of the second conversion chip; the resistor R26 is connected in series between a power supply terminal CHIP VCC of the CHIP 7 to be tested and the pin 6 of the second conversion CHIP U3; the resistor R27 is connected in series between the pin 4 of the U3 of the second conversion chip and the ground end GND; the capacitor C22 is connected in series between the pin 1 of the U3 of the second conversion chip and the ground end GND; the capacitor C23 is connected in series between the pin 6 of the second conversion chip U3 and the ground end GND; the positive electrode of the diode D21 is connected to a node formed by the resistor R27 and the ground end GND in series; the negative electrode of the diode D21 is connected to the output terminal CHIP TX of the CHIP 7 to be tested.
Preferably, the first conversion chip U2 and the second conversion chip U3 are both SN74LVC1T45, the rated voltage of the chip to be tested is 5 volts, the resistance of R10 is 10 kilo-ohms, the resistance of R11 is 15 kilo-ohms, the resistance of R12 is 1 kilo-ohms, the resistance of R20 is 4.7 kilo-ohms, the resistance of R21 is 330 ohms, the resistance of R22 is 100 ohms, the resistance of R23 is 4.7 kilo-ohms, the resistance of R24 is 4.7 kilo-ohms, the resistance of R25 is 330 ohms, the resistance of R26 is 100 ohms, the resistance of R27 is 4.7 kilo-ohms, the resistance of the capacitor C10 is 1 microfarad, and the capacitors C20, C21, C22 and C23 are all 100 picofarads.
The utility model provides a chip resets and surveys test panel, through with analog signal input to operational amplification circuit after, regard as the chip power that awaits measuring to power and voltage amplification back and use, through parameter configuration, can cover more power impulse waveforms, and easily realize automatic test and test in batches.
Example 2:
please continue to refer to fig. 1, and fig. 4 and 5, fig. 4 is a waveform diagram of an oscilloscope in which the chip reset test board provided by the present invention successfully resets the chip; fig. 5 is the utility model provides a pair of oscilloscope oscillogram that test panel chip successfully resets is reseed in chip reset. This embodiment is exemplified on the basis of the above embodiment. In this embodiment, a chip to be tested is tested through the chip reset test board provided in embodiment 1, where the chip to be tested is XAD 1605.
Preferably, before the chip to be tested is tested, firstly, an operation code is written into the microcontroller 1, and the operation code is used for controlling the DAC output, communicating the microcontroller 1 with the chip to be tested, communicating the microcontroller 1 with an upper computer, and displaying on a display screen of a control mainboard of the microcontroller 1.
Preferably, before the chip to be tested is tested, a response code needs to be written into the chip to be tested, and the response code is used for controlling another IO interface of the chip to be tested to output a high level or a low level by detecting a state of the high level or the low level through a preset IO interface of the chip to be tested. And interfaces such as a serial port and the like can be used for communicating the main board MCU with the chip to be tested.
Preferably, as shown in fig. 1, an external power supply is connected through the low dropout regulator 5 for supplying power to the test board, and the chip to be tested is placed in the chip to be tested 7 of the test board, and the position is adjusted to ensure that the chip to be tested is in good contact.
Preferably, after the test board is powered on, the test board is connected with an upper computer through a serial port on the microcontroller 1, the test board is configured through the upper computer, configuration parameters are determined, the configuration parameters are mainly used for determining the maximum value of an output signal of the microcontroller 1, the rising time and the falling time of an output negative pulse, the minimum duration time of the output negative pulse, the number of the negative pulses, the test times and the like, and the configuration parameters can also be configured into random numbers.
Preferably, before the chip to be tested is subjected to the reset test, a normal operating voltage is firstly applied to the chip to be tested to ensure that the chip can normally operate under the normal operating voltage.
Preferably, in the reset test of the chip to be tested, firstly, the chip to be tested is subjected to a normal voltage test, that is, the microprocessor 1 outputs a stable digital signal, the digital signal is converted into an analog signal through the DAC2, and then the analog signal is amplified by the operational amplifier circuit 3 to output a stable test voltage, and the test voltage is a normal operating voltage of the chip to be tested. Then, the microprocessor 1 communicates with the chip to be tested, that is, the first output end of the microprocessor 1 sends a test level to the chip to be tested through the level conversion circuit 4, and receives a feedback level of the chip to be tested through the input end of the microcontroller 1, wherein the feedback level of the chip to be tested is sent to the microcontroller through the level conversion circuit. In this embodiment, the normal operating voltage of the chip to be tested is 5V, that is, the voltage of the first test power supply is 5V. Therefore, the chip to be tested can work normally under a normal working power supply.
Preferably, the test board is used for testing the chip to be tested, wherein the test board repeatedly tests the chip to be tested for hundreds of times within 1 second, and the display screen 6 is used for displaying the test result of the chip to be tested, that is, displaying the number of times that the chip is reset successfully or fails.
Preferably, the first test probe of the oscilloscope is connected to the output end of the operational amplifier circuit, that is, to the power input end of the chip 7 to be tested. And connecting a second test probe of the oscilloscope with the output end of the level conversion circuit 4, namely, the input end of the chip 7 to be tested. And connecting a third test probe of the oscilloscope with the second input end of the level conversion circuit, namely, the output end of the chip 7 to be tested. The specific reset condition of the chip to be tested can be displayed.
Preferably, as shown in fig. 4, the waveform a is a power waveform of the chip to be tested, the waveform B is a signal waveform input when the chip to be tested communicates with the microprocessor 1, and the waveform C is a signal waveform output when the chip to be tested communicates with the microprocessor 1.
Preferably, as shown in fig. 4, the waveform of the waveform diagram is divided into 4 parts, where part a is to perform a complete power-down operation on the chip to be tested when starting the test; before the part b is tested, the microprocessor 1 communicates with the chip to be tested to determine whether the chip to be tested works normally, namely, whether the chip works normally is determined by determining whether the waveform output by the chip to be tested follows the waveform input by the chip to be tested. If the chip to be tested works normally, the waveform C is basically consistent with the waveform B, and is slightly delayed relative to the waveform B; the part c is the operation of power failure of the chip to be tested, and the waveform of the part is controllable by the microcontroller 1 so as to master the reset test condition of the chip to be tested; part d shows the result of the reset of the chip to be tested, and the waveform C can still follow the waveform B, which shows that the reset of the chip to be tested is normal. If the chip to be detected is abnormal after reset, the waveform C cannot follow the change of the waveform B, and the abnormal reset of the chip to be detected can be judged.
Preferably, as shown in fig. 5, the waveform a is a power waveform of the chip to be tested, the waveform B is a signal waveform input when the chip to be tested communicates with the microprocessor 1, and the waveform C is a signal waveform output when the chip to be tested communicates with the microprocessor 1.
Preferably, as shown in fig. 5, the waveform diagram is still divided into 4 parts, and the part a is to perform a complete power-down operation on the chip to be tested when starting the test. before the part b is tested, the microprocessor 1 communicates with the chip to be tested to determine whether the chip to be tested works normally, namely, whether the chip works normally is determined by determining whether the waveform output by the chip to be tested follows the waveform input by the chip to be tested. The part c is the operation of power failure of the chip to be tested; and the part d is the waveform of abnormal reset of the chip to be tested. It can be seen from the section d that after the waveform B becomes high level, namely the microcontroller 1 sends high level, the waveform C, namely the output of the chip to be tested is not changed into high level, and then the chip reset failure can be judged. After the reset of the chip to be tested fails, the chip to be tested cannot work normally, and the phenomenon is represented that no response is caused to the external input level. At this time, the test board provided by this embodiment records the abnormal reset and gives an alarm.
The utility model provides a chip resets and surveys test panel can provide more test pulse wave forms, can be more comprehensive measure the chip and reset the unusual condition for the chip test is more accurate, and easily realizes automatic test and batch test.
The foregoing is a more detailed description of the present invention, taken in conjunction with the specific preferred embodiments thereof, and it is not intended that the invention be limited to the specific embodiments shown and described. To the utility model belongs to the technical field of ordinary technical personnel, do not deviate from the utility model discloses under the prerequisite of design, can also make a plurality of simple deductions or replacement, all should regard as belonging to the utility model discloses a protection scope.
Claims (10)
1. A test board for resetting a chip, comprising: the device comprises a microcontroller (1), a digital-to-analog converter (2), an operational amplifier circuit (3), a level conversion circuit (4), a low dropout regulator (5) and a chip to be tested (7); wherein,
the level conversion circuit (4) is connected between the microcontroller (1) and the chip (7) to be tested;
the microcontroller (1) is connected with the digital-to-analog converter (2);
the digital-to-analog converter (2) is connected with the operational amplification circuit (3);
the operational amplification circuit (3) is connected with the chip (7) to be tested;
the low dropout regulator (5) is connected with the microcontroller (1) and the operational amplification circuit (3);
the microcontroller (1) is provided with an interface for receiving configuration parameters of the microcontroller (1).
2. The chip reset test board according to claim 1, further comprising a display screen (6), wherein the display screen (6) is connected to the microcontroller (1).
3. The chip reset test board according to claim 1, wherein the interface is a serial port, and the microcontroller (1) is connected to an upper computer through the serial port.
4. The chip reset test board according to claim 2, wherein the microcontroller (1), the digital-to-analog converter (2), the operational amplifier circuit (3), the level shifter circuit (4), the low dropout regulator (5), the display screen (6) and the chip under test (7) are all disposed on a motherboard (8).
5. The chip reset test board according to claim 1, wherein the operational amplifier circuit (3) comprises: the operational amplifier chip (U1), the resistor R10, the resistor R11, the resistor R12 and the capacitor C10; wherein,
the resistor R10 and the resistor R11 are sequentially connected in series between the pin 1 of the operational amplifier chip (U1) and a ground terminal (GND); the resistor R12 is connected in series between the output end of the digital-analog converter (2) and the pin 3 of the operational amplifier chip (U1);
the capacitor C10 is sequentially connected in series between the pin 8 of the operational amplifier chip (U1) and the ground terminal (GND);
the low dropout regulator (5) is connected between a node formed by connecting a pin 8 of the operational amplifier chip (U1) and the capacitor C10 in series;
the chip (7) to be tested is connected between the resistor R10 and a node formed by connecting pins 1 of the operational amplifier chip (U1) in series;
the pin 2 of the operational amplifier chip (U1) is connected between the nodes formed by the resistor R10 and the resistor R11 in series connection;
the pin 4 of the operational amplifier chip (U1) is connected between the resistor R11 and a node formed by connecting the ground terminal (GND) in series.
6. The board for testing chip reset according to claim 5, wherein said op-amp chip (U1) is of type MC 33202.
7. The chip reset test board according to claim 1, wherein the level shift circuit (4) comprises: a first conversion circuit (9) and a second conversion circuit (10); wherein,
the input end of the first conversion circuit (9) is connected with the output end of the microcontroller (1);
the output end of the first conversion circuit (9) is connected with the input end of the chip (7) to be tested;
the input end of the second conversion circuit (10) is connected with the output end of the chip (7) to be tested;
the output end of the second conversion circuit (10) is connected with the input end of the microcontroller (1).
8. The chip reset test board according to claim 7, wherein the first converting circuit comprises: the circuit comprises a first conversion chip (U2), a resistor R20, a resistor R21, a resistor R22, a resistor R23, a capacitor C20, a capacitor C21 and a diode D20; wherein,
the pin 1 of the first conversion chip (U2) is connected to a power supply end (MCU VCC) of the microcontroller (1); the pin 2 of the first conversion chip (U2) is connected to a ground terminal (GND); the pin 4 of the first conversion CHIP (U2) is connected to the input end (CHIP RX) of the CHIP to be tested (7);
the resistor R20 is connected in series between the pin 5 of the first conversion chip (U2) and a power supply end (MCUVCC) of the microcontroller (1); the resistor R21 is connected in series between the output end (MCU TX) of the microcontroller (1) and a pin 3 of the first conversion chip (U2); the resistor R22 is connected in series between a power supply end (CHIP VCC) of the CHIP (7) to be tested and a pin 6 of the first conversion CHIP (U2); the resistor R23 is connected in series between the pin 4 of the first conversion chip (U2) and the Ground (GND);
the capacitor C20 is connected in series between the pin 1 of the first conversion chip (U2) and the Ground (GND); the capacitor C21 is connected in series between the pin 6 of the first conversion chip (U2) and the Ground (GND);
the positive electrode of the diode D20 is connected to a node formed by the resistor R23 and the Ground (GND) in series; the negative electrode of the diode D20 is connected to the input terminal (CHIP RX) of the CHIP under test (7).
9. The chip reset test board according to claim 7, wherein the second converting circuit comprises: the second conversion chip (U3), the resistor R24, the resistor R25, the resistor R26, the resistor R27, the resistor C22, the capacitor C23 and the diode D21; wherein,
the pin 1 of the second conversion chip (U3) is connected to a power supply end (MCU VCC) of the microcontroller (1); the pin 2 of the second conversion chip (U3) is connected to a ground terminal (GND); the pin 4 of the second conversion CHIP (U3) is connected to the input end (CHIP RX) of the CHIP (7) to be tested;
the resistor R24 is connected in series between the pin 5 of the first conversion chip (U2) and the Ground (GND); the resistor R25 is connected in series between the input end (MCU RX) of the microcontroller (1) and the pin 3 of the second conversion chip (U3); the resistor R26 is connected in series between a power supply end (CHIP VCC) of the CHIP (7) to be tested and a pin 6 of the second conversion CHIP (U3); the resistor R27 is connected in series between the pin 4 of the second conversion chip (U3) and the Ground (GND);
the capacitor C22 is connected in series between the pin 1 of the second conversion chip (U3) and the Ground (GND); the capacitor C23 is connected in series between the pin 6 of the second conversion chip (U3) and the Ground (GND);
the positive electrode of the diode D21 is connected to a node formed by the resistor R27 and the Ground (GND) in series; the negative electrode of the diode D21 is connected to the output end (CHIP TX) of the CHIP (7) to be tested.
10. The board of claim 8, wherein the first converting chip (U2) has a model number SN74LVC1T 45.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111123077A (en) * | 2020-01-15 | 2020-05-08 | 深圳赛意法微电子有限公司 | Failure positioning method for chip |
| CN111610433A (en) * | 2020-06-17 | 2020-09-01 | 江西联智集成电路有限公司 | Chip power-on and power-off reset test method and device |
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2018
- 2018-08-24 CN CN201821379893.5U patent/CN209167476U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111123077A (en) * | 2020-01-15 | 2020-05-08 | 深圳赛意法微电子有限公司 | Failure positioning method for chip |
| CN111123077B (en) * | 2020-01-15 | 2022-03-08 | 深圳赛意法微电子有限公司 | Failure positioning method for chip |
| CN111610433A (en) * | 2020-06-17 | 2020-09-01 | 江西联智集成电路有限公司 | Chip power-on and power-off reset test method and device |
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