CN209133518U - One kind is novel to bury grid photovoltaic cell - Google Patents

One kind is novel to bury grid photovoltaic cell Download PDF

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Publication number
CN209133518U
CN209133518U CN201821750291.6U CN201821750291U CN209133518U CN 209133518 U CN209133518 U CN 209133518U CN 201821750291 U CN201821750291 U CN 201821750291U CN 209133518 U CN209133518 U CN 209133518U
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China
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layers
layer
groove
type silicon
utility
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Inventor
赵卫东
赵沁
费春燕
赵雅
赵枫
杨冬琴
朱广和
李向华
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JIANGSU ECONESS ENERGY CO Ltd
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JIANGSU ECONESS ENERGY CO Ltd
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Abstract

The utility model discloses it is a kind of it is novel bury grid photovoltaic cell, be related to technical field of photovoltaic power generation.The utility model includes P-type silicon plate, P-type silicon plate upper surface is equipped with N++ layers, N++ layers of upper surface are equipped with N+ layers, N+ layers of upper surface are equipped with silicon oxide layer, and silicon oxide layer is equipped with selective emitter junction layer, and P-type silicon plate lower surface is equipped with back electric field, it carries on the back electric field lower surface and is equipped with back electrode, silicon oxide layer, N+ layers, N++ layers and P-type silicon plate, which are equipped with, offers groove, and groove is the slot carved using laser, and plating grid line is filled in groove.The utility model carries out cutting by laser, and it will be in the narrow trenches of the grid line of metallization insertion battery surface, cell piece series resistance is reduced by selective emitter junction, by using the grid line of the method preparation metallization of electronickelling, copper and tin, the metallization for realizing battery solves the problems, such as that existing photovoltaic cell generating efficiency is lower.

Description

One kind is novel to bury grid photovoltaic cell
Technical field
The utility model belongs to technical field of photovoltaic power generation, buries grid photovoltaic cell more particularly to one kind is novel.
Background technique
Along with the rapid growth of global energy requirements, traditional fossil energy (coal, oil and natural gas etc.) is increasingly reduced And its caused Heavy environmental pollution and global warming promote people increasingly to pay attention to renewable energy the pressure of ecology Use, solar energy is one of the renewable energy of most development and application prospect, and photovoltaic power generation be undoubtedly currently with too The optimal path of positive energy promotes photovoltaic power generation cost continuous in recent years due to the promotion of the progress of photovoltaic technology and regulation, policy It reduces, while market also sharply expands, photovoltaic industry becomes one of the industry that whole world growth is most fast nearly ten years.
Silver paste is directly printed in the front surface of cell piece, electrode zone by the routine solar cell silk screen printing stage at present Directly constituted shading-area, effective light absorption of cell piece is affected, although the region blocked by electrode is due to the folding of light Penetrate not can not carry out photoelectric conversion with diffraction completely, but the occlusion effect of preceding electrode still compare loss in efficiency part can It sees.
It is primarily intended to the overlay area by reducing silver paste technically at present to improve this situation, but contact area reduces It will affect the resistance value of the collecting effect of electric current and the resistance of contact afterwards, it is therefore desirable to which the depth-width ratio of electrode before being promoted in this way may be used To guarantee the contact resistance between electrode and semiconductor under the premise of reducing shielded area.
But for now, silkscreen process is constrained by industry technology, and solar battery printing screen plate line width is Almost close to the limit, so must be by being transformed to process flow, in guarantee electrode under the premise of good electric conductivity Shielded area is reduced as far as possible.
Utility model content
The purpose of this utility model is to provide it is a kind of it is novel bury grid photovoltaic cell, cutting is carried out by laser, and will In the narrow trenches of the grid line insertion battery surface of metallization, cell piece series resistance is reduced by selective emitter junction, is passed through Using the grid line of the method preparation metallization of electronickelling, copper and tin, the metallization of battery is realized, solves existing photovoltaic electric The lower problem of pond piece generating efficiency.
In order to solve the above technical problems, the utility model is achieved through the following technical solutions:
The utility model, which is that one kind is novel, buries grid photovoltaic cell, including P-type silicon plate, and P-type silicon plate upper surface is equipped with N ++ layer, the upper surface N++ layers of are equipped with N+ layers, and the upper surface N+ layers of is equipped with silicon oxide layer, and the silicon oxide layer is equipped with choosing Selecting property emitter junction layer, P-type silicon plate lower surface are equipped with back electric field, and the back electric field lower surface is equipped with back electrode, and selectivity is sent out Knot layer is penetrated using lithography preparation is returned, carries out the silicon wafer after cutting to diffuse to form deep knot low square resistance deeply first, then in cutting area Organic material exposure mask is printed as etching barrier layer in domain, and the sheet resistance of non-blocking layer overlay area is improved by acid liquid corrosion, is covered Low square resistance when retaining diffusion at mould locality protection removes mask by lye, forms height and ties;
The silicon oxide layer, N+ layers, N++ layers and P-type silicon plate are equipped with and offer groove, and groove is carved using laser Slot, the groove are interior filled with plating grid line.
Further, the plating grid line includes deposited nickel layer, in order in the extremely upper depositing subsequent plating of silicon when deposited nickel layer Required conductive layer, the deposited nickel layer upper surface are equipped with electroless nickel layer, and electroless nickel layer mainly thickeies nickel layer, thicker Nickel layer copper and silicon wafer are separated, the electroless nickel layer upper surface be equipped with copper layer, the copper layer upper surface be equipped with electricity Tin coating, plating tin layers play a good protective effect to layers of copper and prevent its oxidation, and be electroplated tin layers be capable of providing it is good Solderability is laid a solid foundation for the welding of assembly end.
Further, the cross section of the groove is inverted triangular structure, the model of the width of the groove in 20-25um It encloses, the range of the depth of the groove in 10-15um.
The utility model has the following beneficial effects:
1, the utility model carries out cutting by laser, while the grid line of metallization being embedded in the narrow trenches of battery surface It is interior, so that reducing the contact resistance of grid line and silicon wafer under the premise of not increasing surface shading-area, it not only can increase grid line height Wide ratio, while making the better collected current of grid line, improve the generating efficiency of battery.
2, the utility model prepares selective emitter junction by returning lithography, and the silicon wafer after cutting is carried out deep divergent contour first Low square resistance is tied at deep, is then improved by acid liquid corrosion non-in cutting region printing organic material exposure mask as etching barrier layer The sheet resistance of barrier layer overlay area has low square resistance when retaining diffusion at masked areas protection that mask is removed by lye, It forms height to tie, reduces cell piece series resistance, realize preferable fill factor.
3, the utility model prepares grid line by using the method for electronickelling, copper and tin, realizes the metallization of battery, first Very thin nickel layer is first deposited using chemical method, for the conductive layer needed for the extremely upper depositing subsequent plating of silicon, second step carries out electricity Nickel plating thickeies nickel layer, and thicker nickel layer separates copper and silicon wafer, and third step deposits thicker layers of copper, can obtain The layers of copper of very high purity finally carries out electrotinning to give full play to its excellent cost performance, and electrotinning can play layers of copper Good protective effect prevents its oxidation, next is to provide good solderability, lays a solid foundation for the welding of assembly end.
Certainly, any product for implementing the utility model does not necessarily require achieving all the advantages described above at the same time.
Detailed description of the invention
In order to illustrate more clearly of the technical solution of the utility model embodiment, make required for being described below to embodiment Attached drawing is briefly described, it should be apparent that, the drawings in the following description are merely some embodiments of the present invention, For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings Other attached drawings.
Fig. 1 is the novel structural schematic diagram for burying grid photovoltaic cell of one kind of the utility model;
Fig. 2 is the partial enlarged view in Fig. 1 at A;
Fig. 3 is the Structure explosion diagram of Fig. 1;
Fig. 4 is the structure sectional view that grid line is electroplated;
In attached drawing, parts list represented by the reference numerals are as follows:
1-P type silicon plate, 2-N++ layers, 3-N+ layers, 4- silicon oxide layer, 5- selective emitter junction layer, 6- back electric field, 7- back electricity Grid line, 901- deposited nickel layer, 902- electroless nickel layer, 903- copper layer, 904- plating tin layers are electroplated in pole, 8- groove, 9-.
Specific embodiment
The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are without creative efforts All other embodiment obtained, fall within the protection scope of the utility model.
It please refers to shown in Fig. 1-3, the utility model, which is that one kind is novel, buries grid photovoltaic cell, including P-type silicon plate 1, P-type silicon 1 upper surface of plate is equipped with N++ layer 2, and 2 upper surface of N++ layer is equipped with N+ layer 3, and 3 upper surface of N+ layer is equipped with silicon oxide layer 4, silicon oxide layer 4 It is equipped with selective emitter junction layer 5,1 lower surface of P-type silicon plate is equipped with back electric field 6, and back 6 lower surface of electric field is equipped with back electrode 7, selection Property emitter junction layer 5 using lithography preparation is returned, first by the silicon wafer after cutting carry out it is deep diffuse to form deep knot low square resistance, then carving Organic material exposure mask is printed as etching barrier layer in slot region, and the sheet resistance of non-blocking layer overlay area is improved by acid liquid corrosion, There is low square resistance when retaining diffusion at masks area protection that mask is removed by lye, forms height and tie;
Silicon oxide layer 4, N+ layer 3, N++ layer 2 and P-type silicon plate 1 are equipped with and offer groove 8, and groove 8 is carved using laser Slot, filled with plating grid line 9 in groove 8.
Wherein as shown in figure 4, plating grid line 9 includes deposited nickel layer 901, in order in the extremely upper deposition of silicon when deposited nickel layer 901 Conductive layer needed for subsequent plating, 901 upper surface of deposited nickel layer are equipped with electroless nickel layer 902, and electroless nickel layer 902 is mainly to nickel layer It is thickeied, thicker nickel layer separates copper and silicon wafer, and 902 upper surface of electroless nickel layer is equipped with copper layer 903, copper layer 903 upper surfaces are equipped with plating tin layers 904, and plating tin layers 904 play a good protective effect to layers of copper and prevent its oxidation, and electricity Tin coating 904 is capable of providing good solderability, lays a solid foundation for the welding of assembly end.
Wherein, the cross section of groove 8 is inverted triangular structure, range of the width of groove 8 in 20-25um, the depth of groove 8 Spend the range in 10-15um.
In the description of this specification, the description of reference term " one embodiment ", " example ", " specific example " etc. means Particular features, structures, materials, or characteristics described in conjunction with this embodiment or example are contained at least one of the utility model In embodiment or example.In the present specification, schematic expression of the above terms be not necessarily referring to identical embodiment or Example.Moreover, particular features, structures, materials, or characteristics described can be in any one or more embodiment or examples In can be combined in any suitable manner.
The preferred embodiment in the utility model disclosed above is only intended to help to illustrate the utility model.Preferred embodiment is simultaneously There is no the details that detailed descriptionthe is all, also not limiting the utility model is only the specific embodiment.Obviously, according to this theory The content of bright book can make many modifications and variations.These embodiments are chosen and specifically described to this specification, is in order to preferably The principles of the present invention and practical application are explained, so that skilled artisan be enable to better understand and utilize this Utility model.The utility model is limited only by the claims and their full scope and equivalents.

Claims (3)

1. one kind is novel to bury grid photovoltaic cell, including P-type silicon plate (1), it is characterised in that:
P-type silicon plate (1) upper surface is equipped with N++ layers (2), and N++ layers described (2) upper surface is N+ layers described equipped with N+ layers (3) (3) upper surface is equipped with silicon oxide layer (4), and the silicon oxide layer (4) is equipped with selective emitter junction layer (5), the P-type silicon plate (1) lower surface is equipped with back electric field (6), and the back electric field (6) lower surface is equipped with back electrode (7);
The silicon oxide layer (4), N+ layers (3), N++ layers (2) and P-type silicon plate (1) are equipped with and offer groove (8), the groove (8) filled with plating grid line (9) in.
2. one kind according to claim 1 is novel to bury grid photovoltaic cell, which is characterized in that plating grid line (9) packet It includes deposited nickel layer (901), deposited nickel layer (901) upper surface is equipped with electroless nickel layer (902), on the electroless nickel layer (902) Surface is equipped with copper layer (903), and copper layer (903) upper surface is equipped with plating tin layers (904).
3. one kind according to claim 1 is novel to bury grid photovoltaic cell, which is characterized in that the groove (8) it is transversal Face is inverted triangular structure, and the width of the groove (8) is in the range of 20-25um, and the depth of the groove (8) is in 10-15um Range.
CN201821750291.6U 2018-10-27 2018-10-27 One kind is novel to bury grid photovoltaic cell Active CN209133518U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201821750291.6U CN209133518U (en) 2018-10-27 2018-10-27 One kind is novel to bury grid photovoltaic cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201821750291.6U CN209133518U (en) 2018-10-27 2018-10-27 One kind is novel to bury grid photovoltaic cell

Publications (1)

Publication Number Publication Date
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111403534A (en) * 2020-03-27 2020-07-10 晶澳(扬州)太阳能科技有限公司 Solar cell and preparation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111403534A (en) * 2020-03-27 2020-07-10 晶澳(扬州)太阳能科技有限公司 Solar cell and preparation method thereof
CN111403534B (en) * 2020-03-27 2022-04-15 晶澳(扬州)太阳能科技有限公司 Solar cell and preparation method thereof

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