CN209105147U - Preemphasis circuit and the high-speed interface circuit that preemphasis is realized using ESD protective device - Google Patents

Abstract

The high-speed interface circuit of preemphasis, including interface circuit, p-type preemphasis circuit and N-type preemphasis circuit are realized the utility model relates to preemphasis circuit and using ESD protective device；P-type preemphasis circuit pulls up moment open signal g_pesd for generating, and N-type preemphasis circuit can be realized moment unlatching pull-up ESD protective device PESD for generating drop-down moment open signal g_nesd, pull-up moment open signal g_pesd；Drop-down moment open signal g_nesd can be realized moment unlatching drop-down ESD protective device NESD.The utility model solves the low technical problem of existing output interface circuit working frequency; the utility model is on the basis of conventional interface circuit; increase preemphasis circuit, is opened by the moment that preemphasis circuit goes control sensing element to protect device ESD, to realize that working frequency increases substantially.

Description

Preemphasis circuit and the high-speed interface circuit that preemphasis is realized using ESD protective device

Technical field

The utility model relates to interface circuit design fields, and in particular to preemphasis circuit and utilization ESD protective device are real The high-speed interface circuit of existing preemphasis.

Background technique

As technique constantly develops, system operating frequency is constantly improved, and the output interface circuit of chip is at restriction The principal element of working frequency of chip.Determine that two crucial factors of chip output interface circuit working frequency are voltage conversion speed The capacitive load of rate (Slew Rate) and output interface signal.

Traditional output interface circuit is as shown in Figure 1:

Pullup driver P1, pull-down driver N1.PESD is the pull-up esd protection circuit that grid connects power supply, the grid of PESD Pole is connected on power vd D by resistance R2.NESD is the drop-down ESD protection circuit of grounded-grid (VSS), and the grid of NESD is logical Resistance R1 is crossed to be connected on VSS.The resistance value of resistance R1 and resistance R2 are bigger, generally in 1k~10K Ohm.It is this traditional defeated Outgoing interface circuit, the overturning of output interface signal is slow, to influence working frequency.

Utility model content

In order to solve the low technical problem of existing output interface circuit working frequency, one of the purpose of this utility model is mentioned For a kind of preemphasis circuit；The two of the purpose of this utility model are to provide a kind of height that preemphasis is realized using ESD protective device Fast interface circuit.

The technical solution of the utility model are as follows:

A method of improve output interface circuit working frequency, be characterized in that the following steps are included:

S1 it) generates a high-frequency and pulls up a pulse signal emp_p and high-frequency drop-down pulse signal emp_n；Pull-up The peak pulse duration input signal inp of pulse signal emp_p is narrow and contrary；The peak pulse duration of drop-down pulse signal emp_n inputs letter Number inp is narrow and contrary；The falling edge emp_n of input signal inp is height；Emp_p at the rising edge of input signal inp It is low；

S2 pull-up pulse signal emp_p) is converted into pull-up moment open signal g_pesd；

Drop-down pulse signal emp_n is converted into drop-down moment open signal g_nesd；

When drop-down pulse signal emp_n is high, drop-down moment open signal g_nesd opens ESD protective device NESD；Under It draws the failing edge of the previous pulse of pulse signal emp_n to the rising edge section of next pulse, pulls down moment open signal g_ Nesd closes ESD protective device NESD；

When pull-up pulse signal emp_p is low, drop-down moment open signal g_pesd opens ESD protective device PESD；On It draws the rising edge of the previous pulse of pulse signal emp_p to the failing edge section of next pulse, pulls down moment open signal g_ Pesd closes ESD protective device PESD；

S3) moment open signal g_pesd opens pull-up ESD protective device PESD, draws high the output letter of output interface circuit Number outp；Moment open signal g_nesd opens drop-down ESD protective device NESD, drags down the output signal of output interface circuit outp。

Further, in order to realize that the moment of drop-down ESD protective device NESD opens, S2) in will be pulled up by capacitor c_p Pulse signal emp_p is converted to pull-up moment open signal g_pesd；Pulse signal emp_n conversion will be pulled up by capacitor c_n To pull down moment open signal g_pesd.

The utility model also provides a kind of N-type preemphasis circuit, specifically includes

Phase inverter group: delay process is carried out to input signal inp and obtains inversion signal inp_n_n；

Nor gate Nor1: input signal inp is handled with inversion signal inp_n_n, obtains drop-down pulse signal emp_ The pulse width of n, drop-down pulse signal emp_n are equal to the sum of total delay of phase inverter；

Processing is carried out with capacitor c_n: drop-down pulse signal emp_n and generates drop-down moment open signal g_nesd, works as drop-down When pulse signal emp_n is high, drop-down moment open signal g_nesd opens ESD and protects device NESD；Drop-down pulse signal Rising edge section of the failing edge of the previous pulse of emp_n to next pulse, drop-down moment open signal g_nesd closing ESD Protect device NESD.

Further, general phase inverter group includes three concatenated phase inverters.

The utility model also provides a kind of p-type preemphasis circuit, specifically includes

Phase inverter group: delay process is carried out to input signal inp and obtains inversion signal inp_n_p；

NAND gate Nand1: handling input signal inp and inversion signal inp_n_p, obtains pull-up pulse signal Emp_p, the width of pull-up pulse signal emp_p are equal to the sum of total delay of phase inverter；

And capacitor: pull-up pulse signal emp_p carries out processing and generates pull-up moment open signal g_pesd, when pull-up pulse When signal emp_p is low, pull-up moment open signal g_pesd opens ESD protective device PESD；Pull up pulse signal emp_p Previous pulse rising edge to next pulse failing edge section, pull-up moment open signal g_pesd close ESD protection Device PESD.

Further, phase inverter group includes three concatenated p-type phase inverters.

The utility model provides a kind of high-speed interface circuit that preemphasis is realized using ESD protective device, including interface electricity Road, p-type preemphasis circuit and N-type preemphasis circuit；P-type preemphasis circuit is for generating pull-up moment open signal g_pesd, N Type preemphasis circuit can be realized moment for generating drop-down moment open signal g_nesd, pull-up moment open signal g_pesd Open pull-up ESD protective device PESD；Drop-down moment open signal g_nesd can be realized moment unlatching drop-down ESD protective device NESD。

The utility model have the utility model has the advantages that

1, the utility model increases preemphasis circuit, goes to control by preemphasis circuit on the basis of conventional interface circuit The moment of sensing element protection device ESD processed opens, to realize that working frequency increases substantially.

2, the preemphasis circuit output of the utility model is directly connected on esd protection circuit, so not additionally introducing defeated The capacitive load of signal out, so that high-frequency signal extra reflection will not be caused.

Detailed description of the invention

Fig. 1 is traditional output interface circuit figure；

Fig. 2 is the output interface circuit figure of the utility model；

Fig. 3 is the structure chart of N-type preemphasis circuit；

Fig. 4 is the timing diagram of N-type preemphasis circuit；

Fig. 5 is p-type preemphasis circuit structure chart；

Fig. 6 is the timing diagram of p-type preemphasis circuit；

Fig. 7 is the output waveform comparison schematic diagram of traditional output interface circuit and the utility model output interface circuit.

Specific embodiment

Embodiment 1: the utility model provides a kind of method for improving output interface circuit working frequency, and specific steps are such as Under:

S1 it) generates a high-frequency and pulls up a pulse signal emp_p and high-frequency drop-down pulse signal emp_n；Pull-up The peak pulse duration input signal inp of pulse signal emp_p is narrow and contrary；The peak pulse duration of drop-down pulse signal emp_n inputs letter Number inp is narrow and contrary；The falling edge emp_n of input signal inp is height；Emp_p at the rising edge of input signal inp It is low；

S2 pull-up pulse signal emp_p) is converted into pull-up moment open signal g_pesd；

Drop-down pulse signal emp_n is converted into drop-down moment open signal g_nesd；

When drop-down pulse signal emp_n is high, drop-down moment open signal g_nesd opens ESD protective device NESD；Under It draws the failing edge of the previous pulse of pulse signal emp_n to the rising edge section of next pulse, pulls down moment open signal g_ Nesd closes ESD protective device NESD；

When pull-up pulse signal emp_p is low, drop-down moment open signal g_pesd opens ESD protective device PESD；On It draws the rising edge of the previous pulse of pulse signal emp_p to the failing edge section of next pulse, pulls down moment open signal g_ Pesd closes ESD protective device PESD；

S3) moment open signal g_pesd opens pull-up ESD protective device PESD, draws high the output letter of output interface circuit Number outp；Moment open signal g_nesd opens drop-down ESD protective device NESD, drags down the output signal of output interface circuit outp。

Embodiment 2: in order to improve output interface circuit working frequency, two circuits: P are increased in original interface circuit Type preemphasis circuit and N-type preemphasis circuit.The output of p-type preemphasis circuit is connected on the grid of PESD.N-type preemphasis electricity The output on road is connected on the grid of NESD, and specific structure is as shown in Figure 2.The high-speed interface of preemphasis is realized with ESD protective device Circuit, including interface circuit, p-type preemphasis circuit and N-type preemphasis circuit；P-type preemphasis circuit is for generating pull-up moment Open signal g_pesd, N-type preemphasis circuit pull up moment open signal g_ for generating drop-down moment open signal g_nesd Pesd can be realized moment unlatching pull-up ESD protective device PESD；Drop-down moment open signal g_nesd can be realized moment and open Open drop-down ESD protective device NESD.

Embodiment 3: as shown in figure 3, the specific implementation structure of N-type preemphasis circuit are as follows: including phase inverter: to input signal Inp carries out delay process and obtains inversion signal inp_n_n；Nor: input signal inp is handled with inversion signal inp_n_n, Drop-down pulse signal emp_n is obtained, the width of drop-down pulse signal emp_n is equal to the sum of total delay of phase inverter；

Capacitor c_n: drop-down pulse signal emp_n, which carries out processing, generates drop-down moment open signal g_nesd, when drop-down arteries and veins Rush signal emp_n be it is high when, drop-down moment open signal g_nesd open NESD；The previous arteries and veins of drop-down pulse signal emp_n Rising edge section of the failing edge of punching to next pulse, drop-down moment open signal g_nesd closing NESD.

Drop-down pulse signal emp_n is generated, since drop-down pulse signal frequency is very high, emp_n is passed to by capacitor c_n The grid of NESD, NESD moment open, and output signal outp is helped quickly to drag down.

The timing diagram of pre-emphasis module N is as shown in Figure 4.

Embodiment 4: as shown in figure 5, p-type preemphasis circuit includes phase inverter: carrying out delay process to input signal inp and obtain To inversion signal inp_n_p；

Nand: handling input signal inp and inversion signal inp_n_p, obtains pull-up pulse signal emp_p, on The width of pulse signal emp_p is drawn to be equal to the sum of total delay of phase inverter；

With capacitor c_p: pull-up pulse signal emp_p carries out processing and generates pull-up moment open signal g_pesd, works as pull-up When pulse signal emp_p is low, pull-up moment open signal g_pesd opens PESD；Pull up the previous of pulse signal emp_p Failing edge section of the rising edge of pulse to next pulse, pull-up moment open signal g_pesd closing PESD.

P-type preemphasis circuit can generate a pulse signal emp_p, and since frequency is very high, emp_p is passed by capacitor c_p To the grid of PESD, PESD moment is opened, and output signal out is helped quickly to draw high.The timing diagram of pre-emphasis module N such as Fig. 6 institute Show.

Fig. 7 compares for the output waveform of traditional output interface circuit and novel output interface circuit.It can be seen from the figure that The output signal high level (voh) and output signal low level (vol) of tradition and the utility model interface circuit are consistent, but It is that the utility model structural circuit output signal level reaches time of voh or vol much faster, thus maximum operation frequency It is much bigger.

The preemphasis circuit output of the utility model is directly connected on esd protection circuit, so not additionally introducing output The load capacitance of signal, so that high-frequency signal extra reflection will not be caused.

Claims (7)

1. a kind of N-type preemphasis circuit, it is characterised in that: including

Phase inverter group: delay process is carried out to input signal inp and obtains inversion signal inp_n_n；

Nor gate Nor1: input signal inp is handled with inversion signal inp_n_n, obtains drop-down pulse signal emp_n, under The pulse width of pulse signal emp_n is drawn to be equal to the sum of total delay of phase inverter；

Processing is carried out with capacitor c_n: drop-down pulse signal emp_n and generates drop-down moment open signal g_nesd, works as drop-down pulse When signal emp_n is high, drop-down moment open signal g_nesd opens ESD protective device NESD；Drop-down pulse signal emp_n's Rising edge section of the failing edge of previous pulse to next pulse, drop-down moment open signal g_nesd closing ESD protector Part NESD.

2. N-type preemphasis circuit according to claim 1, it is characterised in that: phase inverter group includes three concatenated reverse phases Device.

3. a kind of p-type preemphasis circuit, it is characterised in that: including

Phase inverter group: delay process is carried out to input signal inp and obtains inversion signal inp_n_p；

NAND gate Nand1: handling input signal inp and inversion signal inp_n_p, obtains pull-up pulse signal emp_p, The width for pulling up pulse signal emp_p is equal to the sum of total delay of phase inverter；

And capacitor: pull-up pulse signal emp_p carries out processing and generates pull-up moment open signal g_pesd, when pull-up pulse signal When emp_p is low, pull-up moment open signal g_pesd opens ESD protective device PESD；Pull up the previous of pulse signal emp_p Failing edge section of the rising edge of a pulse to next pulse, pull-up moment open signal g_pesd closing ESD protective device PESD。

4. p-type preemphasis circuit according to claim 3, it is characterised in that: phase inverter group includes three concatenated reverse phases Device.

5. a kind of high-speed interface circuit for realizing preemphasis using ESD protective device, it is characterised in that: including interface circuit, p-type Preemphasis circuit and N-type preemphasis circuit；P-type preemphasis circuit is for generating pull-up moment open signal g_pesd, N-type pre-add Heavy circuit can be realized in moment unlatching for generating drop-down moment open signal g_nesd, pull-up moment open signal g_pesd Draw ESD protective device PESD；Drop-down moment open signal g_nesd can be realized moment unlatching drop-down ESD protective device NESD.

6. a kind of high-speed interface circuit for being realized preemphasis using ESD protective device according to claim 5, feature are existed In: the p-type preemphasis circuit includes phase inverter group: carrying out delay process to input signal inp and obtains inversion signal inp_n_ p；

NAND gate Nand1: handling input signal inp and inversion signal inp_n_p, obtains pull-up pulse signal emp_p, The pulse width for pulling up pulse signal emp_p is equal to the sum of total delay of phase inverter；

With capacitor c_p: pull-up pulse signal emp_p carries out processing and generates pull-up moment open signal g_pesd, when pull-up pulse When signal emp_p is low, pull-up moment open signal g_pesd opens ESD protective device PESD；Pull up pulse signal emp_p's Failing edge section of the rising edge of previous pulse to next pulse, pull-up moment open signal g_pesd closing ESD protector Part PESD.

7. a kind of high-speed interface circuit for realizing preemphasis using ESD protective device according to claim 5 or 6, special Sign is: the N-type preemphasis circuit includes phase inverter group: carrying out delay process to input signal inp and obtains inversion signal inp_n_n；

Nor gate Nor1: input signal inp is handled with inversion signal inp_n_n, obtains drop-down pulse signal emp_n, under The pulse width of pulse signal emp_n is drawn to be equal to the sum of total delay of phase inverter；

Processing is carried out with capacitor c_n: drop-down pulse signal emp_n and generates drop-down moment open signal g_nesd, works as drop-down pulse When signal emp_n is high, drop-down moment open signal g_nesd opens ESD protective device NESD；Drop-down pulse signal emp_n's Rising edge section of the failing edge of previous pulse to next pulse, drop-down moment open signal g_nesd closing ESD protector Part NESD.