CN103607130B - Based on control method and the device thereof of the three level pulse expansion of the DSPACE of FPGA - Google Patents

Based on control method and the device thereof of the three level pulse expansion of the DSPACE of FPGA Download PDF

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CN103607130B
CN103607130B CN201310607703.6A CN201310607703A CN103607130B CN 103607130 B CN103607130 B CN 103607130B CN 201310607703 A CN201310607703 A CN 201310607703A CN 103607130 B CN103607130 B CN 103607130B
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pulse
pulse signal
fpga
level state
dspace
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CN201310607703.6A
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CN103607130A (en
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谭国俊
张传金
张晓�
张辉
王珂
李江成
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徐州中矿大传动与自动化有限公司
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Abstract

The invention discloses control method and the device thereof of the three level pulse expansion of a kind of DSPACE based on FPGA, be applicable to experiment and commercial Application.This pulse expansion device is made up of interface conversion circuit, pulse signal extension process unit, power supply circuit, photoelectric switching circuit.The impulse waveform of the DS5101 digit pulse board of DSPACE inputs to interface conversion circuit, pulse signal is sent into extension process unit by logic level coupling by interface conversion circuit, drives the pulse signal required to send into photoelectric switching circuit after pulse signals carries out necessary process by meeting.Utilize device of the present invention and control method, the expansion that the three level pulse of DSPACE is exported can be realized, overcome its intrinsic cannot output duty cycle be 0% and 100% digit pulse defect, extend the field of DSPACE in three level medium voltage frequency converter experimental study and commercial Application, have a extensive future.

Description

Based on control method and the device thereof of the three level pulse expansion of the DSPACE of FPGA

Technical field

The present invention relates to control method and the device thereof of the three level pulse expansion of a kind of DSPACE based on FPGA, belong to electric and electronic technical field, be applicable to experiment and commercial Application.

Background technology

In recent years, along with the maturation of full control property power device production technology, select to adopt multilevel converter in increasing high-voltage high-power frequency transformator occasion, simultaneously the DSPACE advantage that realizes in control algolithm and upgrading has other controllers incomparable.Therefore, the advantage of DSPACE on algorithm realization how is utilized to become problem in the urgent need to address to the experiment research and development and commercial Application of carrying out high-power multi-level frequency conversion device.

At present; the expanded function adopting the DWO language of amendment DS5101 board to realize many level pulses more; but export because self intrinsic defect when its bottom DWO language performs cannot realize three-level pwm pulse accurately, work as power main loop when DS5101 being set to output mode simultaneously and break down and cannot make protection act to power device immediately.

Diode clamp formula three level main circuit diagram as shown in Figure 7, to adopt in DSPACE DWO language to DS5101 board control its export pulsed drive three level main circuit carry out work time, need the parametric t b1 and tb2 action time of a certain road pulse set in DWO language, wherein: tb1 indicating impulse high level action time, tb2 indicating impulse low level action time, all need to take certain clock cycle because every bar statement performs, therefore when set tb1=0 or tb1=Ts(Ts be switch periods) time cannot realize the pwm pulse waveform that output duty cycle is 0% and 100%, the waveform of three-level pwm pulse as shown in Fig. 5 (a) of final output, and the partial enlarged drawing that Fig. 5 (b) is Fig. 5 (a).

Analyze (for A phase) the operating state of the power device of the diode clamp formula three level main circuit shown in Fig. 7 below, in figure, the A phase brachium pontis of inverter has four power switch tube S a1, S a2, S a3, S a4, two clamping diode D a1, D a2with four sustained diode a3, D a4, D a5, D a6.Variable S arepresent the on off state of A phase brachium pontis:

1. if S a3, S a4turn off, S a1, S a2conducting, defining this state is 1 state S a=1, work as current i sfor on the occasion of time, electric current from power positive end P point through S a1, S a2flow into U point; Work as current i sduring for negative value, electric current from U point through D a3, D a4flow into P point.Therefore no matter i swhy be worth A point and all receive P point, therefore:

2. if S a1, S a4turn off, S a2, S a3conducting, defining this state is 0 state S a=0, work as current i sfor on the occasion of time, electric current from power positive end O point through D a1, S a2flow into U point; Work as current i sduring for negative value, electric current from U point through S a3, D a2flow into P point.Therefore no matter i swhy be worth A point and all receive O point, therefore: U u0=0.

3. if S a1, S a2turn off, S a3, S a4conducting, defines this state for-1 state S a=-1, work as current i sfor on the occasion of time, electric current from power supply negative terminal Q point through D a5, D a6flow into U point; Work as current i sduring for negative value, electric current from U point through S a3, S a4flow into Q point.Therefore no matter i swhy be worth A point and all receive Q point, therefore:

Therefore can find out for the effective on off state S of A phase brachium pontis three kinds a=0,1 ,-1 correspond to S respectively a1=0S a2=1S a3=1S a4=0, S a1=1S a2=1S a3=0S a4=0, S a1=0S a2=0S a3=1, S a4=1, DS5101 digital output board card output waveform is as shown in Fig. 5 (a), can find out from waveform Fig. 5 (a) Suo Shi and should should to keep permanent and turn off and all saltus step can occur under state that second power tube should keep perseverance to open by A phase first power tube in half power frequency period for a phase brachium pontis (for A phase), be not difficult to find by above-mentioned analysis, the DS5101 digit pulse output board card for DSPACE1005 makes it cannot directly apply on three-level converter due to himself language defect.

Summary of the invention

In order to overcome above-mentioned defect, the invention provides control method and the device thereof of the three level pulse expansion of a kind of DSPACE based on FPGA, making DSPACE control to become possibility at three level big-power transducer PWM, advancing the commercial Application of this structure.

The present invention in order to the technical scheme solving its technical problem and adopt is: the control method of the three level pulse expansion of a kind of DSPACE based on FPGA, and burst pulse is eliminated and is divided into two kinds of situations, and brachium pontis first is managed and brachium pontis second is managed, and step of its elimination is:

A, a phase brachium pontis first pipe burst pulse process:

(1) FPGA sensitive event is set to system clock rising edge triggering mode, the system progress rapid 2 when FPGA detects system clock rising edge, when system clock for system under other states enters step 5;

(2) present clock period first pipe pulse signal st1 is judged nwhether be high level state and a upper clock cycle first pipe pulse signal st1 n-1whether be low level state, when meeting st1 in a certain system clock cycle simultaneously nfor high level state, st1 n-1for low level state enters step 3, work as st1 n, st1 n-1for other combined electrical level states enter step 5;

(3) judge that duty ratio perseverance that present clock period DS5101 exports is the reference burst signal stc0 of 0% nwhether be high level state, work as stc0 nfor high level state enters step 4, work as stc0 nfor low level state enters step 5;

(4) the first pipe pulse signal is dragged down as low level, eliminate the high level burst pulse that duty ratio is the pulse signal of 0%;

(5) the first pipe pulse signal is exported;

B, a phase brachium pontis second pipe burst pulse process:

(1) FPGA sensitive event is set to system clock rising edge triggering mode, the system progress rapid 2 when FPGA detects system clock rising edge, when system clock for system under other states enters step 5;

(2) present clock period second pipe pulse signal st2 is judged nwhether be low level state and a upper clock cycle second pipe pulse signal st2 n-1whether be high level state, when meeting st2 in a certain system clock cycle simultaneously nfor low level state, st2 n-1for high level state enters step 3, work as st2 n, st2 n-1for other combined electrical level states enter step 5;

(3) judge that duty ratio that present clock period DS5101 exports is the reference burst signal stc100 of 100% nwhether be low level state, work as stc100 nfor low level state enters step 4, work as stc100 nfor high level state enters step 5;

(4) the second pipe pulse signal is drawn high as high level, eliminate the low level burst pulse that duty ratio is the pulse signal of 100%;

(5) the second pipe pulse signal is exported.

Based on a control device for the three level pulse expansion of the DSPACE of FPGA, comprise interface conversion circuit, pulse signal processing unit, power supply circuit, drive circuit based on FPGA; The impulse waveform of the DS5101 digit pulse board of DSPACE inputs to interface conversion circuit, interface conversion circuit mates the pulse signal processing unit of pulse signal feeding based on FPGA by logic level, drive the pulse signal required to send into drive circuit by meeting after pulse signals carries out necessary process, power supply circuit provides power supply to the pulse signal processing unit based on FPGA.

The described pulse signal processing unit based on FPGA is eliminated unit, the dead time unit and power model protected location by burst pulse and is formed; pulse signal eliminates unit via burst pulse makes pulse duty factor reach 0% and 100%; then added the dead band of protection power model by the dead time unit, send finally by power model protected location.

The invention has the beneficial effects as follows: the present invention is perfect DSPACE three-level pwm pulse output function; the basis of amendment DWO language realizes the accurate output of three-level pwm pulse and the protection of power device; make DSPACE be applied to three level high-voltage big-power transducer experimental study and Industry Control becomes possibility, improve simultaneously the shortest protection of the protective capability of DSPACE control system to power device response time≤2us.To realizing, the application of DSPACE in many level Large Powers Frequency Converter Control is significant.

Accompanying drawing explanation

Fig. 1 is the schematic diagram of device of the three level pulse expansion of the DSPACE that the present invention is based on FPGA;

Fig. 2 is the FPGA burst pulse process chart of A/B/C brachium pontis one pipe;

Fig. 3 is the FPGA burst pulse process chart of A/B/C brachium pontis two pipe;

Fig. 4 is the impulse waveform key diagram of Fig. 2 and Fig. 3;

Fig. 5 (a) is the output waveform figure of existing diode clamp formula three level;

The partial enlarged drawing that Fig. 5 (b) is Fig. 5 (a);

Fig. 6 (a) is the oscillogram after improvement;

The partial enlarged drawing that Fig. 6 (b) is Fig. 6 (a);

Fig. 7 is existing diode clamp formula three level main circuit diagram.

Embodiment

Embodiment

As shown in Figures 1 to 7, the control device of the three level pulse expansion of a kind of DSPACE based on FPGA, comprises interface conversion circuit 10, the pulse signal processing unit 20 based on FPGA, power supply circuit 30, drive circuit 40; The impulse waveform of the DS5101 digit pulse board of DSPACE inputs to interface conversion circuit 10, interface conversion circuit 10 mates the pulse signal processing unit 20 of pulse signal feeding based on FPGA by logic level, drive the pulse signal required to send into drive circuit 40 by meeting after pulse signals carries out necessary process, power supply circuit 30 provides power supply to the pulse signal processing unit 20 based on FPGA.

The described pulse signal processing unit 20 based on FPGA is eliminated unit, the dead time unit and power model protected location by burst pulse and is formed; pulse signal eliminates unit via burst pulse makes pulse duty factor reach 0% and 100%; then added the dead band of protection power model by the dead time unit, send finally by power model protected location.

Based on a control method for the three level pulse expansion of the DSPACE of FPGA, burst pulse is eliminated and is divided into two kinds of situations, and brachium pontis first is managed and brachium pontis second is managed, and its step eliminated is:

A, a phase brachium pontis first pipe burst pulse process:

(1) FPGA sensitive event is set to system clock rising edge triggering mode, the system progress rapid 2 when FPGA detects system clock rising edge, when system clock for system under other states enters step 5;

(2) present clock period first pipe pulse signal st1 is judged nwhether be high level state and a upper clock cycle first pipe pulse signal st1 n-1whether be low level state, when meeting st1 in a certain system clock cycle simultaneously nfor high level state, st1 n-1for low level state enters step 3, work as st1 n, st1 n-1for other combined electrical level states enter step 5;

(3) judge that duty ratio perseverance that present clock period DS5101 exports is the reference burst signal stc0 of 0% nwhether be high level state, work as stc0 nfor high level state enters step 4, work as stc0 nfor low level state enters step 5;

(4) the first pipe pulse signal is dragged down as low level, eliminate the high level burst pulse that duty ratio is the pulse signal of 0%;

(5) the first pipe pulse signal is exported;

B, a phase brachium pontis second pipe burst pulse process:

(1) FPGA sensitive event is set to system clock rising edge triggering mode, the system progress rapid 2 when FPGA detects system clock rising edge, when system clock for system under other states enters step 5;

(2) present clock period second pipe pulse signal st2 is judged nwhether be low level state and a upper clock cycle second pipe pulse signal st2 n-1whether be high level state, when meeting st2 in a certain system clock cycle simultaneously nfor low level state, st2 n-1for high level state enters step 3, work as st2 n, st2 n-1for other combined electrical level states enter step 5;

(3) judge that duty ratio that present clock period DS5101 exports is the reference burst signal stc100 of 100% nwhether be low level state, work as stc100 nfor low level state enters step 4, work as stc100 nfor high level state enters step 5;

(4) the second pipe pulse signal is drawn high as high level, eliminate the low level burst pulse that duty ratio is the pulse signal of 100%;

(5) the second pipe pulse signal is exported.

Claims (2)

1. based on a control method for the three level pulse expansion of the DSPACE of FPGA, it is characterized in that: burst pulse is eliminated and is divided into two kinds of situations, and brachium pontis first is managed and brachium pontis second is managed, and its step eliminated is:
A, a phase brachium pontis first pipe burst pulse process:
(1) FPGA sensitive event is set to system clock rising edge triggering mode, when FPGA detects system clock rising edge, system enters step 2, when system clock for system under other states enters step 5;
(2) present clock period first pipe pulse signal st1 is judged nwhether be high level state and a upper clock cycle first pipe pulse signal st1 n-1whether be low level state, when meeting st1 in a certain system clock cycle simultaneously nfor high level state, st1 n-1for low level state enters step 3, work as st1 n, st1 n-1for other combined electrical level states enter step 5;
(3) judge that duty ratio perseverance that present clock period DS5101 exports is the reference burst signal stc0 of 0% nwhether be high level state, work as stc0 nfor high level state enters step 4, work as stc0 nfor low level state enters step 5;
(4) the first pipe pulse signal is dragged down as low level, eliminate the high level burst pulse that duty ratio is the pulse signal of 0%;
(5) the first pipe pulse signal is exported;
B, a phase brachium pontis second pipe burst pulse process:
(1) FPGA sensitive event is set to system clock rising edge triggering mode, when FPGA detects system clock rising edge, system enters step 2, when system clock for system under other states enters step 5;
(2) present clock period second pipe pulse signal st2 is judged nwhether be low level state and a upper clock cycle second pipe pulse signal st2 n-1whether be high level state, when meeting st2 in a certain system clock cycle simultaneously nfor low level state, st2 n-1for high level state enters step 3, work as st2 n, st2 n-1for other combined electrical level states enter step 5;
(3) judge that duty ratio that present clock period DS5101 exports is the reference burst signal stc100 of 100% nwhether be low level state, work as stc100 nfor low level state enters step 4, work as stc100 nfor high level state enters step 5;
(4) the second pipe pulse signal is drawn high as high level, eliminate the low level burst pulse that duty ratio is the pulse signal of 100%;
(5) the second pipe pulse signal is exported.
2. based on a control device for the three level pulse expansion of the DSPACE of FPGA, it is characterized in that: comprise interface conversion circuit (10), the pulse signal processing unit (20) based on FPGA, power supply circuit (30), drive circuit (40); The impulse waveform of the DS5101 digit pulse board of DSPACE inputs to interface conversion circuit (10), interface conversion circuit (10) mates the pulse signal processing unit (20) of pulse signal feeding based on FPGA by logic level, drive the pulse signal required to send into drive circuit (40) by meeting after pulse signals carries out necessary process, power supply circuit (30) provides power supply to the pulse signal processing unit (20) based on FPGA; The described pulse signal processing unit (20) based on FPGA is eliminated unit, the dead time unit and power model protected location by burst pulse and is formed; pulse signal eliminates unit via burst pulse makes pulse duty factor reach 0% and 100%; then added the dead band of protection power model by the dead time unit, send finally by power model protected location.
CN201310607703.6A 2013-11-26 2013-11-26 Based on control method and the device thereof of the three level pulse expansion of the DSPACE of FPGA CN103607130B (en)

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US10175347B2 (en) 2015-12-02 2019-01-08 Butterfly Network, Inc. Ultrasound receiver circuitry and related apparatus and methods
US9492144B1 (en) 2015-12-02 2016-11-15 Butterfly Network, Inc. Multi-level pulser and related apparatus and methods
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US10082488B2 (en) * 2015-12-02 2018-09-25 Butterfly Network, Inc. Time gain compensation circuit and related apparatus and methods
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