CN205912035U - High voltage drive circuit's filter circuit and high voltage drive circuit - Google Patents
High voltage drive circuit's filter circuit and high voltage drive circuit Download PDFInfo
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- CN205912035U CN205912035U CN201620477571.9U CN201620477571U CN205912035U CN 205912035 U CN205912035 U CN 205912035U CN 201620477571 U CN201620477571 U CN 201620477571U CN 205912035 U CN205912035 U CN 205912035U
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Abstract
The utility model discloses a high voltage drive circuit's filter circuit and high voltage drive circuit. This filter circuit includes: first phase inverter is received first level shift signal and is exported first opposition signal, the second phase inverter is received second level shift signal and is exported second opposition signal, first time delay filter circuit receives first opposition signal and second opposition signal respectively, exports the short delay signal of first short delay signal and second, second time delay filter circuit receives second opposition signal and first opposition signal respectively, exports first long delay signal and the long delay signal of second, first short delay signal and first long delay signal are received to first NOR gate, export first or non - signal, short delay signal of second and the long delay signal of second, output second or non - signal are received to the second NOR gate. This filter circuit can improve the filtering capacity of differential mode noise in filtering common mode noise, improve noise filtering efficiency.
Description
Technical field
This utility model is related to high voltage integrated circuit field, the digital analog mixed filter more particularly, in high voltage integrated circuit
Wave technology is and in particular to a kind of filter circuit of high-voltage driving circuit and high-voltage driving circuit.
Background technology
High voltage integrated circuit (hvic) is the work(such as a kind of various protection circuits of band, low-voltage control circuit, high voltage power device
The gate driver circuit of energy, power electronics is combined by it with semiconductor technology, significantly improves integrated level and the stability of whole machine,
Have the advantages that integration density height, small volume, speed are fast, low in energy consumption, gradually replace traditional discrete device, more and more quilt
Apply in mosfet (metal-oxide-semiconductor or field-effect transistor, metal-oxide
Layer-quasiconductor-field-effect transistor), (insulated gate bipolar transistor, insulated gate bipolar is brilliant for igbt
Body pipe) driving field.Wherein, high voltage integrated circuit can be divided into low-pressure area and higher-pressure region, and low-pressure area power supply adopts externally fed,
Higher-pressure region power supply is using bootstrapping power supply.
As shown in figure 1, existing high-voltage driving circuit includes narrow pulse signal generation circuit, the level shift that order is connected
Circuit, level shift circuit, filter circuit and rs trigger.Original burst signal x of 0-15v inputs and produces to narrow pulse signal
Circuit, narrow pulse signal produces the rising that circuit produces 0-15v respectively respectively in the rising edge of original burst signal x, trailing edge
Along narrow pulse signal on and trailing edge narrow pulse signal off.Level shift circuit 0-15v to rising edge narrow pulse signal on and
Trailing edge narrow pulse signal off carries out electrical level shift processing, produces level offset signal c and the level shift letter of 600v-615v
Number d, is sent to the higher-pressure region of high voltage integrated circuit；By rs trigger by the level offset signal c of 600v-615v and level shift
Signal d process, is reduced into reduction pulse letter consistent with original burst signal x phase place and waveform but that voltage range is inconsistent
Number q1, to realize the driving to higher-pressure region mosfet or igbt.
It is to be appreciated that level shift circuit be used for by same chip by the narrow pulse signal on of 0-15v over the ground and
Off changes level offset signal c and d of 600v-615v in couples, to realize the driving to higher-pressure region mosfet or igbt.Can
With understand ground, narrow pulse signal on and off when level shift circuit, because environmental effect and technique productions difference may be produced
Raw common mold noise interference and differential mode noise interference, noise jamming is combined into reduction letter in level offset signal c and d through rs trigger
During number q1 output, the signal of chip system can be caused chaotic, the chip system applying this high-voltage driving circuit is caused to damage.Cause
This, for guaranteeing the accuracy of signal transmission, need to arrange filter circuit between potential shift circuit and rs trigger, for by electricity
In translational shifting circuit, the common-mode noise producing and differential mode noise filter.
As shown in figure 1, existing filter circuit includes two one-level inverter circuits, two two pole inverter circuits and two
OR-NOT circuit；Wherein, two pole inverter circuits are in series by two one-level inverter circuits.Level offset signal c is through one
Level inverter circuit processes and obtains inversion signal j, processes through two grades of inverter circuits and obtains inversion signal f.Level offset signal d
Process through one-level inverter circuit and obtain inversion signal e, process through two grades of inverter circuits and obtain inversion signal f.Inversion signal e
Carry out through OR-NOT circuit with f or non-process after formed or non-signal s1 exporting to the s end of rs trigger.Inversion signal g and j
Carry out through OR-NOT circuit or non-process after formed or non-signal r1 exporting to the r end of rs trigger.Rs trigger to or non-
Signal s1 and r1 is reduced, and exports recovering signal q1 from the q end of rs trigger.
Existing filter circuit is made up of the inverter circuit of different threshold values and OR-NOT circuit, in level shift circuit
When nmos pipe n1 and nmos pipe n2 on or off, because the mos pipe turn-off speed of level shift circuit is generally slow, but
Opening speed but switching characteristic quickly, causes rising edge narrow pulse signal on and trailing edge narrow pulse signal off in transmission,
Flip-flop transition is longer, and the waveform slope of rising edge narrow pulse signal on and trailing edge narrow pulse signal off is less, now utilizes anti-
The different turn threshold of phase device circuit, makes the output waveform of inverter circuit have a little time difference, this time difference is this
The differential mode of filter circuit filters ability.Fig. 2 is the signal logic figure of existing filter circuit, and the differential mode of this filter circuit filters ability
It is limited to the upset waveform slope impact of level shifting circuit, mos pipe upset slope is big, and this filter circuit differential mode filters ability
Weak, on the contrary then strong.
Existing filter circuit is mainly made up of inverter circuit and OR-NOT circuit, be can be very good by OR-NOT circuit
Filtering common mode noise；For differential mode noise, the level offset signal c and level offset signal d of level shift circuit output have relatively
The rising edge of little slope and trailing edge, the response time of the turn threshold of different inverter circuits is different, and this time difference is exactly
It filters the capacity of water of differential mode.In level shift circuit, the turn-off speed of nmos pipe n1 and nmos pipe n2 is slower, and opens speed
Degree very fast so that between different turn threshold inverter circuit response time difference less, thus very little can only be produced not even
Differential mode can be produced and filter the time.If it is to be appreciated that nmos pipe n1 and nmos pipe n2 can not filter differential mode in quick unlatching
Noise, thus impact to the driving of mosfet or igbt to high-voltage driving circuit.
Utility model content
The technical problems to be solved in the utility model is, for the differential mode filter of the filter circuit of existing high-voltage driving circuit
Wave energy power is limited to the switching speed of the mos pipe of level shift circuit, provides a kind of filter circuit of high-voltage driving circuit and height
Pressure drive circuit.
This utility model solves its technical problem and be the technical scheme is that a kind of filtered electrical of high-voltage driving circuit
Road, including the first phase inverter, the second phase inverter, the first filtering wave by prolonging time circuit, the second filtering wave by prolonging time circuit, the first nor gate and
Two nor gates；
Described first phase inverter is used for carrying out anti-phase process to the first level offset signal receiving, and it is anti-to export first
Phase signals；
Described second phase inverter is used for carrying out anti-phase process to the second electrical level shift signal receiving, and it is anti-to export second
Phase signals；
Described first filtering wave by prolonging time circuit be used for receive described first inversion signal processed short to export first
Time delayed signal；And described second inversion signal receiving is processed to export the second short time delayed signal；
Described second filtering wave by prolonging time circuit is used for growing to export first to receiving described second inversion signal and being processed
Time delayed signal；And described first inversion signal receiving is processed to export the second long delay signal；
Described first nor gate is used for the described first short time delayed signal receiving and described first long delay signal are entered
Row or non-process, to export first or non-signal；
Described second nor gate is used for the described second short time delayed signal receiving and described second long delay signal are entered
Row or non-process, to export second or non-signal.
Preferably, described first filtering wave by prolonging time circuit includes a rc time delay branch road and the first inverting branch；
Described second filtering wave by prolonging time circuit includes the 2nd rc time delay branch road and the second inverting branch；
Described first inverting branch and described second inverting branch cooperation, so that first after the first inversion signal is processed is short
Time delayed signal and the first long delay signal inversion, and so that the second short time delayed signal after the second inversion signal process and the second length is prolonged
When signal inversion.
Preferably, a described rc time delay branch road includes the first time delay pmos pipe, the first time delay nmos pipe, the first time delay electricity
Resistance and the first delay capacitor；The grid of described first time delay pmos pipe and described first time delay nmos pipe connects signal input respectively
End, drain electrode is connected to the two ends of described first time delay resistance；The drain electrode of the first time delay pmos pipe and described first time delay electricity
The indirect signal output part of resistance；Described first delay capacitor one end is connected to the drain electrode of described first time delay pmos pipe and described the
Between one time delay resistance, the other end is grounded.
Preferably, described 2nd rc time delay branch road includes the second time delay pmos pipe, the second time delay nmos pipe, the second time delay electricity
Resistance and the second delay capacitor；The grid of described second time delay pmos pipe and described second time delay nmos pipe connects signal input respectively
End, drain electrode is connected to the two ends of described second time delay resistance；The drain electrode of the second time delay nmos pipe and described second time delay electricity
The indirect signal output part of resistance；Described second delay capacitor one end is connected to described second time delay nmos pipe and described second time delay
Between resistance, the other end is grounded.
Preferably, described first inverting branch includes one-level phase inverter, and described second inverting branch includes two grades of phase inverters；
Or, described first inverting branch includes two grades of phase inverters, and described second inverting branch includes one-level phase inverter；
Wherein, described two grades of phase inverters include the two described one-level phase inverters connected, each described one-level phase inverter bag
Include an anti-phase pmos pipe and an anti-phase nmos pipe, it is defeated that described anti-phase pmos pipe and the grid of described anti-phase nmos pipe connect signal respectively
Enter end, drain electrode connects signal output part respectively.
This utility model also provides a kind of high-voltage driving circuit, including narrow pulse signal produce circuit, level shift circuit,
Described filter circuit and rs trigger；
Described narrow pulse signal produces circuit and is used for receiving original burst signal, and export rising edge narrow pulse signal and under
Fall is along narrow pulse signal；
Described level shift circuit is used for carrying out electrical level shift processing to described rising edge narrow pulse signal, described to be formed
First level offset signal；And for electrical level shift processing being carried out to described trailing edge narrow pulse signal, to form described second
Level offset signal；
Described rs trigger includes s end, r end and q end；Described s end is used for receiving described first or non-signal, described r end
For receiving described second or non-signal, described q end is used for exporting described original burst signal corresponding reduction pulse signal.
Preferably, described level shift circuit includes the first displacement branch road and the second displacement branch road；
Described first displacement branch road includes the first displacement nmos pipe, the first displacement resistance and the first clamp diode；Described
The grid of the first displacement nmos pipe produces circuit with described narrow pulse signal and is connected, and drain electrode is connected with the described first displacement resistance,
Source electrode connects common port；Described first clamp diode and described first displacement resistor coupled in parallel；
Described second displacement branch road includes the second displacement nmos pipe, the second displacement resistance and the second clamp diode；Described
The grid of the second displacement nmos pipe produces circuit with described narrow pulse signal and is connected, and drain electrode is connected with the described second displacement resistance,
Source electrode connects common port；Described second clamp diode and described second displacement resistor coupled in parallel.
Preferably, described high-voltage driving circuit also includes the current amplification circuit being connected with described rs trigger.
Preferably, described current amplification circuit includes the 3rd phase inverter, the first amplification nmos pipe and second amplifies nmos pipe；
The input of described 3rd phase inverter is connected with the q end of described rs trigger, the grid that outfan amplifies nmos pipe with described second
Extremely connected；The source electrode of described second amplification nmos pipe connects electronegative potential feed end vs, the source that drain electrode amplifies nmos pipe with described first
Extremely connected；The grid of described first amplification nmos pipe is connected with the q end of described rs trigger, and drain electrode meets high potential feed end vb.
This utility model compared with prior art has the advantage that filter circuit provided by the utility model can produce
The differential mode noise of one determination filters the time, is not affected by mos pipe switching speed in level shift circuit, has accurate differential mode to make an uproar
Sound filters ability, can the differential mode noise in filtering common mode noise forward position and the difference of common-mode noise tailing edge while filtering common mode noise
Mode noise, substantially improves the ability that filters of differential mode noise, improves noise filtering efficiency, prevents noise jamming from leading to circuit logic
Cisco unity malfunction.
Brief description
Below in conjunction with drawings and Examples, the utility model is described in further detail, in accompanying drawing:
Fig. 1 is the circuit theory diagrams of existing high-voltage driving circuit.
Fig. 2 is the signal logic figure of existing high-voltage driving circuit.
Fig. 3 is the circuit theory diagrams of the high-voltage driving circuit in this utility model one embodiment.
Fig. 4 is the signal logic figure of the high-voltage driving circuit in this utility model one embodiment.
Fig. 5 is the circuit theory diagrams of the first filtering wave by prolonging time circuit in this utility model one embodiment.
Fig. 6 is the circuit theory diagrams of the second filtering wave by prolonging time circuit in this utility model one embodiment.
In figure: 10, narrow pulse signal produces circuit；20th, level shift circuit；30th, filter circuit；31st, the first phase inverter；
32nd, the second phase inverter；33rd, the first filtering wave by prolonging time circuit；331st, a rc time delay branch road；332nd, the first inverting branch；34th, second
Filtering wave by prolonging time circuit；341st, the 2nd rc time delay branch road；342nd, the second inverting branch；35th, the first nor gate；36th, the second nor gate；
40th, rs trigger；50th, current amplification circuit；51st, the 3rd phase inverter.
Specific embodiment
In order to be more clearly understood to technical characteristic of the present utility model, purpose and effect, now comparison accompanying drawing is detailed
Specific embodiment of the present utility model is described.
Fig. 3 and Fig. 4 is shown respectively high-voltage driving circuit circuit theory diagrams and signal logic figure in the present embodiment.This high pressure
Drive circuit includes narrow pulse signal and produces circuit 10, level shift circuit 20, filter circuit 30 and rs trigger 40 and electric current
Amplifying circuit 50.
The input that narrow pulse signal produces circuit 10 is used for receiving original burst signal x of 0-15v, former in 0-15v
The rising edge of initial pulse signal x and trailing edge produce rising edge narrow pulse signal on and trailing edge narrow pulse signal off respectively, and
Rising edge narrow pulse signal on and trailing edge narrow pulse signal off is exported by the outfan being connected with level shift circuit 20.
Level shift circuit 20 is used for carrying out electrical level shift processing to rising edge narrow pulse signal on, to form the first level
Shift signal c；And for electrical level shift processing being carried out to trailing edge narrow pulse signal off, to form second electrical level shift signal
d.It is to be appreciated that level shift circuit 20 is used for the rising edge narrow pulse signal on of 0-15v and trailing edge narrow pulse signal
Off is converted into the first level offset signal c and second electrical level shift signal d of 600-615v respectively.It is to be appreciated that in level
During shift circuit 20 carries out electrical level shift processing to rising edge narrow pulse signal on and trailing edge narrow pulse signal off, by
Common mold noise interference and differential mode noise interference may be produced in environmental effect and technique productions difference.
As shown in figure 1, level shift circuit 20 is included for carrying out electrical level shift processing to rising edge narrow pulse signal on
To form the first displacement branch road of the first level offset signal c and to be used for carrying out level shift to trailing edge narrow pulse signal off
Process the second displacement branch road to form second electrical level shift signal d.
First displacement branch road includes the first displacement nmos pipe n21, the first displacement resistance r21 and the first clamp diode d21.
The outfan that the grid of the first displacement nmos pipe n21 produces circuit 10 with narrow pulse signal is connected, narrow for receiving rising edge
Pulse signal on；The drain electrode of the first displacement nmos pipe n21 is connected with the first displacement resistance r21, the source of the first displacement nmos pipe n21
Pole meets common port com.Wherein, the other end of the first displacement resistance r21 is connected with high potential feed end vb.It is to be appreciated that working as
When rising edge narrow pulse signal on controls the first displacement nmos pipe n21 conducting, the first displacement resistance r21 and first shifts nmos pipe
The magnitude of voltage of one end that n21 is connected is pulled low to the magnitude of voltage of common port com by the magnitude of voltage at vb end, and exports the first level shifting
Position signal c, to realize the conversion of the first level offset signal c of rising edge narrow pulse signal on to the 600v-615v of 0-15v.
Due to first displacement nmos pipe n21 switching characteristic so that the first level offset signal c is with respect to rising edge narrow pulse signal
On overturns, and has rising edge and the trailing edge of certain slope.Now, the first level offset signal c and rising edge burst pulse are believed
The opposite in phase of number on, waveform is inconsistent and its voltage range is inconsistent.Wherein, the first clamp diode d21 and first displacement
Resistance r21 is in parallel, to ensure the magnitude of voltage of the first level offset signal c in preset range, such as 600v-615v.
Second displacement branch road includes the second displacement nmos pipe n22, the second displacement resistance r22 and the second clamp diode d22.
Another outfan that the grid of the second displacement nmos pipe n22 produces circuit 10 with narrow pulse signal is connected, for receiving trailing edge
Narrow pulse signal off；The drain electrode of the second displacement nmos pipe n22 is connected with the second displacement resistance r22；Second displacement nmos pipe n22
Source electrode meet common port com.Wherein, the other end of the second displacement resistance r22 is connected with high potential feed end vb.It is appreciated that
Ground, when trailing edge narrow pulse signal off controls the second displacement nmos pipe n22 conducting, second shifts resistance r22 and second displacement
The magnitude of voltage of one end that nmos pipe n22 is connected is pulled up to the magnitude of voltage at vb end by the magnitude of voltage of common port com, and exports second
Level offset signal d, to realize the second electrical level shift signal d of trailing edge narrow pulse signal off to the 600v-615v of 0-15v
Conversion.Because the switching characteristic of the second displacement nmos pipe n22 is so that second electrical level shift signal d is with respect to the narrow arteries and veins of trailing edge
Rush signal off upset, and there is rising edge and the trailing edge of certain slope.Now, second electrical level shift signal d is narrow with trailing edge
Pulse signal off opposite in phase, waveform are inconsistent and its voltage range is inconsistent.Wherein, the second clamp diode d22 and second
Displacement resistance r22 is in parallel, to ensure the magnitude of voltage of second electrical level shift signal d in preset range, such as 600v-615v.
As shown in figure 3, filter circuit 30 include the first phase inverter 31, the second phase inverter 32, the first filtering wave by prolonging time circuit 33,
Second filtering wave by prolonging time circuit 34, the first nor gate 35 and the second nor gate 36.It is to be appreciated that filter circuit 30 is used for filtering
Rise along narrow pulse signal on level shift to the first level offset signal c or trailing edge narrow pulse signal off level shift to the
The common-mode noise producing during two level offset signal d and differential mode noise.This common-mode noise and differential mode noise are due to the first shifting
Position nmos pipe n21 or second displacement nmos pipe n22 turn-off speed is slow and opening speed is fast, rising edge narrow pulse signal on or under
, along along narrow pulse signal off transmittance process, flip-flop transition is longer, the first level offset signal c and second electrical level shift signal d for fall
Rising edge and trailing edge waveform slope less, differential mode filter ability poor and produce.
First phase inverter 31 is used for carrying out anti-phase process (i.e. upset process) to the first level offset signal c receiving,
Obtain with the first level offset signal c opposite in phase and the first consistent inversion signal k of voltage range exporting.Specifically,
One phase inverter 31 is connected with one first filtering wave by prolonging time circuit 33 and one second filtering wave by prolonging time circuit 34 respectively, and the first level is moved
The position corresponding first inversion signal k of signal c is separately input into the first filtering wave by prolonging time circuit 33 and the second filtering wave by prolonging time circuit 34 enters
Line delay Filtering Processing, to obtain the first short time delayed signal n and the second long delay signal m.
Second phase inverter 32 is used for carrying out anti-phase process (i.e. upset process) to the second electrical level shift signal d receiving,
Obtain with second electrical level shift signal d opposite in phase and the second consistent inversion signal l of voltage range exporting.Specifically,
Two phase inverters 32 are connected with one first filtering wave by prolonging time circuit 33 and one second filtering wave by prolonging time circuit 34 respectively, and second electrical level is moved
The position corresponding second inversion signal l of signal d is separately input into the first filtering wave by prolonging time circuit 33 and the second filtering wave by prolonging time circuit 34 enters
Line delay Filtering Processing, to obtain the second short time delayed signal i and the first long delay signal h.
One input of the first filtering wave by prolonging time circuit 33 is connected with the first phase inverter 31, for anti-phase to first receiving
Signal k is processed to export the first short time delayed signal n.In the present embodiment, the first inversion signal k and the first short time delayed signal n
Opposite in phase, voltage range are consistent, and the trailing edge of the first short time delayed signal n lags behind the rising edge of the first inversion signal k.
Another input of the first filtering wave by prolonging time circuit 33 is connected with the second phase inverter 32, for anti-to second receiving
Phase signals l are processed to export the second short time delayed signal i.In the present embodiment, the second inversion signal l and the second short time delayed signal
The opposite in phase of i, voltage range are consistent, and the trailing edge of the second short time delayed signal i lags behind the rising of the second inversion signal l
Edge.
One input of the second filtering wave by prolonging time circuit 34 is connected with the first phase inverter 31, for anti-phase to first receiving
Signal k is processed to export the second long delay signal m.In the present embodiment, the second inversion signal l and the second long delay signal m
Phase place is identical, voltage range is consistent, and the trailing edge of the second long delay signal m lags behind the trailing edge of the first inversion signal k.
Another input of the second filtering wave by prolonging time circuit 34 is connected with the second phase inverter 32, and second for being docked to is anti-phase
Signal l is processed to export the first long delay signal h.In the present embodiment, the second inversion signal l and the first long delay signal h
Phase place is identical, voltage range is consistent, and the trailing edge of the first long delay signal h lags behind the trailing edge of the second inversion signal l.
First nor gate 35 is used for first receiving short time delayed signal n and the first long delay signal h is carried out or non-place
Reason, to export first or non-signal s2.It is to be appreciated that the first inversion signal k is processed through the first filtering wave by prolonging time circuit 33
To the first short time delayed signal n, the second inversion signal l obtains the first long delay through the second filtering wave by prolonging time circuit 34 process process to be believed
Number h.Wherein, the first short time delayed signal n and the first long delay signal h opposite in phase, voltage range are consistent, and the first short time delay letter
The trailing edge of number n lags behind the rising edge of the first long delay signal h, and it is short that the trailing edge of the first long delay signal h lags behind first
The rising edge of time delayed signal n.As shown in figure 4, the signal logic in figure weight of the first short time delayed signal n and the first long delay signal h
Folded part is common-mode noise；When common-mode noise produces, the rising edge of the first long delay signal h and the first short time delayed signal n
Trailing edge between (i.e. the forward position of common-mode noise), the rising edge of the first short time delayed signal n and the first long delay signal h decline
The time difference that between edge, (i.e. the tailing edge of common-mode noise) exists, as differential mode noise.First nor gate 35 is to the first short time delay letter
Number n and the first long delay signal h is carried out or non-process, and level shift circuit 20 is carried out electricity to rising edge narrow pulse signal on
In translational shifting processing procedure, the common-mode noise being formed and differential mode noise filter, to obtain first or non-signal s2.
Second nor gate 36 is used for second receiving short time delayed signal i and the second long delay signal m is carried out or non-place
Reason, to export second or non-signal r2.It is to be appreciated that the first inversion signal k is processed through the first filtering wave by prolonging time circuit 33
To the second short time delayed signal i, the second inversion signal l processes through the second filtering wave by prolonging time circuit 34 and obtains the second long delay signal m.
Wherein, the second short time delayed signal i is consistent with the second long delay signal m opposite in phase, voltage range, and the second short time delayed signal i
Trailing edge lag behind the rising edge of the second long delay signal m, the trailing edge of the second long delay signal m lags behind the second short time delay
The rising edge of signal i.As shown in figure 4, the second short time delayed signal i is overlapping with the signal logic in figure of the second long delay signal m
Part is common-mode noise；When common-mode noise produces, under the rising edge of the second long delay signal m and the second short time delayed signal i
Between fall edge between (i.e. the forward position of common-mode noise), the rising edge of the second short time delayed signal and the trailing edge of the second long delay signal
The time difference that (i.e. the tailing edge of common-mode noise) exists, as differential mode noise.Second nor gate 36 time delayed signal i short to second and
Two long delay signal m are carried out or non-process, and level shift circuit 20 is carried out level shift to trailing edge narrow pulse signal off
During formed common-mode noise and differential mode noise filter, to obtain second or non-signal r2.
As shown in figure 5, the first filtering wave by prolonging time circuit 33 includes a rc time delay branch road 331 and the first inverting branch connected
332.Wherein, a rc time delay branch road 331 includes the first time delay pmos pipe p31, the first time delay nmos pipe n31, the first time delay electricity
Resistance r31 and the first delay capacitor c31.It is defeated that the grid of the first time delay pmos pipe p31 and the first time delay nmos pipe n31 connects signal respectively
Enter to hold in, be respectively used to meet the first inversion signal k or the second inversion signal l.First time delay pmos pipe p31 and the first time delay nmos
The drain electrode of pipe n31 is connected to the two ends of the first time delay resistance r31.The drain electrode of the first time delay pmos pipe p31 and the first time delay
The indirect signal output part of resistance r31, is connected with the input of the first inverting branch 332.First delay capacitor c31 one end is even
It is connected between drain electrode and the first time delay resistance r31 of the first time delay pmos pipe p31, the other end is grounded.
As shown in figure 5, when signal input part in input high level signal, the first time delay pmos pipe p31 turn off and first
Time delay nmos pipe n31 turns on；First delay capacitor c31 passes through the first time delay resistance r31 and the first time delay nmos pipe n31 and discharges,
Signal flows through the first time delay nmos pipe n31, the first time delay resistance r31 and the first inverting branch 332 to signal output part out.When
During signal input part in input low level signal, the first time delay pmos pipe p31 turns on and the first time delay nmos pipe n31 turns off, the
One time delay pmos pipe p31 charges to the first delay capacitor c31, and signal flows through the first time delay pmos pipe p31 and the first inverting branch
332 to signal output part out.It is to be appreciated that the first time delay resistance r31 plays metering function, discharge in the first delay capacitor c31
When act the effect slowing down signal decrease speed, even if signal input part in input signal when low level-high level saltus step, make
Output rising edge time delay；And keep trailing edge and the signal from signal input part in input when high level-low transition
Trailing edge is consistent.
As shown in fig. 6, the second filtering wave by prolonging time circuit 34 includes the 2nd rc time delay branch road 341 and the second inverting branch connected
342.Wherein, the 2nd rc time delay branch road 341 includes the second time delay pmos pipe p32, the second time delay nmos pipe n32, the second time delay electricity
Resistance r32 and the second delay capacitor c32.It is defeated that the grid of the second time delay pmos pipe p32 and the second time delay nmos pipe n32 connects signal respectively
Enter to hold in, for receiving the first inversion signal k and the second inversion signal l；Second time delay pmos pipe p32 and the second time delay nmos pipe
The drain electrode of n32 is connected to the two ends of the second time delay resistance r32；The drain electrode of the second time delay nmos pipe n32 and the second time delay electricity
The indirect signal output part of resistance r32, is connected with the input of the second inverting branch 342.Second delay capacitor c32 one end connects
Between the second time delay nmos pipe n32 and the second time delay resistance r32, the other end is grounded.
As shown in fig. 6, when signal input part in input high level signal, the second time delay pmos pipe p32 turn off and second
Time delay nmos pipe n32 turns on；Second delay capacitor c32 passes through the second time delay nmos pipe n32 electric discharge, and signal flows through the second time delay
Nmos pipe n32 and the second inverting branch 342 are to signal output part out.When signal input part in input low level signal, second
Time delay pmos pipe p32 turns on and the second time delay nmos pipe n32 turns off；Second delay capacitor c32 pass through the second time delay resistance r32 and
Second time delay pmos pipe p32 charges, and signal flows through the second time delay pmos pipe p32, the second time delay resistance r32 and the second inverting branch
342 to signal output part out.It is to be appreciated that the second time delay resistance r32 plays metering function, charge in the second delay capacitor c32
When act the effect slowing down the signal rate of climb；Even if the signal of signal input part in input, when high level-low transition, makes
Output trailing edge time delay；And keep rising edge and the signal from signal input part in input when low level-high level saltus step
Rising edge is consistent.
It is to be appreciated that be provided with the first inverting branch 332 in the first filtering wave by prolonging time circuit 33, so that from a rc time delay
In branch road 331, the signal of output keeps steep in transmitting procedure, ensures the concordance of signal transmission timeliness in the entire system.?
It is provided with the second inverting branch 342, so that the signal of output exists from the 2nd rc time delay branch road 341 in second filtering wave by prolonging time circuit 34
Keep steep in transmitting procedure, ensure the concordance of signal transmission timeliness in the entire system.Wherein, the first inverting branch 332
Coordinate with the second inverting branch 342, the first short time delayed signal n after the first inversion signal k can be made to process and the first long delay are believed
Number h is anti-phase, so that the first short time delayed signal n and the first long delay signal h is carried out or non-process by the first nor gate 35
After can filter common-mode noise therein and differential mode noise.First inverting branch 332 and the cooperation of the second inverting branch 342, can make
The second short time delayed signal i after second inversion signal l process and the second long delay signal m is anti-phase, so that the second short time delay
Signal i and the second long delay signal m by the second nor gate 36 carry out or non-process after can filter common-mode noise therein and difference
Mode noise.
In the present embodiment, the first inverting branch 332 includes one-level phase inverter, the second inverting branch 342 include two grades anti-phase
Device, wherein, two grades of phase inverters include the two one-level phase inverters connected.It is to be appreciated that the first inverting branch 332 is provided with one-level
Phase inverter, and the second inverting branch 342 is provided with two one-level phase inverters of series connection so that through the first inverting branch 332 and second
Two signal phases after inverting branch 342 is processed are contrary.In the present embodiment, the first inversion signal k is through the first filtering wave by prolonging time electricity
The phase of the first short time delayed signal n after the process of road 33 and the second long delay signal m after the second filtering wave by prolonging time circuit 34 process
Position is contrary.Correspondingly, the second short time delayed signal i after the first filtering wave by prolonging time circuit 33 process for the second inversion signal l with through the
The opposite in phase of the first long delay signal h after two filtering wave by prolonging time circuit 34 process.It is to be appreciated that making first anti-phase
Branch road 332 includes two grades of phase inverters, and correspondingly, the second inverting branch 342 includes one-level phase inverter.
Specifically, each one-level phase inverter includes an an anti-phase pmos pipe p01 and anti-phase nmos pipe n01, anti-phase pmos
The grid of pipe p01 and anti-phase nmos pipe n01 connects signal input part respectively, and drain electrode connects signal output part respectively.Work as signal input part
During input high level signal, anti-phase pmos pipe p01 turns off and anti-phase nmos pipe n01 conducting；When signal input part input low level
During signal, anti-phase pmos pipe p01 turns on and anti-phase nmos pipe n01 turns off；Thus realizing anti-to the signal of signal input part input
Phase processor.
The differential mode noise that filter circuit 30 can produce a determination filters the time, is not subject to the first displacement in level shift circuit 20
The impact of nmos pipe n21 and second displacement nmos pipe n22 switching speed, has accurate differential mode noise to filter ability, is filtering altogether
While mode noise can the differential mode noise in filtering common mode noise forward position and the differential mode noise of common-mode noise tailing edge, substantially improve differential mode
Noise filter ability, improve noise filtering efficiency, prevent noise jamming from leading to circuit logic cisco unity malfunction.
Rs trigger 40 includes s end, r end and q end；Wherein, s end is connected with the first nor gate 35, for receiving described
One or non-signal s2；R end is connected with the second nor gate 36, and for receiving second or non-signal r2, q end is outfan, for defeated
Go out original burst signal x corresponding reduction pulse signal q2.It is to be appreciated that rs trigger 40 is used for receiving first or non-signal
S2 and second or non-signal r2, original burst signal x are reduced, obtain 600v- over the ground corresponding with original burst signal x
The clean reduction pulse signal q2 of 615v.Wherein, reduction pulse signal q2 is consistent with original burst signal x phase place, and waveform is consistent,
But voltage range is inconsistent；The voltage range of original burst signal x is 0-15v, and reducing pulse signal q2 is 600v-615v,
To drive mosfet or igbt.
Current amplification circuit 50 is connected with rs trigger 40, and the reduction pulse signal q2 for exporting to rs trigger 40 enters
Row signal processing and amplifying, with output driving mosfet or igbt.Specifically, current amplification circuit 50 include the 3rd phase inverter 51,
First amplifies nmos pipe n51 and second amplification nmos pipe n52.Wherein, the q of the input of the 3rd phase inverter 51 and rs trigger 40
End is connected, and outfan is connected with the grid of the second amplification nmos pipe n52.The source electrode of the second amplification nmos pipe n52 connects electronegative potential and supplies
Vs should be held, drain electrode is connected with the source electrode of the first amplification nmos pipe n51.The grid of the first amplification nmos pipe n51 and rs trigger 40
Q end be connected, drain electrode meet high potential feed end vb.It is to be appreciated that the circuit structure of the 3rd phase inverter 51 and one-level phase inverter
Circuit structure identical, including an an anti-phase pmos pipe p01 and anti-phase nmos pipe n01, anti-phase pmos pipe p01 and anti-phase nmos pipe
The grid of n01 connects signal input part respectively, and drain electrode connects signal output part respectively.
The operation principle of current amplification circuit 50 is as follows: when reducing pulse signal q2 for high level, the first amplification nmos
Pipe n51 turns on, and carries out current amplifying process to reduction pulse signal q2；The now reduction arteries and veins to high level for the 3rd phase inverter 51
Rush signal q2 and carry out anti-phase process to export low level so that second amplifies nmos pipe n52 shutoff.When reduction pulse signal q2 is
During low level, first amplifies nmos pipe n51 turns off；Now the 3rd phase inverter 51 is carried out instead to low level reduction pulse signal q2
Phase processor is to export high level so that second amplifies nmos pipe n52 conducting, and reduction pulse signal q2 is carried out at Current amplifier
Reason.
This utility model is illustrated by above-mentioned specific embodiment, it will be appreciated by those skilled in the art that, not
In the case of departing from this utility model scope, this utility model can also be carried out with various conversion and equivalent substitute.In addition, being directed to
Particular condition or concrete condition, can make various modifications, without deviating from scope of the present utility model to this utility model.Therefore,
This utility model is not limited to disclosed specific embodiment, and should include falling in this utility model right
All embodiments.
Claims (9)
1. a kind of filter circuit of high-voltage driving circuit is it is characterised in that including the first phase inverter, the second phase inverter, first prolonging
When filter circuit, the second filtering wave by prolonging time circuit, the first nor gate and the second nor gate；
Described first phase inverter is used for carrying out anti-phase process to the first level offset signal receiving, and exports the first anti-phase letter
Number；
Described second phase inverter is used for carrying out anti-phase process to the second electrical level shift signal receiving, and exports the second anti-phase letter
Number；
Described first filtering wave by prolonging time circuit is used for being processed to export the first short time delay to receiving described first inversion signal
Signal；And described second inversion signal receiving is processed to export the second short time delayed signal；
Described second filtering wave by prolonging time circuit is used for being processed to export the first long delay to receiving described second inversion signal
Signal；And described first inversion signal receiving is processed to export the second long delay signal；
Described first nor gate be used for the described first short time delayed signal receiving and described first long delay signal carried out or
Non-process, to export first or non-signal；
Described second nor gate be used for the described second short time delayed signal receiving and described second long delay signal carried out or
Non-process, to export second or non-signal.
2. the filter circuit of high-voltage driving circuit according to claim 1 is it is characterised in that described first filtering wave by prolonging time is electric
Road includes a rc time delay branch road and the first inverting branch；
Described second filtering wave by prolonging time circuit includes the 2nd rc time delay branch road and the second inverting branch；
Described first inverting branch and described second inverting branch cooperation, so that the first short time delay after the first inversion signal process
Signal and the first long delay signal inversion, and make the second short time delayed signal after the second inversion signal process and the second long delay
Signal inversion.
3. the filter circuit of high-voltage driving circuit according to claim 2 is it is characterised in that a described rc time delay branch road
Including the first time delay pmos pipe, the first time delay nmos pipe, the first time delay resistance and the first delay capacitor；Described first time delay pmos
The grid of pipe and described first time delay nmos pipe connects signal input part respectively, and drain electrode is connected to described first time delay resistance
Two ends；The drain electrode of the first time delay pmos pipe and the indirect signal output part of described first time delay resistance；Described first delay capacitor
One end is connected between drain electrode and described first time delay resistance of described first time delay pmos pipe, and the other end is grounded.
4. the filter circuit of high-voltage driving circuit according to claim 2 is it is characterised in that described 2nd rc time delay branch road
Including the second time delay pmos pipe, the second time delay nmos pipe, the second time delay resistance and the second delay capacitor；Described second time delay pmos
The grid of pipe and described second time delay nmos pipe connects signal input part respectively, and drain electrode is connected to described second time delay resistance
Two ends；The drain electrode of the second time delay nmos pipe and the indirect signal output part of described second time delay resistance；Described second delay capacitor
One end is connected between described second time delay nmos pipe and described second time delay resistance, and the other end is grounded.
5. the filter circuit of high-voltage driving circuit according to claim 2 is it is characterised in that described first inverting branch bag
Include one-level phase inverter, described second inverting branch includes two grades of phase inverters；
Or, described first inverting branch includes two grades of phase inverters, and described second inverting branch includes one-level phase inverter；
Wherein, described two grades of phase inverters include the two described one-level phase inverters connected, and each described one-level phase inverter includes one
Anti-phase pmos pipe and an anti-phase nmos pipe, the grid of described anti-phase pmos pipe and described anti-phase nmos pipe connects signal input respectively
End, drain electrode connects signal output part respectively.
6. a kind of high-voltage driving circuit is it is characterised in that include narrow pulse signal generation circuit, level shift circuit, right will
Ask filter circuit described in any one of 1-5 and rs trigger；
Described narrow pulse signal produces circuit and is used for receiving original burst signal, and exports rising edge narrow pulse signal and decline
Along narrow pulse signal；
Described level shift circuit is used for carrying out electrical level shift processing to described rising edge narrow pulse signal, to form described first
Level offset signal；And for electrical level shift processing being carried out to described trailing edge narrow pulse signal, to form described second electrical level
Shift signal；
Described rs trigger includes s end, r end and q end；Described s end is used for receiving described first or non-signal, and described r end is used for
Receive described second or non-signal, described q end is used for exporting described original burst signal corresponding reduction pulse signal.
7. high-voltage driving circuit according to claim 6 is it is characterised in that described level shift circuit includes the first displacement
Branch road and the second displacement branch road；
Described first displacement branch road includes the first displacement nmos pipe, the first displacement resistance and the first clamp diode；Described first
The grid of displacement nmos pipe produces circuit with described narrow pulse signal and is connected, and drain electrode is connected with the described first displacement resistance, source electrode
Connect common port；Described first clamp diode and described first displacement resistor coupled in parallel；
Described second displacement branch road includes the second displacement nmos pipe, the second displacement resistance and the second clamp diode；Described second
The grid of displacement nmos pipe produces circuit with described narrow pulse signal and is connected, and drain electrode is connected with the described second displacement resistance, source electrode
Connect common port；Described second clamp diode and described second displacement resistor coupled in parallel.
8. high-voltage driving circuit according to claim 6 it is characterised in that described high-voltage driving circuit also include with described
The current amplification circuit that rs trigger is connected.
9. high-voltage driving circuit according to claim 8 it is characterised in that described current amplification circuit to include the 3rd anti-phase
Device, the first amplification nmos pipe and second amplify nmos pipe；The input of described 3rd phase inverter and the q end phase of described rs trigger
Even, outfan is connected with the grid of the described second amplification nmos pipe；The source electrode of described second amplification nmos pipe connects electronegative potential supply
End vs, drain electrode is connected with the source electrode of the described first amplification nmos pipe；The grid of described first amplification nmos pipe and described rs triggering
The q end of device is connected, and drain electrode meets high potential feed end vb.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201620477571.9U CN205912035U (en) | 2016-05-24 | 2016-05-24 | High voltage drive circuit's filter circuit and high voltage drive circuit |
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|---|---|---|---|
| CN201620477571.9U CN205912035U (en) | 2016-05-24 | 2016-05-24 | High voltage drive circuit's filter circuit and high voltage drive circuit |
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| CN205912035U true CN205912035U (en) | 2017-01-25 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105846813A (en) * | 2016-05-24 | 2016-08-10 | 深圳芯能半导体技术有限公司 | Filter circuit of high-voltage drive circuit and high-voltage drive circuit |
| CN107947774A (en) * | 2017-11-17 | 2018-04-20 | 中国科学院上海微系统与信息技术研究所 | LDMOS level shift dv/dt noise suppression circuits for IGBT grid drive chips |
| CN111181361A (en) * | 2020-01-10 | 2020-05-19 | 电子科技大学 | Level shifter applied to segmented driving circuit of wide bandgap power device |
| CN112260664A (en) * | 2020-11-03 | 2021-01-22 | 电子科技大学 | Digital filter and high-voltage driving circuit applying same |
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2016
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105846813A (en) * | 2016-05-24 | 2016-08-10 | 深圳芯能半导体技术有限公司 | Filter circuit of high-voltage drive circuit and high-voltage drive circuit |
| CN105846813B (en) * | 2016-05-24 | 2018-11-13 | 深圳芯能半导体技术有限公司 | The filter circuit and high-voltage driving circuit of high-voltage driving circuit |
| CN107947774A (en) * | 2017-11-17 | 2018-04-20 | 中国科学院上海微系统与信息技术研究所 | LDMOS level shift dv/dt noise suppression circuits for IGBT grid drive chips |
| CN107947774B (en) * | 2017-11-17 | 2020-05-22 | 中国科学院上海微系统与信息技术研究所 | LDMOS level shift dv/dt noise suppression circuit for IGBT grid electrode driving chip |
| CN111181361A (en) * | 2020-01-10 | 2020-05-19 | 电子科技大学 | Level shifter applied to segmented driving circuit of wide bandgap power device |
| CN112260664A (en) * | 2020-11-03 | 2021-01-22 | 电子科技大学 | Digital filter and high-voltage driving circuit applying same |
| CN112260664B (en) * | 2020-11-03 | 2023-06-02 | 电子科技大学 | Digital filter and high-voltage driving circuit applying same |
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