CN106452424B - A kind of differential driver with preemphasis - Google Patents
A kind of differential driver with preemphasis Download PDFInfo
- Publication number
- CN106452424B CN106452424B CN201610782319.3A CN201610782319A CN106452424B CN 106452424 B CN106452424 B CN 106452424B CN 201610782319 A CN201610782319 A CN 201610782319A CN 106452424 B CN106452424 B CN 106452424B
- Authority
- CN
- China
- Prior art keywords
- signal
- module
- differential
- preemphasis
- emphasis
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
Abstract
The present invention relates to a kind of differential driver with preemphasis, including differential signal generation module, differential driving module, pre-emphasis module, control signal generation module and bias voltage modules.The present invention increases pre-emphasis module in differential driver, improves the rate and anti-interference of output signal, has good matching degree with input signal, improves the quality of signal after preemphasis；Controlling signaling module has rate fast, and be delayed small feature, can accurately rise on the input signals/decline when to driving circuit provide the function of preemphasis, signal quality after ensure that preemphasis；The instantaneous pressure that can be worked at lower voltages, and provide in the pre-emphasis module with double-current source can effectively inhibit noise, improve signal transmission distance.
Description
Technical field
The present invention relates to a kind of differential drivers with preemphasis, belong to CMOS Analog Circuit Design.
Background technique
Traditional lvds driver uses single electric current source module, and signal is in overturning and stable state, by the same electric current
Source provides electric current, shown in Fig. 1.Vp and Vn is bias voltage, and the size of current for flowing through the two transistors is identical.When electric current stream
It, can be in the pressure drop for receiving one about 350mV of input terminal generation when crossing the terminal resistance of 100 Ω.This structure there are the problem of
It is to be limited (250mV~450mV) by differential swings, current source current can only be within the scope of 2.5mA~4.5mA, driving capability
It is limited, there is inborn deficiency in high speed, Long-range Data Transmission.
With the development of technique, the operating voltage of device is continued to decline, device operating voltages from 5V drop to 2.5V with
Afterwards, a kind of solution work is to improve device size, and the raising of device size is inevasible brings speed in the method for low-voltage
The decline of rate.
Summary of the invention
The technology of the present invention solves the problems, such as: a kind of differential driver with preemphasis is overcome the deficiencies of the prior art and provide,
Effective solution lvds driver rate declines problem.
The technology of the present invention solution: a kind of differential driver with preemphasis, including differential signal generation module, difference
Divide drive module, pre-emphasis module, control signal generation module and bias voltage module；
The single-ended signal of input is converted into differential signal by differential signal generation module, for differential driving module and control
Signal generation module uses；
Differential driving module receives the full swing differential signal provided by differential signal generation module, through pre-emphasis module
After exacerbation, differential signal is converted into LVDS signal；
Pre-emphasis module receives and controls signal by the preemphasis that control signal generation module generates, in the upper of data-signal
Liter/failing edge provides additional driving current to differential driving module, improves signal and overturns rate；
Signal generation module is controlled, logic fortune is carried out by the differential signal data-signal generated to difference generation module
Calculate, generate control signal, control opening and shutting off for pre-emphasis module, it is ensured that pre-emphasis module only the rising of data-signal/
Decline moment work；
Bias voltage module provides bias voltage for differential driving module and pre-emphasis module.
The pre-emphasis module uses four pipe switching circuits and double-current source structure, and four pipes switch can effectively reduce
Leakage current, and keep the symmetry of charging current and discharge current.
The pre-emphasis module includes M3~M8, and wherein M3 is PMOS current source, M4 is NMOS current source, and M5~M8 is
NMOS switch pipe receives preemphasis and controls signal, and control preemphasis current path is opened and shut off；The drain of M3 with two
M5 and the M6 drain electrode of NMOS is connected, and the source level of M5 is connected with the drain electrode of M7, and the source level of M6 is connected with the drain electrode of M8, the source of M7, M8
Grade is connected with the drain electrode of M4；M3 and M4 forms current-mirror structure by bias voltage, and M5~M8 is the switch control of pre-emphasis module
Tubulation.
The differential signal generation module using single ended data signal I as reverser INV1 and by PMOS tube M1 and
The input of the transmission gate of NMOS tube M2 composition, generates one group of reverse signal S1, S2.
The differential driving module uses double-current source structure, including M9~M14, and wherein M9 is PMOS current source, M10
For NMOS current source, M11~M14 is input signal reception pipe；M9 drain is connected with M11 with the drain electrode of M12, the source level of M11 with
The drain electrode of M13 is connected, and the source level of M12 is connected with the drain electrode of M14, and the drain electrode of the source level M10 of M13, M14 are connected, and M9 passes through with M10
The source level of bias voltage formation current-mirror structure, M11 and M12 are connected by the biggish resistance of two resistance values, between two resistance
Common mode electrical level is biased to by Vref, to guarantee the stability of output signal common mode electrical level.
The resistance value of described two biggish resistance of resistance value is greater than 100K ohm.
The control signal generation module includes four reverser INV2-5, exclusive or non-exclusive XNOR, NOR1, NOR2；
Input signal I generates two delays identical reverse signal S1, S2, institute after differential signal generation module
State the input signal that reverse signal is differential drive circuit；In addition, S1 signal after the second to the 4th phase inverter INV2-4 with
Former S1 signal carries out XOR operation by XNOR, and output signal is connected to NOR1 and NOR2 after the 5th phase inverter INV5,
Another input signal of NOR1 is S1, and another input signal of output signal D2, NOR2 are S2, output signal D1；D1
It is that preemphasis controls signal with D2, D1 signal is to rise control signal, and D2 signal is decline control signal, and two pulse signals are wide
Degree is consistent, and phase difference is 180 °, and the two control pre-emphasis module works during signal raising and lowering.
The biasing module is by complementary NMOS tube M15 and PMOS tube M16, metal-oxide-semiconductor M17 and an additional current source
Ibias composition；The drain terminal of M16 is connected with the source of M15, and the drain terminal of M15 is shorted with grid end and is connected with pre-emphasis module；
Ibias flows into the drain terminal of M17, and the grid leak of M17 is shorted, and is connect with M16, pre-emphasis module and differential driving module.
The advantages of the present invention over the prior art are that:
(1) present invention increases pre-emphasis module in differential driver, improves the rate of output signal and anti-interference
Property, there is good matching degree with input signal, improve the quality of signal after preemphasis.
(2) control signaling module of the invention has rate fast, and be delayed small feature, can accurately on the input signals
The function of preemphasis is provided to driving circuit when liter/decline, the signal quality after ensure that preemphasis.
(3) there is the present invention pre-emphasis module in double-current source can work at lower voltages, and the moment provided
High pressure can effectively inhibit noise, improve signal transmission distance.
Detailed description of the invention
Fig. 1 is conventional LVDS driver；
Fig. 2 is theory of constitution figure of the present invention；
Fig. 3 is the simulation result that switching signal controls signal D1, D2；
Fig. 4 is output waveform frequency simulation result；
Fig. 5 is output waveform rise time simulation result；
Fig. 6 is preemphasis differential driver design flow diagram of the present invention.
Specific embodiment
As shown in Fig. 2, the differential driver with preemphasis of the invention is by differential signal generation module, differential driving mould
Block, pre-emphasis module, control signal generation module and bias voltage module composition.
Differential signal generation module is using single ended data signal I as reverser INV1 and by PMOS tube M1 and NMOS tube
The input of the transmission gate of M2 composition, generates one group of reverse signal S1, S2.
Differential driving module uses double-current source structure, and preemphasis circuit module uses four pipe switching circuits and double
Current source structure, the benefit of the structure are the stabilizations that double-current source can preferably control electric current, and four pipes switch can be effective
Reduction leakage current, and keep charging current and discharge current symmetry.Another crucial structure is then switching signal
Generation module, the switching signal retention time is too short, efficiency for charge-discharge can be made to reduce, and overlong time can then bring it is additional
Overshoot voltage increases the amplitude of oscillation of differential signal, influences signal quality.
As shown in Fig. 2, pre-emphasis module is made of M3~M8, wherein M3 be PMOS current source, drain and NMOS M5 with
The drain electrode of M6 is connected, and the source level of M5 is connected with the drain electrode of M7, and the source level of M6 is connected with the drain electrode of M8, the source level and NMOS of M7, M8
The drain electrode of current source M4 is connected, and in this structure, by bias voltage formation current-mirror structure, M5~M8 is pre-add molality by M3 and M4
The switch control pipe of block.
Differential driving module is made of M9~M14, and wherein M9 is PMOS current source, drain and NMOS M11 and M12
Drain electrode be connected, the source level of M11 is connected with the drain electrode of M13, and the source level of M12 is connected with the drain electrode of M14, the source level of M13, M14 and
The drain electrode of NMOS current source M10 is connected, and in this structure, by bias voltage formation current-mirror structure, M11~M14 is by M9 and M10
The source level of input signal reception pipe, M11 and M12 are connected by the biggish resistance of two resistance values, inclined by Vref between two resistance
It is set to common mode electrical level, to guarantee the stability of output signal common mode electrical level.
Control signal generation module include four reverser INV2-5, exclusive or non-exclusive XNOR, NOR1, NOR2.
Input signal I generates two delays identical reverse signal S1, S2, institute after differential signal generation module
State the input signal that reverse signal is differential drive circuit；In addition, S1 signal after the second to the 4th phase inverter INV2-4 with
Former S1 signal carries out XOR operation by XNOR, and output signal is connected to NOR1 and NOR2 after the 5th phase inverter INV5,
Another input signal of NOR1 is S1, and another input signal of output signal D2, NOR2 are S2, output signal D1；D1
It is that preemphasis controls signal with D2, D1 signal is to rise control signal, and D2 signal is decline control signal, and two pulse signals are wide
Degree is consistent, and phase difference is 180 °, and the two control pre-emphasis module works during signal raising and lowering.
Table 1NOR2 truth table
| A | B | INV5 output |
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
From the function of NOR gate it is found that output is 1 (height), utilizes this only when two inputs of NOR are 0 (low)
Kind characteristic, when I signal is by low get higher, the output signal of S1 and INV4 generate one narrow low pulse after exclusive or non-exclusive, this is low
Pulse and S2 generate high impulse D1 one narrow after NOR gate, and D1 is that rising edge controls signal.When I signal is lower by height
When, the output signal of S1 and INV4 generate one narrow low pulse after exclusive or non-exclusive, and the low pulse and S1 pass through NOR2 behind the door, raw
It is that failing edge controls signal at high impulse D2 one narrow, D2.
The non-truth table of table 2XNOR
| S1 | INV4 output | INV5 output |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
| 0 | 0 | 0 |
M15~M17 and additional current source Ibias forms bias voltage module, and Ibias flows into NMOS tube M17
Drain terminal, the grid leak of M17 is shorted, and is connected with the grid of M16, M10, M4, and the electric current of Ibias is answered by way of current mirror
M4 and M10 are made, M4 and M10 size of current is determined by the ratio of itself and M17.The drain terminal of M16 is connected with the source of M15, M15's
Drain terminal is shorted with grid end and is connected with the grid end of M3, M9, and the electric current of Ibias is copied to M3 and M9 by way of current mirror.
Fig. 3~5 are differential driver simulation result, and wherein Fig. 3 is the simulation result that switching signal controls signal D1, D2.
In Fig. 3, top is divided into charging control signal, and lower part is divided into discharge control signal, and the effect of charging control signal is
When data rise, control preemphasis circuit is opened；The effect that discharge control signal is done is the control preemphasis electricity in data decline
It opens on road；When two signals are low, preemphasis circuit is in an off state.
The simulation result that Fig. 4 and Fig. 5 are input clock when being 400MHz, wherein Fig. 4 is output waveform frequency simulation result,
Fig. 5 is output waveform rise time simulation result.
After introducing load resistance, emulation is re-started to entire circuit, as a result as shown in figs. 5 and 6, in 800Mbps,
Under the conditions of SS, N, P two-way waveform symmetry are preferable, and the differential signal amplitude of oscillation is 350mA or so, meet LVDS standard requirements, thereon
Liter/failing edge the time is only 713ps, can meet high rate data transmission requirement.
It can significantly see that the speed of LVDS signal rising edge and failing edge is obviously improved, but the amplitude of differential signal is still
It is maintained at 350mV or so, and ensure that the quality of signal well.
As shown in fig. 6, the differential driver design cycle with preemphasis is as follows
(1) combined process feature determines driver working frequency and driving capability according to object is used
(2) according to circuit design feature, devising driving capability first is 3.5mA differential driver, is set on this basis
The preemphasis circuit and corresponding switching signal control circuit that maximum drive ability is 10mA are counted
(3) circuit is emulated under different process and environmental condition, guarantees that circuit function is correct, makes preemphasis circuit
It can achieve desired effect.
Claims (8)
1. a kind of differential driver with preemphasis, it is characterised in that: including differential signal generation module, differential driving mould
Block, pre-emphasis module, control signal generation module and bias voltage module；
The single-ended signal of input is converted into differential signal by differential signal generation module, for differential driving module and control signal
Generation module uses；
Differential driving module receives the full swing differential signal provided by differential signal generation module, aggravates through pre-emphasis module
Afterwards, differential signal is converted into LVDS signal；
Pre-emphasis module receives the preemphasis control signal generated by control signal generation module, data-signal rising/under
Drop improves signal and overturns rate along additional driving current is provided to differential driving module；
Signal generation module is controlled, logical operation is carried out by the differential signal data-signal generated to difference generation module, is produced
Raw control signal, controls opening and shutting off for pre-emphasis module, it is ensured that pre-emphasis module is only in the rise/fall of data-signal
Carve work；
Bias voltage module provides bias voltage for differential driving module and pre-emphasis module.
2. the differential driver according to claim 1 with preemphasis, it is characterised in that: the pre-emphasis module uses
Four pipe switching circuits and double-current source structure, four pipes switch can effectively reduce leakage current, and keep charging current with
The symmetry of discharge current.
3. the differential driver according to claim 1 or 2 with preemphasis, it is characterised in that: the pre-emphasis module
Including M3~M8, wherein M3 is PMOS current source, M4 is NMOS current source, and M5~M8 is NMOS switch pipe, receives preemphasis control
Signal processed, control preemphasis current path are opened and shut off；The drain of M3 is connected with the M5 and M6 of two NMOS drain electrode, M5's
Source level is connected with the drain electrode of M7, and the source level of M6 is connected with the drain electrode of M8, and the source level of M7, M8 are connected with the drain electrode of M4；M3 and M4 is logical
It crosses bias voltage and forms current-mirror structure, M5~M8 is the switch control pipe of pre-emphasis module.
4. the differential driver according to claim 1 with preemphasis, it is characterised in that: the differential signal generates mould
Block is generated using input signal I as reverser INV1 and by the input of PMOS tube M1 and NMOS tube the M2 transmission gate formed
One group of reverse signal S1, S2.
5. the differential driver according to claim 1 with preemphasis, it is characterised in that: the differential driving module is adopted
With double-current source structure, including M9~M14, wherein M9 is PMOS current source, and M10 is NMOS current source, and M11~M14 is defeated
Enter signal reception pipe；M9 drain is connected with M11 with the drain electrode of M12, and the source level of M11 is connected with the drain electrode of M13, the source level of M12 with
The drain electrode of M14 is connected, and the drain electrode of the source level M10 of M13, M14 are connected, and M9 and M10 forms current-mirror structure by bias voltage,
The source level of M11 and M12 is connected by the biggish resistance of two resistance values, is biased to common mode electrical level by Vref between two resistance, with
Guarantee the stability of output signal common mode electrical level.
6. the differential driver according to claim 5 with preemphasis, it is characterised in that: described two resistance values are biggish
The resistance value of resistance is greater than 100K ohm.
7. the differential driver according to claim 1 with preemphasis, it is characterised in that: the control signal generates mould
Block includes four reverser INV2-5, exclusive or non-exclusive XNOR, NOR1, NOR2；
Input signal I generates two delays identical reverse signal S1, S2, S1 signal after differential signal generation module
XOR operation is carried out by XNOR with former S1 signal after the second to the 4th phase inverter INV2-4, output signal is anti-by the 5th
NOR1 and NOR2 are connected to after phase device INV5, another input signal of NOR1 is S1, and another of output signal D2, NOR2 are defeated
Entering signal is S2, output signal D1；D1 and D2 is that preemphasis controls signal, and D1 signal is to rise control signal, and D2 signal is
Decline control signal, two pulse signal widths are consistent, phase difference be 180 °, the two control pre-emphasis module signal rise and
It works during decline.
8. the differential driver according to claim 1 with preemphasis, it is characterised in that: biasing module is by complementation
NMOS tube M15 and PMOS tube M16, metal-oxide-semiconductor M17 and an additional current source Ibias composition；The drain terminal of M16 and the source of M15
End is connected, and the drain terminal of M15 is shorted with grid end and is connected with pre-emphasis module；Ibias flows into the drain terminal of M17, and the grid leak of M17 is short
It connects, and is connect with M16, pre-emphasis module and differential driving module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610782319.3A CN106452424B (en) | 2016-08-30 | 2016-08-30 | A kind of differential driver with preemphasis |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610782319.3A CN106452424B (en) | 2016-08-30 | 2016-08-30 | A kind of differential driver with preemphasis |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106452424A CN106452424A (en) | 2017-02-22 |
| CN106452424B true CN106452424B (en) | 2019-04-09 |
Family
ID=58090372
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610782319.3A Active CN106452424B (en) | 2016-08-30 | 2016-08-30 | A kind of differential driver with preemphasis |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106452424B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113078954A (en) * | 2021-03-19 | 2021-07-06 | 苏州微光电子融合技术研究院有限公司 | Driving circuit based on phase shift pre-emphasis |
| CN114079223B (en) * | 2022-01-18 | 2022-04-26 | 长芯盛（武汉）科技有限公司 | Driving device and method for pre-emphasis processing of driving current |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7183813B2 (en) * | 2003-11-11 | 2007-02-27 | Stmicroelectronics Pvt. Ltd. | Differential signaling driver |
| CN104135272A (en) * | 2014-07-31 | 2014-11-05 | 北京大学 | Pre-emphasis LVDS (Low Voltage Differential Signaling) driver circuit capable of saving power consumption |
| CN103427331B (en) * | 2013-08-23 | 2016-04-13 | 西安电子科技大学 | The driver of Vcsel |
-
2016
- 2016-08-30 CN CN201610782319.3A patent/CN106452424B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7183813B2 (en) * | 2003-11-11 | 2007-02-27 | Stmicroelectronics Pvt. Ltd. | Differential signaling driver |
| CN103427331B (en) * | 2013-08-23 | 2016-04-13 | 西安电子科技大学 | The driver of Vcsel |
| CN104135272A (en) * | 2014-07-31 | 2014-11-05 | 北京大学 | Pre-emphasis LVDS (Low Voltage Differential Signaling) driver circuit capable of saving power consumption |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106452424A (en) | 2017-02-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104135272B (en) | Save the preemphasis LVDS drive circuits of power consumption | |
| CN105529909B (en) | Power tube gate drive circuit and drive part by part method | |
| CN101795132B (en) | Potential pull-up circuit and pull-down circuit of I/O port of integrated circuit | |
| CN102487240B (en) | Control circuit of voltage switching rate and output circuit | |
| CN107094012A (en) | A kind of level shifting circuit and method | |
| CN106026975B (en) | Auto bias circuit | |
| CN106452424B (en) | A kind of differential driver with preemphasis | |
| CN108123708B (en) | Pull-up circuit for IO circuit | |
| CN116208142A (en) | Differential signal driving circuit and method for selecting differential signal driving circuit | |
| CN209072341U (en) | The level shifter and chip across voltage domain based on DMOS pipe | |
| CN104143975B (en) | A kind of DLL time delay chains and the method for reducing delay locked loop clock duty cycle distortion | |
| CN105577165B (en) | A kind of I/O interface level shifting circuit and I/O interface level conversion method | |
| CN107835011A (en) | A kind of high reliability tristate output circuit | |
| CN107565953A (en) | A kind of control circuit of transition detection device and clock frequency regulating system | |
| CN106330172B (en) | The transmission gate of high voltage threshold device and its subsequent pull-down circuit structure | |
| CN106849922A (en) | A kind of adjustable delay circuit | |
| CN206341200U (en) | Grid driving circuit | |
| CN107800280B (en) | The driving circuit of power switch | |
| CN104716938B (en) | A kind of grid follow imput output circuit | |
| CN108011629A (en) | A kind of high-speed low-power-consumption level displacement circuit | |
| CN212434213U (en) | Pre-charging circuit of common-anode LED display screen driving chip | |
| CN107872204A (en) | A kind of new TDA circuits of low-power consumption small area large gain | |
| CN202713250U (en) | Comparison circuit | |
| CN208241644U (en) | A kind of transmission gate circuit that high input voltage is isolated | |
| CN105991125A (en) | Inverter circuit, stable-output dynamic comparator and comparison method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |