CN208923107U - DFN integrated circuit package device - Google Patents
DFN integrated circuit package device Download PDFInfo
- Publication number
- CN208923107U CN208923107U CN201821959434.4U CN201821959434U CN208923107U CN 208923107 U CN208923107 U CN 208923107U CN 201821959434 U CN201821959434 U CN 201821959434U CN 208923107 U CN208923107 U CN 208923107U
- Authority
- CN
- China
- Prior art keywords
- chip
- heat dissipation
- bonding pad
- dissipation bonding
- deep gouge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model discloses a kind of DFN integrated circuit package device, including the heat dissipation bonding pad being located in epoxy insulator, chip and conductive welding disk, the chip is located on heat dissipation bonding pad, several conductive welding disks are equipped with positioned at heat dissipation bonding pad periphery, the conductive welding disk is connected with chip by a lead, the central area of the heat dissipation bonding pad is provided with a deep gouge being embedded in for chip, to form a cofferdam in the marginal zone of heat dissipation bonding pad, silver slurry layer is provided between the bottom of the deep gouge and the lower surface and side wall of cofferdam and chip, the bottom of the deep gouge is provided with several heat exchange blind holes extended in heat dissipation bonding pad, there is silver paste filling part in the heat exchange blind hole.The utility model increases the contact area of chip and silver paste, silver paste and heat dissipation bonding pad, to increase the heat dissipation capacity in the unit time, and then improves the heat dissipation effect of encapsulating structure by the setting of deep gouge and the blind hole that exchanges heat.
Description
Technical field
The utility model relates to DFN integrated circuit package devices, belong to leadless packages technical field.
Background technique
DFN is a kind of leadless packages, is in square or rectangular, and there is the exposed weldering of large area in package bottom central location
Disk has the conductive welding disk for realizing electrical connection around the encapsulation periphery of big pad for thermally conductive.Since DFN encapsulation is unlike passing
SOIC and the TSOP encapsulation of system have gull wing lead like that, and the conductive path between internal pin and pad is short, electrodynamic capacity
And routing resistance is very low in packaging body, so it can provide brilliant electrical property, and is used widely.
It in encapsulation process, needs that chip is bonded on thermal land using silver paste, here, silver paste functions not only as bonding
Agent uses, and the heat transfer that superior heating conduction can generate chip is to thermal land, to reduce under working condition
Chip temperature, protect chip；But since chip is connected by way of attaching with silver paste, contact area is less, leads
Cause the heat dissipation effect of DFN encapsulation semiconductor devices to be improved.
Utility model content
The purpose of the utility model is to provide DFN integrated circuit package devices to be increased by the setting of deep gouge and heat exchange blind hole
The contact area of chip and silver paste, silver paste and heat dissipation bonding pad is added, to increase the heat dissipation capacity in the unit time, and then has improved
The heat dissipation effect of encapsulating structure.
In order to achieve the above objectives, the technical solution adopted in the utility model is: a kind of DFN integrated circuit package device, packet
Heat dissipation bonding pad, chip and the conductive welding disk being located in epoxy insulator are included, the chip is located on heat dissipation bonding pad, is located at heatsink welding
Disk periphery is equipped with several conductive welding disks, and the conductive welding disk is connected with chip by a lead, the center of the heat dissipation bonding pad
Area be provided with one for chip insertion deep gouge, thus heat dissipation bonding pad marginal zone formed a cofferdam, the bottom of the deep gouge and
Be provided with silver slurry layer between cofferdam and the lower surface and side wall of chip, the bottom of the deep gouge be provided with several extend to it is scattered
Heat exchange blind hole in hot weld disk has silver paste filling part in the heat exchange blind hole.
Further improved scheme is as follows in above-mentioned technical proposal:
1. in above scheme, the deep gouge depth is arranged no more than chip thickness.
2. in above scheme, the heat exchange blind hole is tapered blind hole, hole of the heat exchange blind hole close to chip one end port
Diameter is greater than heat exchange aperture of the blind hole far from chip one end port.
3. in above scheme, the heat exchange blind hole extends to heat dissipation bonding pad middle and lower part.
4. in above scheme, being provided with stepped part on the cofferdam inside.
Due to the application of the above technical scheme, the utility model has the advantage that compared with prior art
1, the utility model DFN integrated circuit package device, it is matched heavy with chip to open up in the middle part of heat dissipation bonding pad
Corresponding chip so that silver paste is placed in deep gouge by staff in pasting chip, and is installed into deep gouge i.e. by slot
It can；At this point, chip lower part, in deep gouge, not only its bottom can pass through the silver slurry layer and deep gouge bottom adhesive of formation, chip
The side wall of lower part also can mutually be bonded with the inner wall of the cofferdam outside deep gouge by silver slurry layer, and not only chip and silver slurry layer connect
Contacting surface product increased, and the contact area of silver slurry layer and heat dissipation bonding pad also increased, so that in the unit time, more
More heats conducts between chip and silver slurry layer, between silver slurry layer and heat dissipation bonding pad, and then improves DFN and encapsulate semiconductor devices
Heat dissipation effect.
2, the utility model DFN integrated circuit package device opens up heat exchange blind hole in deep gouge bottom, and the blind hole that will exchange heat
Be set as tapered blind hole, on the one hand, the setting for the blind hole that exchanges heat can accommodating portion silver paste, avoid extra silver paste from overflowing deep gouge,
On the other hand, after having silver paste filling part in the blind hole that exchanges heat, the contact area of silver paste and heat dissipation bonding pad is further increased, encapsulation
Heat dissipation effect is further promoted, also, with the raising of heat exchange blind hole quantity, encapsulating structure heat dissipation effect is gradually mentioned
It is high.
3, upper deep gouge is arranged in the central area of heat dissipation bonding pad, moreover it is possible to convenient in the utility model DFN integrated circuit package device
The installation site of staff's calibration chip realizes the accurate installation of chip, improves chip package quality；Meanwhile it is chip is embedding
Loaded in deep gouge, can positioning chip position, cooperate silver paste setting protection chip and the lead that connect with chip, improves and encapsulates
Quality.
4, the utility model DFN integrated circuit package device, after upper stepped part is opened up on the inside of cofferdam, chip insertion is heavy
When slot, extra part silver paste is able to enter stepped part between cofferdam inner wall and chip lower sides, thus avoid it is extra
Silver paste spreads to chip upper surface in extrusion process, and influences the normal work of chip.
Detailed description of the invention
Attached drawing 1 is the structural schematic diagram of the DFN integrated circuit package device of the utility model embodiment 1；
Attached drawing 2 is the structural schematic diagram of the DFN integrated circuit package device of the utility model embodiment 2.
In the figures above: 1, heat dissipation bonding pad；11, deep gouge；12, cofferdam；121, stepped part；13, exchange heat blind hole；2, silver paste
Layer；21, silver paste filling part；3, chip；4, conductive welding disk；5, lead；6, epoxy insulator.
Specific embodiment
Embodiment 1:DFN integrated circuit package device, referring to attached drawing 1, including the heat dissipation bonding pad being located in epoxy insulator 6
1, chip 3 and conductive welding disk 4, the chip 3 are located on heat dissipation bonding pad 1, are located at 1 periphery of heat dissipation bonding pad and are equipped with several conduction welderings
Disk 4, the conductive welding disk 4 and chip 3 are connected by a lead 5, and it is embedding for chip 3 that the central area of the heat dissipation bonding pad 1 is provided with one
The deep gouge 11 entered, to form a cofferdam 12 in the marginal zone of heat dissipation bonding pad 1, the bottom of the deep gouge 11 and cofferdam 12 with
Silver slurry layer 2 is provided between the lower surface and side wall of chip 3, the bottom of the deep gouge 11 is provided with several and extends to heatsink welding
Heat exchange blind hole 13 in disk 1 has silver paste filling part 21 in the heat exchange blind hole 13.
Above-mentioned 11 depth of deep gouge is arranged no more than 3 thickness of chip；
Above-mentioned heat exchange blind hole 13 is tapered blind hole, and above-mentioned heat exchange blind hole 13 is greater than close to the aperture of 3 one end port of chip changes
Aperture of the hot blind hole 13 far from 3 one end port of chip；
Above-mentioned heat exchange blind hole 13 extends to 1 middle and lower part of heat dissipation bonding pad；
Stepped part 121 is provided on above-mentioned 12 inside of cofferdam.
Embodiment 2:DFN integrated circuit package device, referring to attached drawing 2, including the heat dissipation bonding pad being located in epoxy insulator 6
1, chip 3 and conductive welding disk 4, the chip 3 are located on heat dissipation bonding pad 1, are located at 1 periphery of heat dissipation bonding pad and are equipped with several conduction welderings
Disk 4, the conductive welding disk 4 and chip 3 are connected by a lead 5, and it is embedding for chip 3 that the central area of the heat dissipation bonding pad 1 is provided with one
The deep gouge 11 entered, to form a cofferdam 12 in the marginal zone of heat dissipation bonding pad 1, the bottom of the deep gouge 11 and cofferdam 12 with
Silver slurry layer 2 is provided between the lower surface and side wall of chip 3, the bottom of the deep gouge 11 is provided with several and extends to heatsink welding
Heat exchange blind hole 13 in disk 1 has silver paste filling part 21 in the heat exchange blind hole 13.
Above-mentioned 11 depth of deep gouge is arranged no more than 3 thickness of chip；
Above-mentioned heat exchange blind hole 13 is tapered blind hole, and above-mentioned heat exchange blind hole 13 is greater than close to the aperture of 3 one end port of chip changes
Aperture of the hot blind hole 13 far from 3 one end port of chip；
Above-mentioned heat exchange blind hole 13 extends to 1 middle and lower part of heat dissipation bonding pad.
When encapsulating semiconductor devices using above-mentioned DFN, by the setting of deep gouge 11 and the blind hole 13 that exchanges heat, increasing chip
3 and while silver paste contact area, increase the contact area of silver paste and heat dissipation bonding pad 1, to increase in the unit time, chip 3
With the heat exchange amount of silver paste, silver paste and heat dissipation bonding pad 1, the heat dissipation effect of semiconductor devices is encapsulated so as to improve DFN；In addition, deep gouge
11 setting can also facilitate the accurate chip 3 of staff, and silver paste is cooperated to stablize the chip 3 of insertion deep gouge 11, improve core
The stability that piece 3 is installed, to improve 3 package quality of chip.
The above embodiments are only for explaining the technical ideas and features of the present invention, and its object is to allow be familiar with technique
Personage can understand the content of the utility model and implement accordingly, do not limit the protection scope of the present invention.
All equivalent change or modifications according to made by the spirit of the present invention essence, should all cover the protection scope of the utility model it
It is interior.
Claims (5)
1. a kind of DFN integrated circuit package device, including be located in epoxy insulator (6) heat dissipation bonding pad (1), chip (3) and
Conductive welding disk (4), the chip (3) are located on heat dissipation bonding pad (1), are located at heat dissipation bonding pad (1) periphery and are equipped with several conduction welderings
Disk (4), the conductive welding disk (4) and chip (3) are connected by a lead (5), it is characterised in that: the heat dissipation bonding pad (1)
Central area is provided with a deep gouge (11) being embedded in for chip (3), to form a cofferdam in the marginal zone of heat dissipation bonding pad (1)
(12), silver slurry layer is provided between the bottom and cofferdam (12) and the lower surface and side wall of chip (3) of the deep gouge (11)
(2), the bottom of the deep gouge (11) is provided with several heat exchange blind holes (13) extended in heat dissipation bonding pad (1), and the heat exchange is blind
There are silver paste filling part (21) in hole (13).
2. DFN integrated circuit package device according to claim 1, it is characterised in that: deep gouge (11) depth is little
It is arranged in chip (3) thickness.
3. DFN integrated circuit package device according to claim 1, it is characterised in that: the heat exchange blind hole (13) is cone
Shape blind hole, heat exchange blind hole (13) are greater than heat exchange blind hole (13) far from chip (3) one close to the aperture of chip (3) one end port
Hold the aperture of port.
4. DFN integrated circuit package device according to claim 3, it is characterised in that: the heat exchange blind hole (13) extends
To heat dissipation bonding pad (1) middle and lower part.
5. DFN integrated circuit package device according to claim 1, it is characterised in that: on cofferdam (12) inside
It is provided with stepped part (121).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821959434.4U CN208923107U (en) | 2018-11-27 | 2018-11-27 | DFN integrated circuit package device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821959434.4U CN208923107U (en) | 2018-11-27 | 2018-11-27 | DFN integrated circuit package device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208923107U true CN208923107U (en) | 2019-05-31 |
Family
ID=66712430
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821959434.4U Active CN208923107U (en) | 2018-11-27 | 2018-11-27 | DFN integrated circuit package device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208923107U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113690195A (en) * | 2021-09-16 | 2021-11-23 | 珠海零边界集成电路有限公司 | Packaging frame, packaging structure and preparation method of packaging frame |
-
2018
- 2018-11-27 CN CN201821959434.4U patent/CN208923107U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113690195A (en) * | 2021-09-16 | 2021-11-23 | 珠海零边界集成电路有限公司 | Packaging frame, packaging structure and preparation method of packaging frame |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108573936A (en) | Semiconductor packages | |
| CN103489845B (en) | Electric device package and the method for making electric device package | |
| CN105244347B (en) | A kind of embedded encapsulation and packaging method | |
| CN207765435U (en) | A kind of encapsulating structure of upside-down mounting welding core | |
| CN208111434U (en) | Power module | |
| CN208923107U (en) | DFN integrated circuit package device | |
| CN208923104U (en) | Chip-packaging structure based on QFN | |
| CN101091247B (en) | Dual flat non-leaded semiconductor package | |
| CN215377395U (en) | Packaging structure for semiconductor chip | |
| CN104064532A (en) | Device packaging structure with heat dissipation structure and manufacturing method | |
| CN101882606B (en) | Heat-dissipation semiconductor encapsulation structure and manufacturing method thereof | |
| CN206532771U (en) | Cooling type semiconductor device | |
| CN219435850U (en) | MOSFET chip packaging structure | |
| CN104900612B (en) | A kind of packaging body with umbilicate type cooling fin fin base stacks radiator structure and preparation method thereof | |
| CN209104141U (en) | A kind of chip exposed type encapsulating structure | |
| CN109950158A (en) | The preparation method of high thermal conductivity DFN packaging | |
| CN206595249U (en) | Carry the SOP device encapsulation structures of high current | |
| CN209000902U (en) | A kind of encapsulating structure of frame clsss product enhancing heat dissipation | |
| CN112563226B (en) | DFN packaging device convenient for heat dissipation | |
| CN210200717U (en) | Silicon controlled rectifier adopting insulation encapsulation | |
| CN209298116U (en) | The solar energy of base island separate type bypasses core component frame | |
| CN208923108U (en) | The anti-short circuit DFN device encapsulation structure of SMT | |
| CN206742221U (en) | Electrode for chip package and the chip-packaging structure using the electrode | |
| CN207690783U (en) | A kind of new type integrated circuit encapsulating structure | |
| CN107808872B (en) | A kind of ball grid array Plastic Package preparation method that cavity is downward |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |