CN208861981U - A kind of high speed interface ESD protective device - Google Patents

Abstract

The utility model discloses a kind of high speed interface ESD protective devices, including packaging frame, chip circuit plate and dielectric layer；Dielectric layer is set between the packaging frame and chip circuit plate；Non-conductive adhesive load is arranged in the dielectric layer.Dielectric layer is that CVD deposits silicon dioxide layer.Dielectric layer with a thickness of 0.5~1um.High speed interface ESD protective device provided by the utility model, by the way that the silicon dioxide layer and non-conductive glue layer that CVD is deposited is arranged in chip back；The back side patch insulating film or non-conductive glue layer of silicon dioxide layer, are not only provided with silica, but also have non-conductive glue layer between chip and packaging frame, increase the dielectric constant between chip substrate and packaging frame, to reduce parasitic capacitance.By reducing the parasitic capacitance of IO-GND, being connected in IO-IO reserves more bulky capacitor space；The lower capacitor of IO-IO, IO-GND is realized, the product that can make to change products meet wider array of application field.

Description

A kind of high speed interface ESD protective device

Technical field

The utility model relates to technical field of semiconductor device, especially a kind of high speed interface ESD protective device.

Background technique

With the continuous development of interface data transmission rate, the high-speed interfaces such as HDMI2.0Type C want protection product It asks and has not only been embodied in low residual voltage, junction capacity is also most important.At present applied to HDMI2.0 interface protection product with Based on DFN2510 encapsulation, the product Pin1, Pin2, Pin4 and Pin5 are I/O port, and Pin3 and Pin8 is GND mouthfuls, by current low Capacitance structure, the capacitor of IO-IO are the general of IO-GND capacitor, and device capacitor has and discharge capability positive correlation, therefore, IO- The capacitor of GND limits the discharge capability of IO-IO.

Although this function can also be realized with the packaged type of non-conductive adhesive, due to the parasitic capacitance before chip and substrate It influences, still can not accomplish the capacitors such as IO-IO and IO-GND.

Summary of the invention

The purpose of this utility model is to propose a kind of high speed interface ESD protective device；This product is in existing structure On the basis of by improve encapsulation, realize IO-IO, the capacitors such as IO-GND, so that the discharge capability of IO-IO is improved.

The purpose of this utility model is achieved through the following technical solutions:

A kind of high speed interface ESD protective device provided by the utility model, including capacitor, Pin branch, two pole of pressure stabilizing Pipe；The anode of the zener diode is connected in series to the capacitor；The Pin branch circuit parallel connection is in the both ends of zener diode.

Further, the Pin branch includes first diode and the second diode；The anode of the first diode and steady Press the anode connection of diode；The cathode of the first diode is connect with the anode of the second diode；Second diode Cathode and zener diode cathode connect.

Further, the Pin branch is several Pin branches parallel with one another.

Further, the zener diode includes packaging frame, chip circuit plate and dielectric layer；The packaging frame and core Dielectric layer is set between piece circuit board；Non-conductive glue layer is arranged in the dielectric layer.

Further, the dielectric layer is that CVD deposits silicon dioxide layer.

Further, the dielectric layer with a thickness of 0.5~1um.

By adopting the above-described technical solution, the utility model has the advantage that

High speed interface ESD protective device provided by the utility model, by the way that two that CVD is deposited are arranged in chip back Silicon oxide layer and non-conductive glue layer；The back side patch insulating film or non-conductive glue layer of silicon dioxide layer, in chip circuit plate and encapsulation Not only it is provided with silica between frame, but also has non-conductive glue layer, the dielectric increased between chip substrate and packaging frame is normal Number, to reduce parasitic capacitance.By reducing the parasitic capacitance of IO-GND, being connected in IO-IO reserves more bulky capacitor space；It is real The lower capacitor of IO-IO, IO-GND is showed, the product that can make to change products meet wider array of application field.

Other advantages, target and feature of the utility model will be explained in the following description to a certain extent It states, and to a certain extent, based on will be apparent to those skilled in the art to investigating hereafter, or Person can be instructed from the practice of the utility model.The target of the utility model and other advantages can be said by following Bright book is achieved and obtained.

Detailed description of the invention

The Detailed description of the invention of the utility model is as follows.

Fig. 1 is the device junction composition of the utility model.

Fig. 2 is the CVD silica of the utility model.

Fig. 3 is that insulating film or point non-conductive adhesive are pasted in the back side of the utility model.

Fig. 4 is that the device of the utility model welds figure.

Specific embodiment

The utility model is described in further detail with reference to the accompanying drawings and examples.

As shown in Figure 1, high speed interface ESD protective device provided in this embodiment, including packaging frame, chip circuit Plate, dielectric layer；Chip circuit back is provided with dielectric layer, with a thickness of 0.5~1um；Paste insulating film or point in the dielectric layer back side Non-conductive adhesive load, existing silica between chip circuit plate and frame, and have non-conductive adhesive, increase chip circuit plate Dielectric constant between (chip substrate) and packaging frame, to reduce parasitic capacitance.By improving packaged type, device is improved The actual parameter of part meets high-speed interface protection application；The dielectric layer is silicon dioxide layer；The silicon dioxide layer is Gao Jie Constant dielectric layer.It is as follows to improve structure: after chip grinding, one layer of high dielectric constant being formed by CVD deposition process and is situated between Matter reduces the parasitic capacitance between chip and frame.By reducing the parasitic capacitance of IO-GND, be connected in IO-IO reserve it is bigger Capacitor space；The lower capacitor of IO-IO, IO-GND is realized, the product that can make to change products meet wider array of application field.Concrete technology is, After the completion of chip manufacture, by grinding back surface to required thickness is encapsulated, then CVD deposits layer of silicon dioxide, with a thickness of 0.5~ 1um.Non-conductive adhesive encapsulation；Silicon chip back side patch insulating film selects non-conductive adhesive load, existing so between chip and frame Silica, and have non-conductive adhesive, the dielectric constant between chip substrate and frame is increased, to reduce parasitic capacitance.

Pin1-5 in Fig. 1 is the tie point of device；IO in Fig. 2 is input/output terminal；Substrate is silicon dioxide layer SiO2；Non-conductive adhesive is also set up below silicon dioxide layer SiO2 in Fig. 3；The pad schematic diagram of the position Fig. 4 core device.

Packaging frame provided in this embodiment includes pipe lid and tube socket, and the pipe lid is placed on the tube socket；In pipe lid First electrode is arranged in inner surface；Second electrode is welded in the upper surface of tube socket；For being correspondingly connected with first electrode and the first electricity Pole；

Further include substrate positioning framework, the substrate positioning framework be set to inside tube socket for the chip substrate into Row positioning；It is suitable for the first electrode and second electrode corresponds；

The convex surface matched and shrinkage pool, the convex surface and shrinkage pool are additionally provided between tube socket and pipe lid provided in this embodiment For to the pipe Gai Dingwei；It is suitable for pipe lid and tube socket is fitted close.

Finally, it is stated that above embodiments are merely intended for describing the technical solutions of the present application, but not for limiting the present application, although ginseng The utility model is described in detail according to preferred embodiment, those skilled in the art should understand that, it can be to this The technical solution of utility model is modified or replaced equivalently, should all without departing from the objective and range of the technical program Cover in the protection scope of the utility model.

Claims (5)

1. a kind of high speed interface ESD protective device, it is characterised in that: including capacitor, Pin branch and zener diode；Institute The anode for stating zener diode is connected in series to the capacitor；The Pin branch circuit parallel connection is in the both ends of zener diode；

The zener diode includes packaging frame, chip circuit plate and dielectric layer；The packaging frame and chip circuit plate it Between dielectric layer is set；Non-conductive glue layer is arranged in the dielectric layer.

2. high speed interface ESD protective device as described in claim 1, it is characterised in that: the Pin branch includes first Diode and the second diode；The anode of the first diode and the anode of zener diode connect；The first diode Cathode connect with the anode of the second diode；The cathode of second diode and the cathode of zener diode connect.

3. high speed interface ESD protective device as described in claim 1, it is characterised in that: the Pin branch is several phases Mutually Pin branch in parallel.

4. high speed interface ESD protective device as claimed in claim 3, it is characterised in that: the dielectric layer is CVD deposit Silicon dioxide layer.

5. high speed interface ESD protective device as claimed in claim 3, it is characterised in that: the dielectric layer with a thickness of 0.5~1um.