CN208819832U - The enhanced HEMT device of p-type grid - Google Patents
The enhanced HEMT device of p-type grid Download PDFInfo
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Abstract
The utility model discloses a kind of enhanced HEMT devices of p-type grid.The enhanced HEMT device of p-type grid includes: the hetero-junctions comprising the first semiconductor and the second semiconductor, is formed with two-dimensional electron gas in the hetero-junctions；The p-type semiconductor and high-resistance semi-conductor being formed on hetero-junctions；And source electrode, drain and gate；The source electrode, drain electrode and hetero-junctions form Ohmic contact, p-type semiconductor is located at region under grid and connect with grid, p-type semiconductor is used to exhaust the two-dimensional electron gas in region under grid, high-resistance semi-conductor is located between any one in p-type semiconductor and source electrode, drain electrode, and the thickness of high-resistance semi-conductor is less than the thickness of p-type semiconductor；Source electrode can be electrically connected with drain electrode by two-dimensional electron gas.The enhanced HEMT device of p-type grid provided by the utility model does not need secondary epitaxy, does not need region under the grid to device yet and performs etching, and avoids the uniformity because etching technics introduces, repeatability and introduces damage problem.
Description
Technical field
The utility model relates to a kind of enhanced HEMT device, in particular to a kind of enhanced HEMT device of p-type grid belongs to
Semiconductor electronic switching device technology field.
Background technique
Important representative of III group-III nitride semiconductor as third generation semiconductor material, with the first generation, second generation semiconductor
Material is compared, and the advantages that forbidden bandwidth is big, breakdown electric field is high, electron mobility is high and saturated electrons rate is high is possessed.Therefore, III
Group-III nitride semiconductor has wide practical use in fields such as industry, electric system, communications and transportation, communication, consumer electronics.Ⅲ
Group-III nitride semiconductor heterojunction structure, by taking AlGaN/GaN hetero-junctions as an example because polarity effect can produce high concentration (>
1013cm-2) and high electron mobility (> 103cm2/ Vs) two-dimensional electron gas (2DEG).It is different based on III group-III nitride semiconductor
The high electron mobility transistor (HEMT) of matter structure is suitable as high frequency power switching device, and maximum operating frequency can achieve
10MHz.But the 2DEG of high concentration makes the HEMT usually manufactured be normally on device.In actual circuit application, open type
Device needs to introduce negative pressure source and is allowed to turn off, and not only there is security risk, but also increase the complexity and cost of circuit.
By taking AlGaN/GaN HEMT as an example, realize that enhanced major programme includes that the realization of Cascode structure is enhanced,
Mainly by the AlGaN/GaN HEMT device of depletion type and enhanced Si metal oxide semiconductor field-effect device (MOSFET)
Device connection；The realization of groove grid structure is enhanced, mainly performs etching to the AlGaN under grid；Enhancing is realized in F ion processing
Type mainly injects F ion in the AlGaN potential barrier under grid；P-type grid structure realize it is enhanced, mainly in grid and
P- (Al) GaN layer is inserted between AlGaN layer.Wherein p-type grid structure realizes that enhanced is that p- is inserted between grid and AlGaN layer
(Al) GaN layer realizes that enhanced AlGaN/GaN HEMT includes a variety of specific implementation technical solutions；Such as part shown in Fig. 1
The enhanced HEMT scheme for etching p-GaN, by being inserted into p-GaN layer between grid (G) and AlGaN layer, and to grid with
The p-GaN of tens outer nano thickness is performed etching.Utilize potential barrier at p-GaN raising AlGaN/GaN interface-channel to Fermi's energy
On grade, so that the conducting channel below grid disconnects, two-dimensional electron gas is exhausted, is realized enhanced；Its device realized needs
The p-GaN of tens nano thickness other than grid is performed etching, technology controlling and process is difficult, poor repeatability；Etching is easy to produce boundary
Face state causes device current avalanche to aggravate, influences device performance.Selection region extension p-GaN's shown in Fig. 2 is enhanced
HEMT is mentioned by selection region (only region under grid) the extension p-GaN layer between grid (G) and AlGaN layer using p-GaN
At high AlGaN/GaN interface-channel on potential barrier to fermi level, so that the conducting channel below grid disconnects, by Two-dimensional electron
Gas consumption is most, realizes enhanced；That there are threshold values is low for its enhancement device realized, it is difficult to realize the device of high threshold voltage；Technique
Realize difficulty, epitaxial quality is not high；Extension p-GaN side wall is not steep, influences subsequent technique.Hydrogen shown in Fig. 3 is passivated p-GaN
Enhanced HEMT exhaust the Two-dimensional electron below grid by being inserted into p-GaN layer between grid (G) and AlGaN layer
Gas realizes enhancement device, and makes using the methods of H plasma treatment the p-GaN of tens nano thickness other than grid blunt
Change, forms high resistant GaN cap；Energy needed for its device hydrogen ion realized is high, causes to damage to material, and OFF state electric leakage is big,
To make loss increase, breakdown voltage reduces；Hydrogen ion energy is high, is injected into AlGaN barrier region, causes under saturation current
Drop；There are high resistant GaN cap to decline saturation current because of polarity effect.
In place of the above equal Shortcomings of prior art, such as etching technics control is difficult, poor repeatability, while can produce
Raw interfacial state, aggravates current collapse, influences device performance.The extension difficulty of selective area epitaxial p- (Al) GaN is big, it is difficult to realize high threshold
What is be worth is enhanced, while side wall is not steep；Hydrogen is passivated the hydrogen ion for needing higher-energy and density, is easy to produce damage, increases
OFF state electric leakage, to increase loss.Therefore it needs to provide a kind of new enhanced to realize based on the technical solution of p- (Al) GaN
HEMT。
Utility model content
The main purpose of the utility model is to provide a kind of enhanced HEMT device of p-type grid and preparation method thereof, with gram
Take the deficiencies in the prior art.
For the aforementioned purpose of utility model of realization, the technical solution adopted in the utility model includes:
The utility model embodiment provides a kind of production method of enhanced HEMT device of p-type grid, including makes heterogeneous
The step of grid, source electrode, drain electrode of the step of knot and production and hetero-junctions cooperation；
The hetero-junctions includes the first semiconductor and the second semiconductor, and second semiconductor is formed in the first semiconductor
On, and second semiconductor has the band gap for being wider than the first semiconductor, is formed with two-dimensional electron gas in the hetero-junctions；And
The production method further include:
Third semiconductor is formed on the hetero-junctions；
If region is first area under the grid of the third semiconductor, remaining region is second area, and will be distributed over the
The part third semiconductor etching in two regions removes, and the thickness of third semiconductor in second area is made to be less than third in first area
The thickness of semiconductor；
The 4th semiconductor is converted by the third semiconductor in second area, the 4th semiconductor is high-resistance semi-conductor,
And retain the third semiconductor for being located at first area, the two-dimensional electron gas in region under grid in the hetero-junctions to be exhausted.
The utility model embodiment is also provided by the p-type of the production method production of the enhanced HEMT device of p-type grid
The enhanced HEMT device of grid.
The utility model embodiment additionally provides a kind of enhanced HEMT device of p-type grid comprising:
Hetero-junctions, including the first semiconductor and the second semiconductor being formed on the first semiconductor, second semiconductor
Two-dimensional electron gas is formed with the band gap for being wider than the first semiconductor, and in the hetero-junctions；
The p-type semiconductor and high-resistance semi-conductor being formed on the hetero-junctions；And
Source electrode, drain and gate；The source electrode, drain electrode and hetero-junctions form Ohmic contact, and the p-type semiconductor is located at grid
It lower region and is connect with grid, the p-type semiconductor is used to exhaust the two-dimensional electron gas in region under grid, the high-resistance semi-conductor position
In p-type semiconductor and source electrode, drain electrode between any one, and the thickness of the high-resistance semi-conductor is less than the thickness of p-type semiconductor；
The source electrode can be electrically connected with drain electrode by the two-dimensional electron gas.
Compared with prior art, include: the advantages of the utility model
1) enhanced HEMT device of p-type grid provided by the embodiment of the utility model and preparation method thereof can effectively realize increasing
Strong type HEMT；
2) it does not need region under the grid to device to perform etching, avoids uniformity, the repeatability because etching technics introduces
With introducing damage problem, technology controlling and process difficulty is solved the problems, such as；
3) simple process does not need secondary epitaxy；
4) partial etching is carried out to the active area other than region under device gate, reduces damage, interfacial state, current collapse problem
It is effectively improved；
5) remainder after the p-type semiconductor etching other than region under device gate is passivated, required ion energy
Reduce, OFF state leakage reduction small to material damage, loss reduces, and breakdown voltage improves；
6) remainder after the p-type semiconductor etching other than region under device gate is passivated, required ion energy
Reduce, the ion for being injected into AlGaN barrier region is reduced, and saturation current increases；
7) high resistant GaN cap thickness is less than the thickness of the p-type semiconductor in region under grid, and polarity effect weakens, saturation electricity
Stream increases.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of the enhanced HEMT device of partial etching p-GaN in the prior art；
Fig. 2 is a kind of structural schematic diagram of the enhanced HEMT device of selection region extension p-GaN in the prior art；
Fig. 3 is a kind of structural schematic diagram of the enhanced HEMT device of hydrogen passivation p-GaN in the prior art；
Fig. 4 is a kind of structural schematic diagram of the enhanced HEMT device of p-type grid in one exemplary embodiments of the utility model；
Fig. 5 is a kind of production method step (1) production of the enhanced HEMT device of p-type grid in the utility model embodiment 1
The structural schematic diagram of the epitaxial structure of formation；
Fig. 6 is a kind of production method step (2) etching of the enhanced HEMT device of p-type grid in the utility model embodiment 1
Fall source, drain region p-GaN after device architecture schematic diagram；
Fig. 7 is a kind of production method step (3) production of the enhanced HEMT device of p-type grid in the utility model embodiment 1
Device architecture schematic diagram after forming source electrode, drain electrode；
Fig. 8 be in the utility model embodiment 1 a kind of production method step (4) of the enhanced HEMT device of p-type grid to grid
P-GaN between any one in pole and source electrode, drain electrode carries out the device architecture schematic diagram after reduction processing；
Fig. 9 be in the utility model embodiment 1 a kind of production method step (5) of the enhanced HEMT device of p-type grid by grid
P-GaN between any one in pole and source electrode, drain electrode forms the device architecture schematic diagram after high resistant GaN after being passivated processing；
Figure 10 is the enhanced HEMT device of one of the utility model embodiment 1 or embodiment 3 p-type grid and comparative example 1
In the enhanced HEMT device of p-type grid saturation current contrast test figure；
Figure 11 is the enhanced HEMT device of one of the utility model embodiment 1 or embodiment 3 p-type grid and comparative example 1
In the enhanced HEMT device of p-type grid OFF state leaky contrast test figure.
Specific embodiment
In view of deficiency in the prior art, inventor is studied for a long period of time and is largely practiced, and is able to propose that this is practical new
The technical solution of type.The technical solution, its implementation process and principle etc. will be further explained as follows.
The utility model embodiment additionally provides a kind of enhanced HEMT device of p-type grid comprising:
Hetero-junctions, including the first semiconductor and the second semiconductor being formed on the first semiconductor, second semiconductor
Two-dimensional electron gas is formed with the band gap for being wider than the first semiconductor, and in the hetero-junctions；
The p-type semiconductor and high-resistance semi-conductor being formed on the hetero-junctions；And
Source electrode, drain and gate；The source electrode, drain electrode and hetero-junctions form Ohmic contact, and the p-type semiconductor is located at grid
It lower region and is connect with grid, the p-type semiconductor is used to exhaust the two-dimensional electron gas in region under grid, the high-resistance semi-conductor position
In p-type semiconductor and source electrode, drain electrode between any one, and the thickness of the high-resistance semi-conductor is less than the thickness of p-type semiconductor；
The source electrode can be electrically connected with drain electrode by the two-dimensional electron gas.
Further, first semiconductor and the second semiconductor equalizing are selected from III group-III nitride.
Preferably, first semiconductor material includes GaN, but not limited to this.
Preferably, the material of second semiconductor includes any one in AlGaN, AlInN, but not limited to this.
Preferably, the hetero-junctions with a thickness of 10nm-10 μm.
Further, the material of the p-type semiconductor includes p-GaN, appointing in p-AlGaN, p-type diamond and p-NiO
It anticipates one kind, but not limited to this.
Preferably, the p-type semiconductor with a thickness of 10nm-1 μm.
Further, the material of the high-resistance semi-conductor includes high resistant GaN, high resistant AlGaN, high resistant diamond and high resistant
Any one in NiO, but not limited to this.
Preferably, the high-resistance semi-conductor with a thickness of 9nm-999nm.
Further, the p-type semiconductor is wholely set with high-resistance semi-conductor.
Preferably, the high-resistance semi-conductor is infused by p-type semiconductor through hydrogen plasma process, hydrogen ion injection, p-type impurity
Any one the mode processing entered in compensation is formed；Alternatively, the p-type semiconductor is infused by high-resistance semi-conductor through localized p-type impurity
Enter, any one mode processing in low-energy electron beam radiation is formed.
In some more specific embodiments, insertion is also formed between first semiconductor and the second semiconductor
Layer.
Preferably, the material of the insert layer includes InGaN or AlN, but not limited to this.
In some more specific embodiments, the hetero-junctions is formed on the buffer layer, the buffer layer formed with
On substrate.
Further, the material of the buffer layer includes high resistant GaN or high resistant AlGaN, but not limited to this.
Preferably, the buffer layer with a thickness of 100nm-1mm.
Further, the material of the substrate includes any one in Si, SiC, sapphire and GaN, but not limited to this.
Preferably, the substrate with a thickness of 100 μm of -10mm.
The utility model embodiment provides a kind of production method of enhanced HEMT device of p-type grid, including makes heterogeneous
The step of grid, source electrode, drain electrode of the step of knot and production and hetero-junctions cooperation；
The hetero-junctions includes the first semiconductor and the second semiconductor, and second semiconductor is formed in the first semiconductor
On, and second semiconductor has the band gap for being wider than the first semiconductor, is formed with two-dimensional electron gas in the hetero-junctions；And
The production method further include:
Third semiconductor is formed on the hetero-junctions；
If region is first area under the grid of the third semiconductor, remaining region is second area, and will be distributed over the
The part third semiconductor etching in two regions removes, and the thickness of third semiconductor in second area is made to be less than third in first area
The thickness of semiconductor；
The 4th semiconductor is converted by the third semiconductor in second area, the 4th semiconductor is high-resistance semi-conductor,
And retain the third semiconductor for being located at first area, the two-dimensional electron gas in region under grid in the hetero-junctions to be exhausted,
Alternatively, retaining the third semiconductor for being located at second area, the third semiconductor is high-resistance semi-conductor, and by first
Third semiconductor in region is converted into the 4th semiconductor, to by the Two-dimensional electron gas consumption in region under grid in the hetero-junctions
To the greatest extent.
In some more specific embodiments, the production method further include: institute is formed on the hetero-junctions
After stating third semiconductor, grid is made on the first area of the third semiconductor, later by the third in second area half
Conductor transition is the 4th semiconductor.
In some more specific embodiments, the production method further include: by the of the second area
After three semiconductors are converted into the 4th semiconductor, grid is made on the third semiconductor for remaining in first area.
Further, the production method includes: at least using hydrogen plasma process, hydrogen ion injection, p-type impurity
The third semiconductor of the second area is converted the 4th semiconductor by any one mode in injecting compensating；Alternatively, at least
The third semiconductor of the first area is converted using any one mode in n-type impurity injection, low-energy electron beam radiation
For the 4th semiconductor.
Further, the third semiconductor is p-type semiconductor, and the 4th semiconductor is high-resistance semi-conductor；Alternatively, described
Three semiconductors are high-resistance semi-conductor, and the 4th semiconductor is p-type semiconductor.
Preferably, the material of the p-type semiconductor includes p-GaN, any in p-AlGaN, p-type diamond and p-NiO
One kind, but not limited to this.
The material of the high-resistance semi-conductor includes any in high resistant GaN, high resistant AlGaN, high resistant diamond and high resistant NiO
One kind, but not limited to this.
Further, positioned at first area third semiconductor with a thickness of 10nm-1 μm, positioned at the third of second area
Semiconductor with a thickness of 9nm-999nm；
Further, the production method includes: at least using reactive ion etching, plasma etching, inductive coupling
Any one mode after plasma etching, physical bombardment, wet etching, initial oxidation in wet etching will be distributed over the secondth area
The part third semiconductor etching in domain removes.
The utility model embodiment is additionally provided by the enhanced HEMT device of p-type grid of the production method production.
In some more specific embodiments, the production method includes:
Form p-type semiconductor on the hetero-junctions, and to region under non-grid (under non-grid region be aforementioned second area or
Person part second area) p-type semiconductor carry out reduction processing (general using etch by the way of reduction processing) so that under non-grid
The thickness of the p-type semiconductor in region is less than the thickness of region (region, that is, first area under grid) p-type semiconductor under grid, later with hydrogen
Corona treatment, hydrogen ion inject, any one mode in p-type impurity injecting compensating partly leads the p-type in region under non-grid
Body is handled, to form the high-resistance semi-conductor；Alternatively, forming high-resistance semi-conductor on the hetero-junctions, and to non-grid
The high-resistance semi-conductor in lower region carries out reduction processing, so that the thickness of the high-resistance semi-conductor in region is less than region under grid under non-grid
The thickness of high-resistance semi-conductor, later to the area Shan Xia in a manner of any one in the injection of localized p-type impurity, low-energy electron beam radiation
The high-resistance semi-conductor in domain is handled, to form the p-type semiconductor；
And the high-resistance semi-conductor of source electrode, drain region is removed in a manner of dry etching or wet etching, it carries out later
The production of source electrode, drain and gate.
In some more specific embodiments, the mode that reduction processing is carried out to p-type semiconductor includes reactive ion
After etching, plasma etching, inductively coupled plasma etching, physical bombardment, wet etching, initial oxidation in wet etching
Any one.
The utility model embodiment is also provided by the p-type of the production method production of the enhanced HEMT device of p-type grid
The enhanced HEMT device of grid.As Vgs < Vth, the p-type semiconductor under gate electrode G be can be improved at AlGaN/GaN interface-channel
On potential barrier to fermi level, the high concentration two-dimensional electron gas under grid is exhausted, device is not turned on；And as Vgs > Vth, dielectric layer
The voltage being added on gate electrode G can be made to pass through electric field form to modulate, reach AlGaN/GaN Quantum Well below gate electrode G
The height of fermi level restores the two-dimensional electron gas of high concentration, break-over of device.
It as follows will be further to works such as the technical solution, its implementation process and principles in conjunction with attached drawing and specific embodiment
It illustrates, and, source electrode, that is, source electrode described in the utility model, drain electrode are drain electrode, grid, that is, gate electrode, the grid
Lower region, the corresponding region of the equal finger grid of area of grid, region, the equal finger grid corresponding region of non-area of grid under the non-grid
Except region, the corresponding region of source region finger source electrode, the corresponding region of drain region, that is, drain electrode.
Referring to Fig. 4, in some more specific embodiments, a kind of enhanced HEMT device of p-type grid be can wrap
Include: substrate 5, the buffer layer 6 being formed on substrate 5, (AlGaN/GaN is different for the AlGaN/GaN hetero-junctions being formed on buffer layer 6
Matter knot includes GaN 1 and the AlGaN 2 that is formed on GaN 1), the p-GaN 3 and height that are formed on AlGaN/GaN hetero-junctions
Two-dimensional electron gas 2DEG, institute are formed in resistance GaN 4 and source electrode S, drain electrode D and gate electrode G, AlGaN/GaN hetero-junctions
It states source electrode S, drain electrode D and hetero-junctions forms Ohmic contact, and source electrode S and drain electrode D can pass through two-dimensional electron gas
2DEG electrical connection；P-GaN is located at region under grid and connect with gate electrode G, and p-GaN is used to exhaust the two-dimensional electron gas in region under grid
2DEG, high resistant GaN 4 are located between any one in p-GaN 3 and source S, drain D, and the thickness of high resistant GaN 4 is less than p-GaN
3 thickness.As Vgs < Vth, potential barrier is can be improved at AlGaN/GaN interface-channel to Fermi in the p-type semiconductor under gate electrode G
On energy level, the high concentration two-dimensional electron gas under grid is exhausted, device is not turned on；And as Vgs > Vth, dielectric layer can make to be added in
Voltage on gate electrode G is modulated by electric field form, and AlGaN/GaN Quantum Well below gate electrode G is made to reach fermi level
Highly, restore the two-dimensional electron gas of high concentration, break-over of device.
In some more specific embodiments, a kind of production method of the enhanced HEMT device of p-type grid may include
Following steps:
1) outside using Metal Organic Chemical Vapor Deposition (MOCVD), hydride gas-phase epitaxy (HVPE), molecular beam
Prolong the technology growths substrate/buffer layer/III nitride heterostructure/p-type semiconductor such as (MBE) or pulse laser deposition (PLD)
Epitaxial structure；Substrate can select Si, SiC, sapphire or GaN etc., substrate with a thickness of 100 μm of -10mm；Buffer layer can
To select high resistant GaN, AlGaN etc., buffer layer with a thickness of 100nm-1mm；III nitride heterostructure can be AlGaN/
GaN heterojunction structure, AlInN/GaN heterojunction structure, AlGaN/InGaN/GaN heterojunction structure, AlGaN/AlN/GaN heterojunction structure
Deng；III race's elemental constituent content of ternary semiconductor one of which can be from 0 to 1 in III nitride heterostructure；Ⅲ
Nitride heterostructure with a thickness of 10nm-10 μm, p-type semiconductor can select p-GaN, p-AlGaN, p-type diamond, p-
The p-type semiconductor materials such as NiO, with a thickness of 10nm-1 μm；
2) dry etchings or the wet etch techniques such as oxygen plasma, reactive ion etching, ion beam etching, removal are utilized
P-GaN (or p-AlGaN, p-type diamond, the p-type semiconductors such as p-NiO of ohmic area (i.e. source region and drain region)
Material), the technologies such as etch areas can be shifted by photoetching or exposure mask are determined；
3) using metal deposition techniques such as electron beam evaporation or sputterings, source electrode S and drain electrode D is made in ohmic area；
4) dry etchings or the wet etch techniques such as oxygen plasma, reactive ion etching, ion beam etching, removal are utilized
P-GaN (or p-AlGaN, p-type diamond, the p-type semiconductor materials such as p-NiO) under the grid of part outside region, etch thicknesses can
Think 1nm-999nm；Etch areas can be determined by the technologies such as photoetching or exposure mask transfer；
5) remaining p-GaN (or p-AlGaN, p-type diamond, the p such as p-NiO will be etched under grid outside region by processing
Type semiconductor material) passivation, form high-resistance semi-conductor；Specifically, H plasma treatment, hydrogen ion can be used for p-type GaN
The modes such as injection, p-type impurity injecting compensating, for p-AlGaN, p-type diamond, the p-type semiconductor materials such as p-NiO can be used
The modes such as p-type impurity injecting compensating；Processing region can be determined by the technologies such as photoetching or exposure mask transfer；
6) using the metal deposition techniques such as electron beam evaporation or sputtering, in p-GaN (or p-AlGaN, p-type diamond, p-
The p-type semiconductor materials such as NiO) production gate electrode G, the region gate electrode G can be carried out true by the technologies such as photoetching or exposure mask transfer
It is fixed.
Embodiment 1
A kind of production method of the enhanced HEMT device of p-type grid, includes the following steps:
1) epitaxial structure as shown in Figure 5 is grown by the way of Metal Organic Chemical Vapor Deposition (MOCVD)；
Substrate 6 selects Si, and with a thickness of 400 μm, buffer layer 5 selects high resistant GaN, with a thickness of 4200nm, in AlGaN/GaN heterojunction structure
GaN with a thickness of 260nm, AlGaN 2 with a thickness of 18nm, in AlGaN the content of Al component be 18%, p-GaN 3 with a thickness of
70nm；
2) p-GaN of source region and drain region, device architecture such as Fig. 6 after etching are removed using plasma etching
It is shown；Etch areas can determine that photoetching specific steps include pretreatment, spin coating, front baking, exposure and imaging by photoetching；
3) using electron beam evaporation in source region and drain region depositing Ti/Al/Ni/Au, as source electrode S and electric leakage
Pole D, the device architecture made after forming source electrode and drain electrode are as shown in Figure 7；Etching in the deposition region Ti/Al/Ni/Au and step 2)
Area coincidence does not need repetition photoetching and determines region；Wherein Ti/Al/Ni/Au refer to the Ti layer being stacked, Al layers, Ni layers and
Au layers；
4) using plasma etching between any one in grid and source electrode, drain electrode (or can be area of grid with
Between any one in source region, drain region, or be also believed that be region under non-grid) p-GaN carry out reduction processing,
It can remove the p-GaN of 1nm-999nm, selection removes the p-GaN of 30nm thickness, the device architecture after reduction processing in the present embodiment
As shown in Figure 8；Etch areas can determine that photoetching specific steps include pre-processing, spin coating, front baking by photoetching, expose and aobvious
Shadow；
5) processing is passivated to the p-GaN after reduction processing in the way of hydrogen plasma process, to form height
GaN is hindered, the device architecture after Passivation Treatment is as shown in Figure 9；The region of hydrogen plasma process can be determining by photoetching, photoetching
Specific steps include pretreatment, spin coating, front baking, exposure and imaging；
6) deposited on the p-GaN in region under grid by the way of electron beam evaporation Ni/Au (the Ni layer that is stacked with
Au layers), as gate electrode G, the device architecture made after forming gate electrode (i.e. grid) is as shown in Figure 4；Gate electrode region is really
Surely it can use photoetching technique, the specific steps of photoetching include pretreatment, spin coating, front baking, exposure and imaging.
Embodiment 2
A kind of production method of the enhanced HEMT device of p-type grid, includes the following steps:
1) growth substrates/buffer layer/AlGaN/ by the way of Metal Organic Chemical Vapor Deposition (MOCVD)
GaN heterojunction structure/high resistant GaN epitaxial structure；Substrate selects Si, and with a thickness of 400 μm, buffer layer selects high resistant GaN, with a thickness of
GaN is in 4200nm, AlGaN/GaN heterojunction structure with a thickness of 260nm, and AlGaN is with a thickness of 18nm, the content of Al component in AlGaN
Be 18%, high resistant GaN with a thickness of 70nm；
2) using the high resistant GaN of plasma etching removal source region and drain region, etch areas can pass through light
It carves and determines, photoetching specific steps include pretreatment, spin coating, front baking, exposure and imaging；
3) using electron beam evaporation in source region and drain region depositing Ti/Al/Ni/Au, as source electrode S and electric leakage
The deposition region pole D, Ti/Al/Ni/Au is overlapped with etch areas in step 2), is not needed repetition photoetching and is determined region；Wherein Ti/
Al/Ni/Au refers to the Ti layer being stacked, Al layers, Ni layers and Au layers；
4) (or area of grid and source region, drain region be can be between any one in grid and source electrode, drain electrode
In between any one, or being also believed that is region under non-grid) high resistant GaN carry out reduction processing, remove the height of 30nm thickness
Hinder GaN；
5) high resistant GaN in region under in a manner of any one in the injection of localized p-type impurity, low-energy electron beam radiation to grid
It is handled, to form p-GaN；
6) deposited on the p-GaN in region under grid by the way of electron beam evaporation Ni/Au (the Ni layer that is stacked with
Au layers), as gate electrode G, the device architecture made after forming gate electrode (i.e. grid) is as shown in Figure 4；Gate electrode region is really
Surely it can use photoetching technique, the specific steps of photoetching include pretreatment, spin coating, front baking, exposure and imaging.
Embodiment 3
The production method and the production method basic one in embodiment 1 of the enhanced HEMT device of p-type grid in the present embodiment
It causes, the difference is that preparation is formed after source electrode, drain electrode, can first prepare gate electrode, use etching technics pair later
P-GaN between any one in gate electrode and source electrode, drain electrode carries out reduction processing, finally again to the p- after reduction processing
GaN is passivated processing and forms high resistant GaN.
Comparative example 1
A kind of enhanced HEMT device of p-type grid is as shown in figure 3, comprising: substrate, form buffer layer on substrate, shape
At AlGaN/GaN hetero-junctions on the buffer layer, the p-GaN and high resistant GaN that are formed on AlGaN/GaN hetero-junctions, Yi Jiyuan
Two-dimensional electron gas 2DEG, the source electrode S, electric leakage are formed in electrode S, drain electrode D and gate electrode G, AlGaN/GaN hetero-junctions
Pole D and hetero-junctions form Ohmic contact, and source electrode S and drain electrode D can be electrically connected by two-dimensional electron gas 2DEG；p-GaN
It region and is connect with gate electrode G under grid, p-GaN is used to exhaust the two-dimensional electron gas 2DEG in region under grid, and high resistant GaN is located at
Between any one in p-GaN and source electrode, drain electrode, and the thickness of high resistant GaN is equal with the thickness of p-GaN.
To the enhanced HEMT device of p-type grid in utility model embodiment 1 or embodiment 3 and the p-type grid in comparative example 1
The saturation current and OFF state drain conditions of enhanced HEMT device are tested, and test result difference is as shown in Figure 10, Figure 11；
Base is by the enhanced HEMT device of p-type grid provided by the embodiment of the utility model compared to the enhanced HEMT of p-type grid in comparative example 1
The saturation current of device significantly improves, and significantly reduces OFF state leaky.
The device manufacture method that the utility model previous embodiment provides can effectively realize enhanced HEMT, technique letter
It is single, do not need secondary epitaxy, do not need region under the grid to device yet and perform etching, avoid because etching technics introduce it is uniform
Property, repeatability and introduce damage problem, solves the problems, such as that technology controlling and process is difficult, while by having other than region under device gate
Source region carries out partial etching, reduces damage, and interfacial state, current collapse problem are effectively improved, and by under device gate
The remainder after p-type semiconductor etching other than region is passivated, and required ion energy reduces, small to material damage, is closed
State leakage reduction, loss reduce, and breakdown voltage improves, and the ion for being injected into AlGaN barrier region is reduced, saturation current
Increase；In addition, high resistant GaN cap thickness is less than the thickness of the p-type semiconductor in region under grid, polarity effect weakens, saturation electricity
Stream increases.
It should be appreciated that above-described embodiment is only to illustrate the technical ideas and features of the present invention, it is ripe its object is to allow
The personage for knowing technique can understand the content of the utility model and implement accordingly, can not limit the utility model with this
Protection scope.All equivalent change or modifications according to made by the spirit of the present invention essence, should all cover in the utility model
Within protection scope.
Claims (18)
1. a kind of enhanced HEMT device of p-type grid, characterized by comprising:
Hetero-junctions, including the first semiconductor and the second semiconductor being formed on the first semiconductor, second semiconductor has
It is wider than the band gap of the first semiconductor, and is formed with two-dimensional electron gas in the hetero-junctions；
The p-type semiconductor and high-resistance semi-conductor being formed on the hetero-junctions；And
Source electrode, drain and gate；The source electrode, drain electrode and hetero-junctions form Ohmic contact, and the p-type semiconductor is located at the area Shan Xia
It domain and is connect with grid, the p-type semiconductor is used to exhaust the two-dimensional electron gas in region under grid, and the high-resistance semi-conductor is located at p
Between any one in type semiconductor and source electrode, drain electrode, and the thickness of the high-resistance semi-conductor is less than the thickness of p-type semiconductor；
The source electrode can be electrically connected with drain electrode by the two-dimensional electron gas.
2. the enhanced HEMT device of p-type grid according to claim 1, it is characterised in that: the p-type semiconductor and high resistant half
Conductor is wholely set.
3. the enhanced HEMT device of p-type grid according to claim 2, it is characterised in that: the high-resistance semi-conductor is by p-type half
Conductor is formed through any one mode processing in hydrogen plasma process, hydrogen ion injection, p-type impurity injecting compensating.
4. the enhanced HEMT device of p-type grid according to claim 2, it is characterised in that: the p-type semiconductor is by high resistant half
Conductor is injected through localized p-type impurity, any one mode processing in low-energy electron beam radiation is formed.
5. the enhanced HEMT device of p-type grid according to claim 1, it is characterised in that: the material packet of the p-type semiconductor
P-GaN is included, any one in p-AlGaN, p-type diamond and p-NiO.
6. the enhanced HEMT device of p-type grid according to claim 1, it is characterised in that: the material of the high-resistance semi-conductor
Including any one in high resistant GaN, high resistant AlGaN, high resistant diamond and high resistant NiO.
7. the enhanced HEMT device of p-type grid according to claim 1, it is characterised in that: the p-type semiconductor with a thickness of
10 nm-1 μm, the high-resistance semi-conductor with a thickness of 9 nm-999 nm.
8. the enhanced HEMT device of p-type grid according to claim 1, it is characterised in that: first semiconductor and second
Semiconductor equalizing is selected from III group-III nitride.
9. the enhanced HEMT device of p-type grid according to claim 8, it is characterised in that: the first semiconductor material packet
Include GaN.
10. the enhanced HEMT device of p-type grid according to claim 8, it is characterised in that: the material of second semiconductor
Including any one in AlGaN, AlInN.
11. the enhanced HEMT device of p-type grid according to claim 1, it is characterised in that: the hetero-junctions with a thickness of 10
nm-10 μm。
12. the enhanced HEMT device of p-type grid according to claim 1, it is characterised in that: first semiconductor and second
Insert layer is also formed between semiconductor.
13. the enhanced HEMT device of p-type grid according to claim 12, it is characterised in that: the material packet of the insert layer
Include InGaN or AlN.
14. the enhanced HEMT device of p-type grid according to claim 1, it is characterised in that: the hetero-junctions is formed in buffering
On layer, in the buffer layer formation and substrate.
15. the enhanced HEMT device of p-type grid according to claim 14, it is characterised in that: the material packet of the buffer layer
Include high resistant GaN or high resistant AlGaN.
16. the enhanced HEMT device of p-type grid according to claim 14, it is characterised in that: the buffer layer with a thickness of
100 nm-1 mm。
17. the enhanced HEMT device of p-type grid according to claim 14, it is characterised in that: the material of the substrate includes
Any one in Si, SiC, sapphire and GaN.
18. the enhanced HEMT device of p-type grid according to claim 14, it is characterised in that: the substrate with a thickness of 100
μm-10 mm。
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108962752A (en) * | 2018-09-04 | 2018-12-07 | 苏州能屋电子科技有限公司 | Enhanced HEMT device of p-type grid and preparation method thereof |
| WO2023273900A1 (en) * | 2021-06-29 | 2023-01-05 | 北京大学 | Low-dynamic-resistance enhanced gan device |
| WO2024092544A1 (en) * | 2022-11-02 | 2024-05-10 | Innoscience (Zhuhai) Technology Co., Ltd. | Nitride-based semiconductor device and method for manufacturing thereof |
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2018
- 2018-09-04 CN CN201821443359.6U patent/CN208819832U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108962752A (en) * | 2018-09-04 | 2018-12-07 | 苏州能屋电子科技有限公司 | Enhanced HEMT device of p-type grid and preparation method thereof |
| WO2023273900A1 (en) * | 2021-06-29 | 2023-01-05 | 北京大学 | Low-dynamic-resistance enhanced gan device |
| WO2024092544A1 (en) * | 2022-11-02 | 2024-05-10 | Innoscience (Zhuhai) Technology Co., Ltd. | Nitride-based semiconductor device and method for manufacturing thereof |
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