CN208637425U

CN208637425U - Preparation laminated structure of semiconductor memory capacitor hole

Info

Publication number: CN208637425U
Application number: CN201820970453.0U
Authority: CN
Inventors: 不公告发明人
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2018-06-22
Filing date: 2018-06-22
Publication date: 2019-03-22
Anticipated expiration: 2028-06-22

Abstract

The utility model provides a preparation laminated structure in semiconductor memory capacitor hole, include: a semiconductor substrate; the capacitor supports the sacrifice structure layer; the hard mask consumption layer is positioned on the surface of the capacitor supporting sacrificial structure layer; the double-pattern integration layer is positioned on the surface of the hard mask consumption layer; the pattern transfer layer is positioned on the double-pattern integration layer and comprises a plurality of first pitch multiplication units which are arranged in parallel at intervals along a first direction and a plurality of second pitch multiplication units which are arranged in parallel at intervals along a second direction, an intersection angle is formed between the second direction and the first direction, a first pitch is generated between every two adjacent first pitch multiplication units, and a second pitch is generated between every two adjacent second pitch multiplication units. The utility model discloses utilize two directions to form the lateral wall layer respectively and carry out the figure and double, improve the definition of characteristic dimension in the device structure, solve the problem of big or small hole to through the improvement on the two pattern integration layers in the sculpture process, improve the figure precision, improve the structural layer, improve the yield.

Description

Semiconductor memory capacitor hole prepares laminated construction

Technical field

The utility model belongs to semiconductor device processing technology field, more particularly to a kind of semiconductor memory capacitor hole Prepare laminated construction.

Background technique

Dynamic RAM (Dynamic Random Access Memory, referred to as: DRAM) is commonly used in computer Semiconductor storage unit, be made of many duplicate storage units.Each storage unit generally includes capacitor and transistor； The grid of transistor is connected with wordline, the drain/source of transistor is connected with bit line, the source/drain and capacitor of transistor It is connected；Voltage signal in wordline can control opening or closing for transistor, and then be stored in capacitor by bit line reading In data information, or data information is written in capacitor by bit line and is stored.

With the development of semicon industry, many factors (comprising in modern electronic equipment to the portability of raising, calculate energy The demand of power, memory capacity and energy efficiency), the size of integrated circuit constantly reduces.Reduce to facilitate this size, after The method that continuous research reduces the size of the component characteristic of integrated circuit, the example of above-mentioned composition characteristic include capacitor, electric contact, Interconnection line and other electric devices etc..Reduce characteristic size trend be in memory circuit or device very it will be evident that Wherein, memory circuit or device are, for example, dynamic RAM (DRAM) or Static RAM (SRAM) etc..

Higher and higher to the continuous demand for reducing characteristic size, the technology that mutually reply is used to form the feature claims Also higher and higher, in addition, the concept of spacing can be used for describing the size of these features, spacing is identical in two adjacent features Point the distance between.Currently, certain photo anti-corrosion agent materials only make a response to certain wavelength, a kind of workable common wave Long range is ultraviolet light (UV) range, because many photo anti-corrosion agent materials selectivity makes a response to specific wavelength, Photoetching technique each all has minimum spacing, however, in the minimum spacing hereinafter, specific photoetching technique cannot be reliable Formation feature, this minimum spacing with the optical wavelength being used together usually by that can determine, therefore, the minimum of photoetching technique Spacing may the reduction of limited features size.Therefore, it is necessary to reduce the size of integrated circuit and increase electrical on computer chip Apparatus array can operational densities, it is desirable to provide form the improved method of smaller feature, for increasing the improved of characteristic density Method by the method for generating more efficient array and will provide the skill of more compact array in the case where not characteristic of damage resolution Art.

Therefore, how to provide a kind of semiconductor memory capacitor hole prepares laminated construction, in the prior art to solve The above problem is necessary.

Utility model content

In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of semiconductor memory electricity Hold hole and prepare laminated construction, be difficult to prepare for solving size in the prior art miniature semiconductor structure, size it is uneven The problems such as even figure is not accurate and there are sidewall features size holes.

In order to achieve the above objects and other related objects, the utility model provides a kind of system in semiconductor memory capacitor hole Standby laminated construction, comprising:

Semiconductor base；

Structure sheaf is sacrificed in capacitor support, at least one layer of Jie including etching barrier layer and on the etching barrier layer Matter sacrificial layer and at least one layer of supporting layer, and the etching barrier layer is located at the surface of the semiconductor base；

Hard exposure mask exhaustion layer is located at capacitor support and sacrifices structure layer surface；

Double patterning conformable layer is located at the hard exposure mask and consumes layer surface；And

Pattern transfer layer is located on the double patterning conformable layer, including several along the arrangement of first direction parallel interval First pitch-multiplied unit and several in a second direction parallel interval arrange and be connected with the described first pitch-multiplied unit The second pitch-multiplied unit, there is an angle of intersection, and adjacent described the between the second direction and the first direction One first spacing is generated between one pitch-multiplied unit, generates one second spacing between the adjacent second pitch-multiplied unit, First spacing and second spacing are all defined by the thickness of respective intervals sacrificial layer.

Further include one first graphic mask duplicating layer as a kind of preferred embodiment of the utility model, is used to form described First pitch-multiplied unit, wherein the first graphic mask duplicating layer includes the first pattern of several parallel intervals arrangement Unit and several second pattern units between adjacent first pattern unit, second pattern unit include First bottom deposit layer and the first top deposited layer on the first bottom deposit layer, and the adjacent first pattern list First spacing between second pattern unit and the thickness of the first bottom deposit layer are generally in identical.

Further include a second graph exposure mask duplicating layer as a kind of preferred embodiment of the utility model, is used to form described Second pitch-multiplied unit, wherein the second graph exposure mask duplicating layer includes the third pattern of several parallel intervals arrangement Unit and several the 4th pattern units between the adjacent third pattern unit, the 4th pattern unit include Second bottom deposit layer and the second top deposited layer on the second bottom deposit layer, and the adjacent third pattern list The thickness of first spacing between the 4th pattern unit and the second bottom deposit layer is generally in identical.

As a kind of preferred embodiment of the utility model, the dielectric layer includes that first medium sacrificial layer, second medium are sacrificial Domestic animal layer and third medium sacrificial layer, the supporting layer include the first supporting layer and the second supporting layer, wherein the first medium is sacrificial Domestic animal layer, the second medium sacrificial layer, first supporting layer, the third medium sacrificial layer and second supporting layer are under It is sequentially stacked on and.

As a kind of preferred embodiment of the utility model, the angle of intersection includes 60 °；The first pitch-multiplied unit Equally parallel interval is arranged, and the second pitch-multiplied unit equally arrange by parallel interval；First spacing times The width for increasing unit is equal with the width of the described second pitch-multiplied unit；The width of first spacing and second spacing It is equal.

As a kind of preferred embodiment of the utility model, the double patterning conformable layer successively includes the first pad from bottom to top Layer, the second bed course, third bed course and the 4th bed course.

As a kind of preferred embodiment of the utility model, first bed course is selected from silicon oxide layer and ethyl orthosilicate (TEOS) any one in layer, second bed course are any in amorphous silicon layer, silicon oxynitride layer and silicon nitride layer One kind, any one of the third bed course in silicon oxide layer and ethyl orthosilicate (TEOS) layer, the 4th bed course Any one in amorphous silicon layer, silicon oxynitride layer and silicon nitride layer.

Further include a pattern transfer hard mask layer as a kind of preferred embodiment of the utility model, is used for transition diagram shape At at least one of the described first pitch-multiplied unit and the second pitch-multiplied unit, wherein the pattern transfer is hard Mask layer includes that can be ashed at least one of hard mask layer (AHM) and DLC film layer (DLC).

As a kind of preferred embodiment of the utility model, structure sheaf is sacrificed in the capacitor support has several uniform intervals The semiconductor memory capacitor hole of arrangement.

As described above, the preparation method in the semiconductor memory capacitor hole of the utility model, has the advantages that

The utility model based on being respectively formed side wall using both direction in pitch-multiplied semiconductor structure layer preparation Layer (spacer) carries out figure and doubles, and is based on this pitch doubling technique, it is micro- can to reach figure in 30nm and following processing procedure Contracting, further, the utility model pass through the size of twocouese in control preparation process, to reach the good of doubling range interval figure Uniformity is further improved characteristic size in device architecture and is defined, solve the problems, such as big small holes, and pass through etching process The improvement of middle double patterning conformable layer carries out figure amendment during the preparation process, figure precision is improved, in addition, the utility model Also structure sheaf is improved, to reach better choice ratio, improves capacitor size defect, improves yield.

Detailed description of the invention

Fig. 1 is shown as the process flow chart of the utility model memory capacitor hole preparation process.

Fig. 2 is shown as providing the structural schematic diagram of semiconductor base in the preparation of the utility model memory capacitor hole.

Fig. 3 be shown as the utility model memory capacitor hole preparation in formed on semiconductor base hard exposure mask exhaustion layer, The structural schematic diagram of first figure migrating layer and the first mask layer.

Fig. 4 is shown as also forming the structural schematic diagram of double patterning conformable layer on the basis of Fig. 3.

Fig. 5 is shown as forming the structural schematic diagram of the first pattern layer in the preparation of the utility model memory capacitor hole.

Fig. 6 is shown as the top view of Fig. 5, and Fig. 5 is shown as the sectional view of the position A-A ' in Fig. 6.

Fig. 7 is shown as forming the structural schematic diagram of the second pattern layer in the preparation of the utility model memory capacitor hole.

Fig. 8 is shown as forming the structural schematic diagram of the first interval sacrificial layer in the preparation of the utility model memory capacitor hole.

Fig. 9 is shown as forming the structural schematic diagram of the first filling mask layer in the preparation of the utility model memory capacitor hole.

Figure 10 is shown as forming the structural schematic diagram of planarization auxiliary layer in the preparation of the utility model memory capacitor hole.

Figure 11 is shown as being planarized to the structural schematic diagram of the second pattern layer in the preparation of the utility model memory capacitor hole.

Figure 12 is shown as forming etching stop layer, stress relief layer, second in the preparation of the utility model memory capacitor hole The structural schematic diagram of figure migrating layer and the second mask layer.

The first direction structure that Figure 13 is shown as being formed third pattern layer in the preparation of the utility model memory capacitor hole is shown It is intended to.

The second direction structure that Figure 14 is shown as being formed third pattern layer in the preparation of the utility model memory capacitor hole is shown It is intended to.

Figure 15 is shown as forming the top view of third pattern layer in the preparation of the utility model memory capacitor hole, wherein figure 13 are shown as the sectional view in the direction A-A ' in Figure 15, and Figure 14 is shown as the sectional view in the direction B-B ' in Figure 15.

The second direction structure that Figure 16 is shown as being formed the 4th pattern layer in the preparation of the utility model memory capacitor hole is shown It is intended to.

The first direction structure that Figure 17 is shown as being formed the 4th pattern layer in the preparation of the utility model memory capacitor hole is shown It is intended to.

Figure 18 is shown as forming the top view of the 4th pattern layer in the preparation of the utility model memory capacitor hole, wherein figure 16 are shown as the sectional view in the direction B-B ' in Figure 18, and Figure 17 is shown as the sectional view in the direction A-A ' in Figure 18.

Figure 19 is shown as forming the structural schematic diagram of the second interval sacrificial layer in the preparation of the utility model memory capacitor hole.

Figure 20 is shown as forming the second filling mask layer second direction structure in the preparation of the utility model memory capacitor hole Diagram.

Figure 21 is shown as forming the second filling mask layer first direction structure in the preparation of the utility model memory capacitor hole Diagram.

Figure 22 is shown as forming the top view of the second filling mask layer in the preparation of the utility model memory capacitor hole, In, Figure 20 is shown as the sectional view in the direction B-B ' in Figure 22, and Figure 21 is shown as the sectional view in the direction A-A ' in Figure 22.

The structure that Figure 23 is shown as being planarized to the second interval sacrificial layer in the preparation of the utility model memory capacitor hole is shown It is intended to.

Figure 24 is shown as forming the structural schematic diagram of the 5th pattern layer in the preparation of the utility model memory capacitor hole.

Figure 25 is shown as the utility model memory capacitor hole and prepares to form relief layer pattern transfer layer second direction structure Diagram.

Figure 26 is shown as the utility model memory capacitor hole and prepares to form relief layer pattern transfer layer first direction structure Diagram.

Figure 27 is shown as forming the top view of relief layer pattern transfer layer in the preparation of the utility model memory capacitor hole, In, Figure 25 is shown as the sectional view in the direction B-B ' in Figure 27, and Figure 26 is shown as the sectional view in the direction A-A ' in Figure 27.

Figure 28 is shown as the utility model memory capacitor hole and prepares the second direction structural diagrams to form pattern transfer layer.

Figure 29 is shown as the utility model memory capacitor hole and prepares the first direction structural diagrams to form pattern transfer layer.

Figure 30 is shown as forming the top view of pattern transfer layer in the preparation of the utility model memory capacitor hole, wherein figure 28 are shown as the sectional view in the direction B-B ' in Figure 30, and Figure 29 is shown as the sectional view in the direction A-A ' in Figure 30.

Figure 31 is shown as the utility model memory capacitor hole and prepares to form the first intermediate pattern transfer layer second direction knot Composition.

Figure 32 is shown as the utility model memory capacitor hole and prepares to form the first intermediate pattern transfer layer first direction knot Composition.

Figure 33 is shown as forming the structural schematic diagram of graphics-optimized sacrificial layer in the preparation of the utility model memory capacitor hole.

Figure 34 is shown as the preparation planarization of the utility model memory capacitor hole and forms the second intermediate pattern transfer layer structure Diagram.

Figure 35 is shown as the structural schematic diagram that the preparation of the utility model memory capacitor hole removes remaining pattern transfer layer.

The structure that Figure 36 is shown as being formed third intermediate pattern transfer layer in the preparation of the utility model memory capacitor hole is shown It is intended to.

Figure 37 is shown as the utility model memory capacitor hole and prepares to form the 4th intermediate pattern transfer layer second direction knot Composition.

Figure 38 is shown as the utility model memory capacitor hole and prepares to form the 4th intermediate pattern transfer layer first direction knot Composition.

Figure 39 is shown as forming the top view of the 4th intermediate pattern transfer layer in the preparation of the utility model memory capacitor hole, Wherein, Figure 37 is shown as the sectional view in the direction B-B ' in Figure 39, and Figure 38 is shown as the sectional view in the direction A-A ' in Figure 39.

Figure 40 is shown as the utility model memory capacitor hole and prepares to form the 5th intermediate pattern transfer layer second direction knot Composition.

Figure 41 is shown as the utility model memory capacitor hole and prepares to form the 5th intermediate pattern transfer layer first direction knot Composition.

Figure 42 is shown as forming the top view of the 5th intermediate pattern transfer layer in the preparation of the utility model memory capacitor hole, Wherein, Figure 40 is shown as the sectional view in the direction B-B ' in Figure 42, and Figure 41 is shown as the sectional view in the direction A-A ' in Figure 42.

Figure 43 is shown as the utility model memory capacitor hole and prepares to form graphical hard exposure mask exhaustion layer second direction knot Composition.

Figure 44 is shown as the utility model memory capacitor hole and prepares to form graphical hard exposure mask exhaustion layer first direction knot Composition.

Figure 45 is shown as forming the top view of graphical hard exposure mask exhaustion layer in the preparation of the utility model memory capacitor hole, Wherein, Figure 43 is shown as the sectional view in the direction B-B ' in Figure 45, and Figure 44 is shown as the sectional view in the direction A-A ' in Figure 45.

Figure 46 is shown as the utility model memory capacitor hole preparation etching capacitor support sacrificial layer and forms memory capacitor Hole pattern.

Figure 47 is shown as removing remaining graphical hard exposure mask exhaustion layer in the preparation of the utility model memory capacitor hole Diagram.

Figure 48 is shown as forming the top view in memory capacitor hole in the preparation of the utility model memory capacitor hole, wherein Figure 47 is shown as the sectional view in the direction A-A ' in Figure 48.

Component label instructions

100 semiconductor bases

101 hard exposure mask exhaustion layers

102 double patterning conformable layers

The first bed course of 102a

The second bed course of 102b

102c third bed course

The 4th bed course of 102d

103 first figure migrating layers

103a underlying graphics transfer layer

The upper layer 103b pattern transfer layer

104 first mask layers

105 first pattern layers

The first pattern unit of 105a

106 second pattern layers

The second pattern unit of 106a

107 first interval sacrificial layers

The first clearance groove of 107a

The first transverse part of 107b

107c first longitudinal direction portion

The second transverse part of 107d

108 first filling mask layers

109 planarization auxiliary layers

110 sizes limit unit

111 pattern auxiliary units

112 etching stop layers

113 stress relief layers

114 second graph migrating layers

115 second mask layers

116 third pattern layers

116a third pattern unit

117 the 4th pattern layers

The 4th pattern unit of 117a

118 second interval sacrificial layers

The second clearance groove of 118a

118b third transverse part

118c second longitudinal direction portion

The 4th transverse part of 118d

119 second filling mask layers

120 the 5th pattern layers

The 5th pattern unit of 120a

121 relief layer pattern transfer layers

121a relief layer pattern transfer unit

122 pattern transfer layers

The pitch-multiplied unit of 122a first

The pitch-multiplied unit of 122b second

123 first intermediate pattern transfer layers

The first intermediate pattern of 123a first direction shifts layer unit

The first intermediate pattern of 123b second direction shifts layer unit

124 graphics-optimized sacrificial layers

125 second intermediate pattern transfer layers

The second intermediate pattern of 125b second direction shifts layer unit

126 third intermediate pattern transfer layers

126b second direction third intermediate pattern shifts layer unit

127 the 4th intermediate pattern transfer layers

The 4th intermediate pattern of 127a first direction shifts layer unit

The 4th intermediate pattern of 127b second direction shifts layer unit

128 the 5th intermediate pattern transfer layers

The 5th intermediate pattern of 128a first direction shifts layer unit

The 5th intermediate pattern of 128b second direction shifts layer unit

129 patterned hard exposure mask exhaustion layers

The patterned polysilicon unit of 129a first direction

The patterned polysilicon unit of 129b second direction

Structure sheaf is sacrificed in the support of 300 capacitors

301 etching barrier layers

302 first medium sacrificial layers

303 second medium sacrificial layers

304 first supporting layers

305 third medium sacrificial layers

306 second supporting layers

307 semiconductor device layers

307a semiconductor memory capacitor hole

308 first graphic mask duplicating layers

S1~S13 step 1)~step 13)

Specific embodiment

Illustrate the embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this theory Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition Different specific embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer With carrying out various modifications or alterations under the spirit without departing from the utility model.

Please refer to Fig.1 to Fig.4 8.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way The basic conception of utility model, though it is only shown with related component in the utility model rather than when according to actual implementation in diagram Component count, shape and size are drawn, when actual implementation form, quantity and the ratio of each component can arbitrarily change for one kind Become, and its assembly layout form may also be increasingly complex.

As shown in Fig. 1~48, the utility model provides a kind of preparation method in semiconductor memory capacitor hole, including as follows Step:

Firstly, carrying out step 1) shown in S1 as shown in figure 1 and Fig. 2~4, providing semiconductor substrate 100, and in described Capacitor support sacrificial layer 300, hard exposure mask exhaustion layer 101, double patterning conformable layer 102, first are sequentially formed on semiconductor base 100 Figure migrating layer 103 and the first mask layer 104, wherein first mask layer 104 includes that can be ashed hard mask layer (AHM) And at least one of DLC film layer (DLC).

Specifically, the utility model provides a kind of step for forming semiconductor memory capacitor hole based on pitch multiplication techniques Suddenly, it is formed in preparation process including semiconductor substrate 100 and is based on pitch multiplication techniques for the hard exposure mask exhaustion layer 101 Patterned graph layer (patterned hard exposure mask exhaustion layer 129), the pitch doubling technique of the utility model, in 30nm and following Reach the technology that capacitor figure is miniature and deep hole is formed in processing procedure by pitch doubling technique, wherein the semiconductor base 100 can be the semiconductor material layer of single layer, such as silicon material layer, are also possible to be laminated by multilayer material and set the laminated material formed Layer, for example, it may be the material layer of a certain semiconductor device structure is constituted, in addition, the hard exposure mask exhaustion layer 101 is graphical Graph layer can be used as semiconductor mask layer, can be continued based on the hard exposure mask exhaustion layer being patterned to the semiconductor Substrate 100 performs etching, and by pattern transfer to the semiconductor base 100, obtains required structure, can such as be formed The capacitor of 30nm and following rank, wherein the hard exposure mask exhaustion layer 101 can be selected from polysilicon layer.In addition, for " Away from " concept, can be used for describing the characteristic size of semiconductor, spacing be between the identical point in two adjacent features away from From, wherein it is pitch-multiplied for the spacing quantity multiple increase under a fixed intervals.

As an example, as shown in figure 4, the double patterning conformable layer 102 successively includes the first pad from bottom to top in step 1) Layer 102a, the second bed course 102b, third bed course 102c and the 4th bed course 102d.

Specifically, the utility model also forms a double patterning conformable layer before forming the first figure migrating layer 103 102, for carrying out figure modification in the preparation process of capacitor hole, to obtain more accurately pattern transfer, in addition, in this example The double patterning conformable layer 102 includes the structure of four layers of bed course, relative to other structures such as two layers of bed courses, so that the feature of figure Size, such as CD of the second direction, can be corrected on bottom bed course (such as A-si/Oxide), for example, preferably one Embodiment in, the structure of tetra- layers of bed course of A-si/Oxide/A-si/Oxide can be used, the CD of Y-direction is (special in subsequent technique Sign size) it can go to correct in the A-si/Oxide layer of bottom, so that the figure made is more accurate.

As an example, the first bed course 102a is any one in silicon oxide layer and ethyl orthosilicate (TEOS) layer Kind, it can be used as hard exposure mask, the thickness of the first bed course 102a is between 100nm~500nm；The second bed course 102b In amorphous silicon layer (A-Si, Amorphous silicon), silicon oxynitride layer (Sion) and silicon nitride layer (Nitride) Any one, can be used as hard exposure mask, the thickness of the second bed course 102b is between 100nm~800nm；The third Any one of bed course 102c in silicon oxide layer and ethyl orthosilicate (TEOS) layer, can be used as mask layer, and described the The thickness of three bed course 102c is between 100nm~500nm；The 4th bed course 102d is selected from amorphous silicon layer, silicon oxynitride Any one in layer and silicon nitride layer, can be used as etching stop layer, the thickness of the 4th bed course 102d between 50nm~ Between 200nm.In addition, the hard exposure mask exhaustion layer 101 formed is as used chemical vapor deposition (CVD) technique, thickness between Between 300nm~1000nm.

As an example, the first figure migrating layer 103 is including underlying graphics transfer layer 103a and is located at institute in step 1) State the upper layer pattern transfer layer 103b on underlying graphics transfer layer 103a.

As an example, the underlying graphics transfer layer 103a include in silicon oxide layer and ethyl orthosilicate (TEOS) layer extremely Few one kind, as oxide migrating layer, in addition, upper layer pattern transfer layer 103b (MLR, the Multilayer It photoresist) include Silicon-rich photoresist layer.

Specifically, the thickness of the underlying graphics transfer layer 103a, between 50nm~100nm, the upper layer pattern turns Move layer (MLR, Multilayer photoresist) 103b can be used as mask layer, thickness between 20nm~150nm, Structure of the utility model by two layers of material as figure migrating layer designs, and improves etching characteristic, optimizes dimension of picture.

Specifically, in step 1), first mask layer 104 includes that can be ashed hard mask layer (AHM) and diamond-like is thin At least one of film layer (DLC), the thickness of first mask layer 104 is between 50nm~200nm.Specifically, originally showing Traditional Carbon is substituted using AHM (Ashable hard mask) or DLC (Diamond like carbon) in example, is made For mask layer, wherein AHM or DLC ratio Carbon has better choice ratio, and is easier to be got rid of by O2 plasma, Profile more tends to ideal, certainly, in other examples, also can choose as Carbon, in addition, first mask layer 104 Can also be can be ashed the laminated construction that both hard mask layer (AHM) and DLC film layer (DLC) are constituted, it is preferably described can Ashing hard mask layer (AHM) is located on the DLC film layer (DLC), to further increase in device fabrication process Stability.

Then shown in S2, as shown in figure 1 and Fig. 5~6, step 2) is carried out, is formed on the first mask layer of Yu Suoshu 104 along the First pattern layer 105 of one direction arrangement, first pattern layer 105 include the first pattern list of several parallel intervals arrangement First 105a.

Specifically, the utility model is based on pitch multiplication techniques, perform etching at least two directions, to be parallel to For defining both direction in plane where semiconductor base 100, i.e. first direction and second direction, first in one direction A degree of etching is carried out, then is deposited on structure sheaf after etching, and in the other directions to post-depositional knot Structure and the material layer formed before perform etching, wherein both direction can be first direction defined in this example and second Direction, the two can be vertical, can be the other angles of intersection, and such as 60 °.In addition, the formation of first pattern layer 105 can be with It using first coating photoresist layer (PR, Photo resist), then is exposed the technique of development and obtains, it is of course also possible to be this Other modes known to the those of ordinary skill of field.Preferably, the first pattern unit 105a preferably uses equidimension etc. The arrangement of spacing parallel interval.It is of course also possible to carry out selection setting according to actual demand.

Then, shown in S3 and Fig. 7 as shown in figure 1, step 3) is carried out, shifts described the via first mask layer 104 Pattern in one pattern layer 105 is into the first figure migrating layer 103, to form the second pattern layer 106, second pattern Layer 106 includes the second pattern unit 106a of several parallel intervals arrangement.

Specifically, in the step, pattern transfer that the first party is upwardly formed to the first figure migrating layer 103 In, so that the second pattern layer 106 is formed, second pattern layer 106 namely graphical first figure migrating layer later, wherein Second pattern layer 106 replicates the pattern of first pattern layer 105, in addition, during pattern transfer, including described in etching The step of first mask layer 104, wherein etching first mask layer 104 preferably uses ICP etching machine bench, the technique of etching It includes at least one of O2, AR, N2 and CH4 that parameter, which includes: etching gas, be preferably selected from above-mentioned etching gas O2, AR, N2 and The combination of CH4, etch pressure between 5mT~20mT, source power between 200W~600W, bias between 200V~ Between 600V.

As an example, as shown in Figure 7, when the first figure migrating layer 103 include underlying graphics transfer layer 103a and When upper layer pattern transfer layer 103b on the underlying graphics transfer layer 103a, then in step 3), transfer described first Pattern in pattern layer 105 is to the underlying graphics migrating layer 103a, to form second pattern layer 106, additionally, it is preferred that institute Stating underlying graphics and shifting 103a layers includes at least one of silicon oxide layer and ethyl orthosilicate (TEOS) layer, the upper layer pattern Transfer layer 103b includes Silicon-rich photoresist layer.

As an example, when the first figure migrating layer 103 includes underlying graphics transfer layer 103a and upper layer pattern transfer When layer 103b, in step 3) further include: etch the upper layer pattern transfer layer 103b and the underlying graphics transfer layer 103a with It shifts on the pattern to the underlying graphics transfer layer 103a in first pattern layer 105, wherein the etching upper layer pattern The technological parameter of transfer layer 103b includes: that etching gas includes at least one of N2, O2 and HE；The underlying graphics are etched to turn The technological parameter for moving layer 103a includes: that etching gas includes at least CH4 and CHF3, certainly can also include O2, etching gas is excellent Choosing contains O2, CH4 and CHF3, and the ratio of CH4 and CHF3 is between 3:1~1:1, etching pressure between 1mT~10mT it Between, source power is between 300W~800W, and bias is between 10V~100V.

Then shown in S4, as shown in figure 1 and Fig. 8~10, step 4), the top of the second pattern unit of Yu Suoshu 106a are carried out It is sacrificial that portion, side wall and 102 surface of double patterning conformable layer between the second pattern unit 106a form the first interval Domestic animal layer 107, and first interval, 107 surface of sacrificial layer between the adjacent second pattern unit 106a is formed between one first Slot 107a, and the first filling mask layer 108, the first filling exposure mask are formed in first interval, 107 surface of sacrificial layer 108 covering of layer, the first interval sacrificial layer 107 simultaneously fills up first clearance groove that first interval sacrificial layer 107 is formed 107a。

Specifically, continuous first interval sacrificial layer 107 is formed in the step, to define subsequent feature ruler Very little, first interval sacrificial layer 107 includes the first transverse part 107b being formed on the top of the second pattern unit 106, position First longitudinal direction portion 107c on 106 side wall of the second pattern unit, and on the double patterning conformable layer 102 Two transverse part 107d, in the present invention, the subsequent characteristic size etched away the first longitudinal direction portion 107c as device CD, because Nitride side wall (first longitudinal direction portion 107c) is what Spacer long got on, thickness can be consistent, such CD size one It causes, solves in the side wall technique of the prior art, the structure of the side wall two sides of deposition forms different CD, that is, there is Spacer The problem of big duck eye of CD odevity.

In addition, described the first of deposition is spaced the thickness of sacrificial layer 107 between 10nm~80nm, and in this example, institute State the CD size that first interval sacrificial layer 107 (side wall Nitride) thickness determines the first direction (such as X-direction).In addition, One layer of the first filling mask layer 108, the first filling mask layer are deposited on second interval, 107 surface of sacrificial layer For 108 thickness between 20nm~100nm, material may include at least one of silica and TEOS, described in part Mask layer of the first filling mask layer 108 as subsequent etching, it is preferable that the first filling filling of mask layer 108 is full described First gap 107a is further conducive to the homogeneity for improving capacitor pore size to advantageously ensure that etching precision.

As an example, as shown in Figure 10, in step 4) further include: Yu Suoshu first fills 108 surface of mask layer deposition one Planarize auxiliary layer 109, deposit it is described planarization auxiliary layer 109 be used for optimize subsequent step 5) flattening effect.

As an example, the planarization auxiliary layer 109 includes that can be ashed hard mask layer (AHM) and DLC film layer At least one of (DLC), it can be any one in the two, be also possible to the laminated structural layers that the two is constituted.As showing Example, the thickness of the planarization auxiliary layer 109 is between 20nm~100nm.

Then, shown in S5 and Figure 11 as shown in figure 1, step 5) is carried out, removal is located at the second pattern unit 106a and pushes up The first transverse part 107b, the first filling mask layer 108 of first interval sacrificial layer 107 in portion, and be located at described Part in first clearance groove 107a the first filling mask layer 108, is equivalent to planarisation step 4) obtained structure is to institute State the second pattern layer 106, wherein be formed with size between the adjacent second pattern unit 106a and limit unit 110 and be located at The size limits the pattern auxiliary unit 111 between unit 110, wherein is located on the second pattern unit 106a side wall The first longitudinal direction portion 107c of first interval sacrificial layer 107 form the size and limit unit 110, be located at the double patterning On the second transverse part 107d and the second transverse part 107d of first interval sacrificial layer 107 on 102 surface of conformable layer The remaining first filling mask layer 108a forms the pattern auxiliary unit 111；

Specifically, the technique by the step, the shape between the second pattern unit 106a in second pattern layer 106 At filler, including the second U-shaped interval sacrificial layer remaining after planarization and the part first being filled between U-shaped opening Mask layer is filled, that is, is defined as size and limits unit 110 and pattern auxiliary unit 111, wherein size limits unit 110 and is used for Limit figure CD, be removed in the subsequent process, the second pattern unit 106a and its between the pattern auxiliary Mask pattern structure of the unit 111 as subsequent first direction pattern etching.

As an example, in step 5), when there are the planarization auxiliary layer 109, planarisation step 4) obtained structure To second pattern layer 106 include: the etching planarization auxiliary layer 109, etching described first fill mask layer 108 and The first transverse part 107b of first interval sacrificial layer 107 at the top of the second pattern unit 106a is etched, preferably Using ICP etching machine bench, wherein etching it is described planarization auxiliary layer 109 technological parameter include: etching gas include O2, AR, At least one of N2 and CH4 preferably include above-mentioned four kinds of etching gas, etch pressure between 5mT~20mT, source power Between 200W~600W, bias is between 200V~600V；Etch the technological parameter of the first filling mask layer 108 Include: that etching gas includes at least CH4 and CHF3, certainly can also include O2, preferably include tri- kinds of O2, CH4 and CHF3 etchings Gas, and the ratio of CH4 and CHF3 is between 3:1~1:1, etches pressure between 1mT~10mT, source power between Between 300W~800W, bias is between 10V~100V；First interval etched at the top of second pattern unit is sacrificial It includes at least one of CHF3, CH4 and SF6 that the technological parameter of domestic animal layer 107b, which includes: etching gas, preferably includes above-mentioned three kinds Etching gas etches pressure between 5mT~30mT, and source power is between 300W~600W, and bias is between 50V~250V Between, to be finally reached the preferable figure of surface planarisation effect.

Then, shown in S6 and Figure 12 as shown in figure 1, step 6) is carried out, in sequentially forming quarter in the structure that step 5) obtains Lose stop-layer 112, second graph migrating layer 114 and the second mask layer 115；

As an example, in step 6) further include: Yu Suoshu etching stop layer 112 and the second graph migrating layer 114 Between form a stress relief layer 113.

As an example, second mask layer 115 includes that can be ashed hard mask layer (AHM) and diamond-like in step 6) At least one of film layer (DLC), naturally it is also possible to be the laminated construction that the two is constituted.

Specifically, deposition materials layer first deposits one using the material layer as the pattern etching in the subsequent second direction Layer etching stop layer 112, using the etching stop layer as subsequent etching, material includes silicon nitride, thickness between 10nm~ Between 80nm, in a preferred embodiment, formed on the etching stop layer 112 for alleviating the etching stop layer 112 Stress the stress relief layer 113, the material of the stress relief layer 113 includes at least one in silica and TEOS Kind, thickness is between 50nm~200nm.In addition, second graph migrating layer (MLR, the Multilayer Photoresist) the preferred Silicon-rich photoresist layer of 114 material, thickness is between 20nm~150nm, second exposure mask Layer 115 can be AHM (Ashable hard mask) or DLC (Diamond like carbon) or Carbon, thickness between Between 50nm~200nm.

Then shown in S7, as shown in figure 1 and Figure 13~15, step 7) is carried out, forms edge on the second mask layer of Yu Suoshu 115 The third pattern layer 116 of second direction arrangement, the third pattern layer 116 include the third pattern of several parallel intervals arrangement Unit 116a has an angle of intersection between the second direction and the first direction；

Specifically, defining graphic structure in the other directions in this example, first pattern layer 116 can be used Photoresist layer (PR, Photo resist) first is coated, then is exposed the technique of development and obtains, it is of course also possible to be this field Other modes known to those of ordinary skill.Preferably, the first pattern unit 116a preferably uses equidimension equidistant Parallel interval arrangement.It is of course also possible to carry out selection setting according to actual demand.In addition, the second direction is needed according to practical Selection is asked, the second direction can be vertical with the first direction, can be the other angles of intersection, such as 60 °.

Then shown in S8, as shown in figure 1 and Figure 16~18, step 8) is carried out, shifts institute via second mask layer 115 The pattern in third pattern layer 116 is stated into the second graph migrating layer 114, to form the 4th pattern layer 117, the described 4th Pattern layer 117 includes the 4th pattern unit 117a of several parallel intervals arrangement；

As an example, step 8) includes: etching second mask layer 115 to shift the figure of the third pattern layer 116 Case to second mask layer 115, etch second mask layer 115 technological parameter include: etching gas include O2, AR, At least one of N2 and CH4, etch pressure between 5mT~20mT, source power between 200W~600W, bias between Between 200V~600V, it is preferable that second mask layer 115 includes that can be ashed hard mask layer (AHM) and DLC film At least one of layer (DLC).

Specifically, in the step, pattern transfer that the second party is upwardly formed to the second graph migrating layer 114 On, to form the 4th pattern layer 117, wherein the 4th pattern layer 117 replicates the pattern of the third pattern layer 116, separately Outside, during pattern transfer, include the steps that etching first mask layer 104, wherein etching second mask layer 115 preferably use ICP etching machine bench, the technological parameter of etching include: etching gas include in O2, AR, N2 and CH4 at least one Kind, it is preferably selected from the combination of above-mentioned etching gas, etches pressure between 5mT~20mT, source power is between 200W~600W Between, bias is between 200V~600V.Step 8) further include: etch the second graph migrating layer 114 described in transfer The pattern of third pattern layer 116 etches second figure to the second graph migrating layer 114 to form the 4th pattern layer 117 The technological parameter of shape migrating layer includes: that etching gas includes at least one of N2, O2 and HE.

Then shown in S9, as shown in figure 1 and Figure 19~22, step 9) is carried out, the top of tetra- pattern unit 117a of Yu Suoshu, Side wall and 112 surface of the etching stop layer between the 4th pattern unit 117a form the second interval sacrificial layer 118, and the second clearance groove is formed between second interval, 118 surface of sacrificial layer between the adjacent 4th pattern unit 117a 118a, and the second filling mask layer 119, the second filling mask layer 119 are formed in second interval, 118 surface of sacrificial layer It covers the second interval sacrificial layer 118 and fills up second interval sacrificial layer 118 and form the second clearance groove 118a.

As an example, the second filling mask layer 119 includes that can be ashed hard mask layer (AHM) and eka-gold in step 9) At least one of hard rock film layer (DLC), the thickness of the second filling mask layer 119 is between 50nm~200nm.

Specifically, continuous second interval sacrificial layer 118 is formed in the step, to define subsequent feature ruler Very little, second interval sacrificial layer 118 includes the third transverse part 118b being formed on the top the 4th pattern unit 117a, position Second longitudinal direction portion 118c on the 4th pattern unit 117a side wall, and be located at the etching stop layer 112 and (work as presence The 4th transverse part 118d on when the stress relief layer 113 on the stress relief layer 113, as shown in figure 19), at this In utility model, the subsequent characteristic size CD etched away the second longitudinal direction portion 118c as device, because of second longitudinal direction portion 118c is what Spacer long got on, and thickness can be consistent, and such CD is in the same size, in addition, second interval of deposition is sacrificed The thickness of layer 118 is between 10nm~80nm, in this example, the second interval sacrificial layer 118 (side wall silicon oxide or the TEOS At least one of) thickness determines the CD size of the second direction (such as Y-direction).In addition, in a preferred embodiment, the The high selectivity ratio that Oxide/Nitride is used in the graphic definition of one direction and second direction, so that figure is compared with other way It is finer.

Then, shown in S10 and Figure 23 as shown in figure 1, step 10) is carried out, planarizes structure that the step 9) obtains extremely Expose the top surface of second interval sacrificial layer 118, and between described second be located on the 4th pattern unit 117a side wall The remaining second filling mask layer 119a between the second longitudinal direction portion 118c of sacrificial layer 118 retains；

Specifically, being planarized in the step by etching technics, to remove part the second filling mask layer 119, the third transverse part 118b of second interval sacrificial layer 118 at the top of the 4th pattern unit 117a is manifested, with For carrying out lower step process to prepare the graphic structure in the second direction.

As an example, in step 10), structure that the step 9) obtains is planarized to second interval sacrificial layer 118 It include: etching the second filling mask layer 119, the technological parameter for etching the second filling mask layer 119 includes: etching gas Body includes at least one of O2, AR, N2 and CH4, etches pressure between 5mT~20mT, source power between 200W~ Between 600W, bias is between 200V~600V.

Then shown in S11, as shown in figure 1 and Figure 24~27, step 11) is carried out, etching removal is located at the 4th pattern Described second at the top of unit 117a is spaced the third transverse part 118b of sacrificial layer 118 and is located at the 4th pattern unit 117a The second longitudinal direction portion 118c of second interval sacrificial layer 118 on side wall, to manifest the etching stop layer 112 simultaneously The 5th pattern layer 120 is obtained, the 5th pattern layer 120 includes the 5th pattern unit 120a of several parallel intervals arrangement, Wherein, the 4th pattern unit 117a on the etching stop layer 112, positioned at the institute of the etching stopping layer surface State the second interval sacrificial layer 118 the 4th transverse part 118d and thereon it is remaining it is described second filling mask layer 119a constitute Lamination forms the 5th pattern unit 120a.

As an example, when further including in the etching stop layer 112 and the second graph migrating layer 114 in step 6) Between when forming a stress relief layer 113, etching removal is located at described the of second interval sacrificial layer 118 in step 11) The stress relief layer 113 is etched simultaneously during two longitudinal direction portion 118c, to form relief layer pattern transfer layer 121.

Specifically, the pattern in the second direction is defined in the step, for ultimately forming capacitor pore structure, institute It states the 5th pattern unit 120a to be made of two-part structure, a portion is the 4th pattern unit 117a, another part It is the laminated construction after etching, the 4th transverse part 118d including second interval sacrificial layer 118 and remaining institute thereon The second filling mask layer 119a is stated, in addition, when there are the stress relief layer 113, the material of the preferably described stress relief layer 113 Material is identical as the second interval material of sacrificial layer 118, to also etch while removing the second longitudinal direction portion 118c The stress relief layer, at this point, the 5th pattern layer 120 formed includes the structure sheaf that the stress relief layer 113 etching is formed.

As an example, in step 11), the third transverse part 118b of etching removal the second interval sacrificial layer 118 And it includes at least one of O2, CH4 and CHF3, etching that the technological parameter of the second longitudinal direction portion 118c, which includes: etching gas, Gas preferably includes tri- kinds of O2, CH4 and CHF3, etches pressure between 1mT~10mT, source power between 300W~800W it Between, bias is between 10V~100V.

In addition, when there are the stress relief layer 113, and the stress relief layer 113 is in shape as shown in Figure 25~27 It is etched simultaneously when at five pattern layer 120, i.e., the described stress relief layer 113 displaced in the 5th pattern layer 120 Pattern, formed relief layer pattern transfer layer 121, including several parallel intervals arrangement relief layer pattern transfer unit 121a further includes removal the 5th pattern layer 120, retains the relief layer pattern transfer layer 121 in a preferred embodiment The step of, as shown in figure 25, then with the relief layer pattern transfer layer 121 be exposure mask carry out subsequent etching processes.

Then shown in S12, as shown in figure 1 and Figure 28~30, step 12) is carried out, using the 5th pattern unit as exposure mask, Selective etch removes the etching stop layer 112 and the size limits unit 110, to shift the 5th pattern layer On pattern to second pattern layer 106 on 120, with the pattern transfer layer 122 formed on the double patterning conformable layer 102, The pattern transfer layer 122 include several first pitch-multiplied unit 122a for arranging along the first direction parallel interval with And several are arranged along the second direction parallel interval and are connected with the described first pitch-multiplied unit second pitch-multiplied Unit 122b, wherein the first pitch-multiplied unit 122a is assisted by the second pattern unit 106a and the pattern Unit 111 is constituted, and the second pitch-multiplied unit 122b is shifted by the 5th pattern unit 120a to be formed；

As an example, the pattern transfer layer 122 formed includes grid-like pattern transfer layer, diamond shaped pattern transfer layer At least one of.

Specifically, the figure on the first direction crosses with the figure in the second direction in the step, one compared with In good embodiment, the material of the etching stop layer 112 is identical as the first interval material of sacrificial layer 107, to have The removal of unit is limited conducive to the etching stop layer 112 and by the size that first interval sacrificial layer 107 is formed, most End form obtains the figure that subsequent etching forms capacitor hole at the pattern transfer layer 122 as shown in FIG. 28 and 29.Into one Step, in a preferred embodiment, the material of the material of preferably described second pattern layer 106 and the first filling mask layer 108 It is identical, to be conducive to the embodiment of subsequent etching processes, is conducive to the homogeneity for improving pattern topology, improves device performance Stability.It, can be in addition, pictorial pattern in the pattern transfer layer 122 formed in this example is selected according to actual conditions It is mesh pattern, e.g., when the first direction is mutually perpendicular to the second direction, the pattern transfer layer 122 of formation Middle pattern topology is to intersect grid-like, that is, forms that several are of uniform size, uniform array arrangement it is grid-like, certainly, at other It in example, can be selected according to demand, such as form ground of uniform size diamond shaped patterned structural layer.

Finally, step 13) is carried out, via 102 turns of the double patterning conformable layer shown in S13 as shown in figure 1 and Figure 31~48 The figure on the pattern transfer layer 122 is moved into the hard exposure mask exhaustion layer 101, obtains patterned hard exposure mask exhaustion layer 129, and the capacitor support is etched based on the patterned hard exposure mask exhaustion layer 129 and sacrifices structure sheaf 300, in the electricity Hold support and sacrifices the semiconductor memory capacitor hole 307a for forming the arrangement of several uniform intervals in structure sheaf 300.

Specifically, by the pattern transfer on the pattern transfer layer 122 to the hard exposure mask exhaustion layer 101, obtained institute The etching technics that patterned hard exposure mask exhaustion layer 129 carries out subsequent capacitor hole as mask layer is stated, as shown in Figure 43~45. Wherein, in the process for etching the hard exposure mask exhaustion layer 101, it is preferred to use CCP board, thereon the part meeting of surface exposure Be oxidized, in a preferred embodiment, first with the etching gas of at least one of AR/CF4/O2,5~30mt/HF, 200~500W/LF and 200~800W condition go down to open surface layer, then utilize the etching gas of at least one of HBR/NF3/O2 Body goes down to etch open hard exposure mask described in hard exposure mask in 30~200mt/HF, 100~800W/LF and 500~1500W condition and disappears Layer is consumed, in addition, it is further preferred that preferential goes to etch by the way of Pulse Etch in order to keep Profile more vertical.

As an example, when there are the double patterning conformable layer 102, in step 13) on the transfer pattern transfer layer 122 Figure into the hard exposure mask exhaustion layer 101 before further include: shift figure on the pattern transfer layer 122 to described double Pattern conformable layer 102, and specific steps include:

It is 13-1) the 4th bed course 102d described in mask etching with the pattern transfer layer 122, obtains the first intermediate pattern and turn Layer 123 is moved, and retains the remaining pattern transfer layer after etching, as shown in FIG. 31 and 32, the 4th bed course 102d turns It is melted into the first intermediate pattern transfer layer 123, and it displaced the pattern in 122 both direction of pattern transfer layer, forms the One direction the first intermediate pattern buanch unit 123a and second direction the first intermediate pattern buanch unit 123b；

Graphics-optimized sacrificial layer 124 13-2) is deposited in the surface of the obtained structure of step 13-1), the graphics-optimized is sacrificial Domestic animal layer 124 is filled between the pattern on the first intermediate pattern transfer layer 123 and the remaining pattern transfer layer 122 Gap simultaneously covers the pattern transfer layer 122, as shown in figure 33, wherein on the first direction and the second direction Identical effect is generated, example is only carried out with the section of the second direction herein；

The graphics-optimized sacrificial layer 124 13-3) is planarized to the remaining pattern transfer layer 122, and removes residue The pattern transfer layer 122, wherein the graphics-optimized sacrificial layer is converted into the second intermediate pattern transfer layer 125, including Two direction the second intermediate pattern buanch unit 125b, as shown in FIG. 34 and 35, in this second direction, the graphics-optimized Sacrificial layer 124 forms the second intermediate pattern transfer layer 125 after planarizing, and later, removes the remaining pattern transfer layer 122, Retain the 4th bed course transfer layer 123, as shown in figure 35, wherein produce on the first direction and the second direction Raw identical effect, only carries out example herein with the section of the second direction；

The second intermediate pattern transfer layer 125 13-4) is removed, and is based on step 13-1) etch described first obtained Intermediate pattern transfer layer 123 etches the third bed course 102c, obtains third intermediate pattern transfer layer 126, including second direction Third intermediate pattern buanch unit 126b, and the first direction and described are adjusted during etching the third bed course The size of figure on two directions as shown in figure 36, and adjusts the first party during etching the third bed course 102c To and the second direction on figure size, in one example, the effect of graphics-optimized sacrificial layer described herein as shown, If pattern transfer layer serves as exposure mask when directly etching, and material is identical, and etch profile can be turned round without the graphics-optimized sacrificial layer Song, since Oxide etch-rate is very fast, can also hurt lower layer's third bed course, so pattern if pattern transfer layer does not remove first It can be more preferable.In addition, in this example, the CD size for the figure that the transfer of first direction X obtains, (at this time by Nitride Nitride is the first interval sacrificial layer 107) thickness of side wall deposition determines, and transferred figure can be passed through here CD needed for middle CD (CD as at this time can be the CD such as figure in the 4th bed course transfer layer 123 in Figure 35) size judgement is big Small whether to reach demand, if excessive or too small, time when can be etched by third bed course goes adjustment to make up amendment CD Size realizes the amendment of the size for the figure for finally needing to obtain.

The second bed course 102b 13-5) is etched, obtains the 4th intermediate pattern transfer layer 127, and to etch obtained institute Stating the 4th intermediate pattern transfer layer 127 is the first bed course 102a described in mask etching, obtains the 5th intermediate pattern transfer layer 128, With by the pattern transfer on the pattern transfer layer 122 into the first bed course 102a.

Specifically, in the step by the pattern transfer on the pattern transfer layer 122 into the first bed course 102a, with By the pattern transfer on the pattern transfer layer 122 into figure finishing mask layer 102, the utility model passes through above-mentioned four The design of the figure finishing mask layer of layer bed course, the available accurate figure of pattern, wherein on the pattern transfer layer 122 Figure, here upper is not position below proper top, and so on, those of ordinary skill in the art are equal Expressed meaning can be determined according to diagram and actual conditions.

As an example, as shown in figure 46, in step 1), it includes being located at described half that structure sheaf 300 is sacrificed in the capacitor support Etching barrier layer 301 in conductor substrate 100 and at least one layer of medium sacrificial layer on the etching barrier layer 301 (302,303,305) and at least one layer of supporting layer (304,306)；Step 13) includes: based on the patterned hard exposure mask consumption 129 etching of the layer supporting layer (304,306), the medium sacrificial layer (302,303,305) and the etching barrier layer 301, and the remaining patterned hard exposure mask exhaustion layer 129 after etching is removed, to be etched on the semiconductor base 100 Form the semiconductor memory capacitor hole 307a for several uniform intervals arrangement being located in capacitor support sacrificial layer 300.

Specifically, etching the capacitor support in this example and sacrificing structure sheaf 300, so as to obtain subsequent preparation electricity The capacitor pore structure that container is based on, wherein form semiconductor device layer 307 comprising several memory capacitor holes 307a. In addition, in a preferred embodiment, can have multiple capacitive touch in memory structure of arrays in the semiconductor base 100 Point, the semiconductor base 100 may include silicon substrate, germanium substrate, germanium silicon substrate, silicon carbide substrates etc., in the present embodiment, The semiconductor base 100 can be silicon substrate.In addition, the memory array structure further includes having transistor character line (Word Line) and bit line (Bitline), the capacitor contact are electrically connected the transistor source in the memory array structure.It is described Capacitor contact is corresponding with the arrangement of the capacitor of subsequent production.In addition, between the capacitor contact by wall carry out every From the material of the wall can be silicon nitride (SiN), silica (SiO₂), aluminium oxide (Al₂O₃) in any one or Any two or more combination, in the present embodiment, the material selection of the wall are SiN.

As an example, the dielectric layer includes first medium sacrificial layer 302, second medium sacrificial layer 303 and third medium Sacrificial layer 305, the supporting layer include the first supporting layer 304 and the second supporting layer 306, wherein the first medium sacrificial layer 302, the second medium sacrificial layer 303, first supporting layer 304, the third medium sacrificial layer 305 and second described Support layer 306 is sequentially stacked from bottom to top.

As an example, the etching barrier layer 301 includes silicon nitride layer, the thickness of the etching barrier layer 301 between Between 10nm~80nm；The first medium layer 302 includes phosphorus doping silicon oxide layer (PSG layers), boron phosphorous doped oxide layer (BPSG Layer) and at least one of silicon oxide glass layers (fsg layer) of Fluorin doped, the thickness of the first medium sacrificial layer 302 between Between 100nm~600nm；Preferably, the hardness of the second medium sacrificial layer 303 is greater than the first medium sacrificial layer 302 Hardness, to improve the stability of subsequent capacitance structure, the second medium sacrificial layer 303 includes TEOS layer, second Jie The thickness of matter sacrificial layer 303 is between 300nm~1000nm；The third medium sacrificial layer 305 includes silica and TEOS At least one of layer, the thickness of the third medium sacrificial layer 305 is between 300nm~1000nm；First support Layer 304 includes silicon nitride layer, and the thickness of first supporting layer 304 is between 10nm~80nm；Second supporting layer 306 Including silicon nitride layer, the thickness of second supporting layer 306 is between 50nm~200nm.

Specifically, this example provides a kind of subsequent laminated material bed of material that can form memory capacitor hole 307a, wherein draw The structure for having entered laminated medium sacrificial layer and two layers of supporting layer, due to the reduction of capacitor size and the increase of height, capacitor is very It is easy to happen and topples over so that form short circuit, therefore, introduce two layers of supporting layer (Nitride) and cooperate three layers of medium sacrificial layer Configuration, can achieve the effect of fixed capacity, prevent the problem that capacitor causes short circuit due to toppling over.In addition, due to electricity Holding is that deep hole etches, and is occurred to reduce bottom Undercut, the first medium sacrificial layer preferably uses material relatively soft The materials such as PSG/BPSG/FSG, and the hardness of the second medium sacrificial layer 303 is preferably greater than the first medium sacrificial layer 302 Hardness, can be TEOS material or the PSG/BPSG/FSG faster than 302 deposition velocity of first medium sacrificial layer.Separately Outside, the third medium sacrificial layer 305 can be the materials such as SiO2 or TEOS, to reach the capacitor height of requirement.

In addition, preferably being adopted in the process for etching the etching stop layer, the medium sacrificial layer and the supporting layer Performed etching with CCP board, the etching technics of second supporting layer 306 include: etching gas include C4F8, CHF3, CF4, At least one of CH2F2 and 50~300W/60MHZ200 of pressure 5~50mt/2MHZ, 1000~5000W/27MHZ~ The condition of 1000W etches；It includes in O2, C4F6, NF3 that the etching technics of the third medium sacrificial layer 305, which includes: etching gas, At least one and go to etch under conditions of pressure 5~30mt/2MHZ, 4000~8000W/60MHZ, 500~1500W； The etching technics of first supporting layer 304 include: etching gas include in C4F6, O2, C4F8, NF3 and CH2F2 at least one It plants and goes to lose in 100~500W/60MHZ200 of pressure 5~50mt/2MHZ, 1000~5000W/27MHZ~800W condition It carves；The etching technics of the second medium sacrificial layer 303 include: etching gas include at least one of C4F6, O2 and NF3 and It goes to etch under conditions of pressure 5~30mt 2MHZ 4000~8000W/60MHZ, 500~2000W；The first medium is sacrificial It includes at least one of C4F6, O2 and NF3 and in 5~30mt of pressure that the etching technics of domestic animal layer 302, which includes: etching gas, It goes to etch under conditions of 4000~8000W/60MHZ of 2MHZ, 500~2000W；The etching technics packet of the etching barrier layer 301 Include: etching gas includes at least one of O2, CHF3, CH2F2 and in 5~50mt/2MHZ of pressure, 200~1000W/27MHZ It goes to etch under conditions of 50~300W/60MHZ, 200~1000W.

As an example, etching the supporting layer (304,306), the medium sacrificial layer by the way of pulse radiation frequency etching (302,303,305) and the etching barrier layer 301, wherein the etching period of the pulse radiation frequency etching includes that pulse is opened It opens primary and pulse to close once, the pulse performs etching when opening, and by-product, the pulse is discharged when closing in the pulse The time of unlatching accounts for the 70%~90% of the etching period of the pulse radiation frequency etching.

It is preferential using Pulse Etch's in order to keep Profile more preferable specifically, the depth due to etching is deep Mode, mainly the period of radio frequency on is changed to 70%~90% by 100% in Recipe setting here, entire radio frequency Time also increases in proportion, guarantees that the radio frequency on time is enough.

The utility model also provides the laminated construction in a kind of preparation process in semiconductor memory capacitor hole, and referring to fig. 28 Shown in~30, the laminated construction preferably uses the technique system in the present embodiment in the preparation process of semiconductor memory capacitor hole It is standby, comprising:

Semiconductor base 100；

Structure sheaf 300 is sacrificed in capacitor support, including etching barrier layer 301 and on the etching barrier layer 301 At least one layer of medium sacrificial layer (302,303,305) and at least one layer of supporting layer (304,306), and the etching barrier layer 301 Positioned at the surface of the semiconductor base 100；

Hard exposure mask exhaustion layer 101, is located at 300 surface of capacitor supporting structure layer；

Double patterning conformable layer 102 is located at hard 101 surface of exposure mask exhaustion layer；And

Pattern transfer layer 122 is located on the double patterning conformable layer 102, including several are along first direction parallel interval First pitch-multiplied unit 122a of arrangement and several in a second direction parallel interval arrangement and with first spacing times Increase the second connected pitch-multiplied unit 122b of unit, there is an angle of intersection between the second direction and the first direction Degree, and one first spacing is generated between the adjacent first pitch-multiplied unit, between the adjacent second pitch-multiplied unit One second spacing is generated, first spacing and second spacing are all defined by the thickness of respective intervals sacrificial layer.

Specifically, the pictorial pattern in the pattern transfer layer 122 formed in this example is selected according to actual conditions, it can To be mesh pattern, e.g., when the first direction is mutually perpendicular to the second direction, the pattern transfer layer of formation Pattern topology is to intersect grid-like in 122, that is, forms that several are of uniform size, uniform array arrangement it is grid-like, certainly, at it It in his example, can be selected according to demand, such as form ground of uniform size diamond shaped patterned structural layer.

As an example, the laminated construction in the preparation process in semiconductor memory capacitor hole further includes one first figure Exposure mask duplicating layer 308 is used to form the described first pitch-multiplied unit 122a, and the first graphic mask duplicating layer includes several First pattern unit of a parallel interval arrangement and several second patterns between adjacent first pattern unit Unit, second pattern unit include that the first bottom deposit layer and the first top on the first bottom deposit layer sink Lamination, and the spacing between adjacent first pattern unit and second pattern unit and the first bottom deposit layer Thickness is generally in identical.

Specifically, to provide a kind of the first graphic mask that can form the described first pitch-multiplied unit 122a multiple for this example Preparative layer 308, for details, reference can be made to shown in Figure 11 in the present embodiment, first pattern unit in this example be can be found in Figure 11 The second pattern unit 106a, the second graph unit in this example can be found in the pattern auxiliary unit in Figure 11 111, wherein the bottom deposit layer is equivalent to the second transverse part 107d of first interval sacrificial layer in figure, the top Portion's sedimentary is equivalent to the remaining first filling mask layer 109a in figure.

As an example, the laminated construction in the preparation process in semiconductor memory capacitor hole further includes a second graph Exposure mask duplicating layer 120, the second graph exposure mask duplicating layer can be semiconductor memory in the utility model embodiment at this time The 5th pattern layer in preparation process is used to form second graph exposure mask duplicating layer described in the described second pitch-multiplied unit Including several parallel intervals arrangement third pattern unit and several between the adjacent third pattern unit 4th pattern unit, the 4th pattern unit include the second bottom deposit layer and on the second bottom deposit layer Two top deposited layers, and the spacing between the adjacent third pattern unit and the 4th pattern unit and second bottom The thickness of sedimentary is generally in identical.

Specifically, this example provides a kind of figure that can form the described second pitch-multiplied unit 122b, can specifically join As shown in Figure 23 and Figure 24 in the present embodiment, wherein the third pattern unit in this example is equivalent to described in figure 4th pattern unit 117a, the 4th pattern unit in this example are equivalent to the 5th pattern unit 120a, wherein second bottom Portion's sedimentary is equivalent to the 4th transverse part 118d of second interval sacrificial layer in figure, and second top deposited layer is suitable In the remaining second filling mask layer 119a.

As an example, the etching barrier layer 301 includes silicon nitride layer, the thickness of the etching barrier layer 301 between Between 10nm~80nm；The first medium sacrificial layer 302 includes phosphorus doping silicon oxide layer (PSG layers), boron phosphorous doped oxide layer At least one of silicon oxide glass layers (fsg layer) of (bpsg layer) and Fluorin doped, the thickness of the first medium sacrificial layer 302 Between 100nm~600nm；Preferably, the hardness of the second medium sacrificial layer 303 is greater than the first medium sacrificial layer 302 hardness, to improve the stability of subsequent capacitance structure, the second medium sacrificial layer 303 is including TEOS layers, described second The thickness of medium sacrificial layer 303 is between 300nm~1000nm；The third medium sacrificial layer 305 include silica and At least one of TEOS layers, the thickness of the third medium sacrificial layer 305 is between 300nm~1000nm；Described first Supporting layer 304 includes silicon nitride layer, and the thickness of first supporting layer 304 is between 10nm~80nm；Second support Layer 306 includes silicon nitride layer, and the thickness of second supporting layer 306 is between 50nm~200nm.

Specifically, this example provides, one kind is subsequent can to form the capacitor supporting structure 307b and memory capacitor hole The laminated material bed of material of 307a, wherein the structure for introducing laminated medium sacrificial layer and two layers of supporting layer, due to capacitor size It reduces and the increase of height, capacitor is easy to topple over so that form short circuit, therefore, introduce two layers of supporting layer (Nitride) and cooperate three layers of medium sacrificial layer configuration, can achieve the effect of fixed capacity, prevent capacitor due to inclining Cause the problem of short circuit.In addition, occurring since capacitor is deep hole etching in order to reduce bottom Undercut, described first The materials such as the PSG/BPSG/FSG that medium sacrificial layer preferably uses material relatively soft, and the second medium sacrificial layer 303 is hard Degree is preferably greater than the hardness of the first medium sacrificial layer 302, can be for TEOS material or than the first medium sacrificial layer The fast PSG/BPSG/FSG of 302 deposition velocities.In addition, the third medium sacrificial layer 305 can be the materials such as SiO2 or TEOS Matter, to reach the capacitor height of requirement.

As an example, the angle of intersection includes 60 °；The first pitch-multiplied unit 122a equally parallel interval Arrangement, the second pitch-multiplied unit 122b equally arrange by parallel interval；The width of the first pitch-multiplied unit It is equal with the width of the described second pitch-multiplied unit；First spacing is equal with the width of second spacing.

As an example, the double patterning integration in lamination knot in the preparation process in semiconductor memory capacitor hole Layer 102, is used to form the patterned hard exposure mask exhaustion layer, referring to fig. 2 shown in 8~30, wherein the double patterning conformable layer 102 successively include the first bed course 102a, the second bed course 102b, third bed course 102c and the 4th bed course 102d from bottom to top.This Utility model by the design of above-mentioned four layers of bed course may be implemented that it is accurate to obtain pattern to the amendment of figure in etching process Figure.

As an example, the first bed course 102a is any one in silicon oxide layer and ethyl orthosilicate (TEOS) layer Kind, any one of the second bed course 102b in amorphous silicon layer, silicon oxynitride layer and silicon nitride layer, the third pad Any one of layer 102c in silicon oxide layer and ethyl orthosilicate (TEOS) layer, the 4th bed course 102d is selected from non- Any one in crystal silicon layer, silicon oxynitride layer and silicon nitride layer.

As an example, the laminated construction in the preparation process in semiconductor memory capacitor hole further includes a pattern transfer Hard mask layer is formed in the described first pitch-multiplied unit 122a and the second pitch-multiplied unit 122b for transition diagram At least one, wherein the pattern transfer hard mask layer include can be ashed hard mask layer (AHM) and DLC film layer At least one of (DLC).

Specifically, in a preferred embodiment, the pattern transfer hard mask layer includes the stacked lamination of two layers of material Structure, including the diamond-like on hard mask layer (AHM, Ashable hard mask carbon) and surface disposed thereon can be ashed Film layer (DLC, Diamond like carbon), wherein the thickness for being ashed hard mask layer is between 50nm~200nm Between, it is preferably between 100nm~150nm, the thickness of the DLC film layer is excellent between 200nm~300nm Selected introductions are between 120nm~180nm；Further preferably, the thickness of the DLC film layer is greater than described can be ashed and covers firmly Mask layer is carried out above structure improvement by the thickness of film layer, this example, forms the pitch-multiplied list of the first pattern for etching Member, or it is used to form the described second pitch-multiplied unit, there is better choice compared to carbon and other mask materials Than so that the pattern migrated is more accurate, and being easier to be removed by oxygen (O2).

As shown in Figure 47 and Figure 48, as an example, structure sheaf 300 is sacrificed in capacitor support has several uniform intervals The semiconductor memory capacitor hole 307a of arrangement；The utility model also provides a kind of semiconductor memory capacitor pore structure, described Semiconductor memory capacitor pore structure includes the preparation using the semiconductor memory capacitor hole as described in above-mentioned any scheme Laminated structural layers in journey simultaneously etch the semiconductor device layer 307 that the supplementary structure layer is formed based on the pattern transfer layer, The semiconductor device layer is located in the semiconductor substrate, and the semiconductor device layer 307 includes the several of etching formation The semiconductor memory capacitor hole 307a of a uniform intervals arrangement.

In conclusion the utility model provides a kind of preparation method in semiconductor memory capacitor hole, including 1) provide one Semiconductor base, and structure sheaf, hard exposure mask exhaustion layer, double patterning are sacrificed in sequentially forming capacitor support on the semiconductor base Conformable layer, the first figure migrating layer and the first mask layer, first mask layer include that can be ashed hard mask layer (AHM) and class At least one of diamond film layer (DLC)；2) the first figure arranged along first direction is formed on the first mask layer of Yu Suoshu Pattern layer, first pattern layer include the first pattern unit of several parallel intervals arrangement；3) via first mask layer The pattern in first pattern layer is shifted into the first figure migrating layer, to form the second pattern layer, second figure Pattern layer includes the second pattern unit of several parallel intervals arrangement；4) top of the second pattern unit of Yu Suoshu, side wall and The double patterning between second pattern unit integrates layer surface and forms the first interval sacrificial layer, and adjacent described second First interval sacrificial layer surface between pattern unit forms one first clearance groove, and in first interval sacrificial layer table Face formation the first filling mask layer, wherein the first filling mask layer covering described first is spaced described in sacrificial layer and filling First clearance groove that first interval sacrificial layer is formed；5) removal is located between described first at the top of second pattern unit It is filled out every the first transverse part, the first filling mask layer and the part described first in first clearance groove of sacrificial layer Fill mask layer, wherein be formed with size between adjacent second pattern unit and limit unit and be located at size restriction list Pattern auxiliary unit between member, the first longitudinal direction of first interval sacrificial layer on the second pattern unit side wall Portion forms the size and limits unit, the second transverse part of first interval sacrificial layer on the double patterning conformable layer And the remaining first filling mask layer on second transverse part forms the pattern auxiliary unit；6) in step Etching stop layer, second graph migrating layer and the second mask layer are sequentially formed in the rapid structure 5) obtained；7) Yu Suoshu second The third pattern layer arranged in a second direction is formed on mask layer, the third pattern layer includes what several parallel intervals were arranged Third pattern unit, wherein there is an angle of intersection between the second direction and the first direction；8) via described second Mask layer shifts the pattern in the third pattern layer into the second graph migrating layer, described to form the 4th pattern layer 4th pattern layer includes the 4th pattern unit of several parallel intervals arrangement；9) top of tetra- pattern unit of Yu Suoshu, side wall And the etching stopping layer surface between the 4th pattern unit forms the second interval sacrificial layer, and adjacent described the Second interval sacrificial layer surface between four pattern units forms one second clearance groove, and in second interval sacrificial layer Surface forms the second filling mask layer, wherein the second filling mask layer covering described second is spaced sacrificial layer and fills institute State second clearance groove of the second interval sacrificial layer formation；10) it planarizes described in the structure to exposing that the step 9) obtains The top surface of second interval sacrificial layer, and the second of second interval sacrificial layer being located on the 4th pattern unit side wall is vertical Retain to the remaining second filling mask layer between portion；11) etching removal is located at the top of the 4th pattern unit The third transverse part of second interval sacrificial layer and described second on the 4th pattern unit side wall are spaced sacrificial The second longitudinal direction portion of domestic animal layer, to manifest the etching stop layer and obtain the 5th pattern layer, the 5th pattern layer packet Include the 5th pattern unit of several parallel intervals arrangement, wherein the 4th pattern list on the etching stop layer Member, positioned at the etching stopping layer surface it is described second interval sacrificial layer the 4th transverse part and be located at it is described 4th laterally The lamination that the remaining second filling mask layer in portion is constituted forms the 5th pattern unit；12) with the 5th figure Case unit is exposure mask, and selective etch removes the etching stop layer and the size limits unit, to shift the described 5th On pattern to second pattern layer in pattern layer, with the pattern transfer layer formed on the double patterning conformable layer, the figure The first pitch-multiplied unit that shape transfer layer, which includes several, arranges along the first direction parallel interval and several along institute The the second pitch-multiplied unit stating the arrangement of second direction parallel interval and being connected with the described first pitch-multiplied unit, wherein institute It states the first pitch-multiplied unit to be made of second pattern unit and the pattern auxiliary unit, described second is pitch-multiplied Unit is shifted by the 5th pattern unit and is formed；And 13) the pattern transfer layer is shifted via the double patterning conformable layer On figure obtain patterned hard exposure mask exhaustion layer into the hard exposure mask exhaustion layer, and patterned covered firmly based on described Film exhaustion layer etches the capacitor support and sacrifices structure sheaf, to form several uniform intervals in the capacitor supporting structure layer The semiconductor memory capacitor hole of arrangement.Through the above scheme, the utility model based on pitch-multiplied semiconductor structure layer Side wall layer (spacer) progress figure is respectively formed using both direction in preparation to double, and is based on this pitch doubling technique, it can Miniature to reach figure in 30nm and following processing procedure, further, the utility model passes through twocouese in control preparation process Size further, is improved characteristic size in device architecture and is defined, solve to reach the good uniformity of doubling range interval figure Certainly the problem of big small holes, and by the improvement of double patterning conformable layer in etching process, figure amendment is carried out during the preparation process, Figure precision is improved, in addition, the utility model also improves structure sheaf, to reach better choice ratio, improves electricity Hold dimensional defects, improves yield.So the utility model effectively overcomes various shortcoming in the prior art and has high industrial Utility value.

The above embodiments are only illustrative of the principle and efficacy of the utility model, and not for limitation, this is practical new Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model All equivalent modifications or change completed under mind and technical idea, should be covered by the claim of the utility model.

Claims

1. a kind of semiconductor memory capacitor hole prepares laminated construction characterized by comprising

Semiconductor base；

Structure sheaf is sacrificed in capacitor support, and the capacitor support sacrifices structure sheaf and includes etching barrier layer and hinder positioned at the etching At least one layer of medium sacrificial layer and at least one layer of supporting layer in barrier, and the etching barrier layer is located at the semiconductor base Surface；

Pattern transfer layer is located on the double patterning conformable layer, including several along the first of the arrangement of first direction parallel interval Pitch-multiplied unit and several in a second direction parallel interval arrange and be connected with the described first pitch-multiplied unit the Two pitch-multiplied units have an angle of intersection between the second direction and the first direction, and between adjacent described first Away from one first spacing is generated between multiplication units, one second spacing is generated between the adjacent second pitch-multiplied unit, it is described First spacing and second spacing are all defined by the thickness of respective intervals sacrificial layer.

2. semiconductor memory capacitor according to claim 1 hole prepares laminated construction, which is characterized in that further include one First graphic mask duplicating layer is used to form the described first pitch-multiplied unit, wherein the first graphic mask duplicating layer packet Include the arrangement of several parallel intervals the first pattern unit and several between adjacent first pattern unit the Two pattern units, second pattern unit include the first bottom deposit layer and on the first bottom deposit layer first Top deposited layer, and the spacing between adjacent first pattern unit and second pattern unit and first bottom are heavy The thickness of lamination is generally in identical.

3. semiconductor memory capacitor according to claim 1 hole prepares laminated construction, which is characterized in that further include one Second graph exposure mask duplicating layer is used to form the described second pitch-multiplied unit, wherein the second graph exposure mask duplicating layer packet Include the arrangement of several parallel intervals third pattern unit and several between the adjacent third pattern unit the Four pattern units, the 4th pattern unit include the second bottom deposit layer and on the second bottom deposit layer second Top deposited layer, and the spacing between the adjacent third pattern unit and the 4th pattern unit and second bottom are heavy The thickness of lamination is generally in identical.

4. semiconductor memory capacitor according to claim 1 hole prepares laminated construction, which is characterized in that the medium Sacrificial layer includes first medium sacrificial layer, second medium sacrificial layer and third medium sacrificial layer, and the supporting layer includes first Support layer and the second supporting layer, wherein the first medium sacrificial layer, the second medium sacrificial layer, first supporting layer, institute It states third medium sacrificial layer and second supporting layer is sequentially stacked from bottom to top.

5. semiconductor memory capacitor according to claim 1 hole prepares laminated construction, which is characterized in that the intersection Angle includes 60 °；The first pitch-multiplied unit equally parallel interval arrange, the second pitch-multiplied unit in etc. The arrangement of spacing parallel interval；The width of the first pitch-multiplied unit is equal with the width of the described second pitch-multiplied unit； First spacing is equal with the width of second spacing.

6. semiconductor memory capacitor hole prepares laminated construction, feature described according to claim 1~any one of 5 It is, the double patterning conformable layer successively includes the first bed course, the second bed course, third bed course and the 4th bed course from bottom to top.

7. semiconductor memory capacitor according to claim 6 hole prepares laminated construction, which is characterized in that described first Any one of bed course in silicon oxide layer and ethyl orthosilicate (TEOS) layer, second bed course are selected from amorphous silicon Any one in layer, silicon oxynitride layer and silicon nitride layer, the third bed course is selected from silicon oxide layer and ethyl orthosilicate (TEOS) any one in layer, the 4th bed course are any in amorphous silicon layer, silicon oxynitride layer and silicon nitride layer It is a kind of.

8. semiconductor memory capacitor according to claim 6 hole prepares laminated construction, which is characterized in that further include one Pattern transfer hard mask layer is formed in the described first pitch-multiplied unit and the second pitch-multiplied unit for transition diagram At least one, wherein the pattern transfer hard mask layer include can be ashed hard mask layer (AHM) and DLC film layer At least one of (DLC).

9. semiconductor memory capacitor according to claim 1 hole prepares laminated construction, which is characterized in that the capacitor The semiconductor memory capacitor hole that structure sheaf has the arrangement of several uniform intervals is sacrificed in support.