CN110957262A - Semiconductor structure and through hole forming method - Google Patents
Semiconductor structure and through hole forming method Download PDFInfo
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- CN110957262A CN110957262A CN201811122758.7A CN201811122758A CN110957262A CN 110957262 A CN110957262 A CN 110957262A CN 201811122758 A CN201811122758 A CN 201811122758A CN 110957262 A CN110957262 A CN 110957262A
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
Abstract
The invention provides a semiconductor structure and a forming method of through holes, wherein the semiconductor structure comprises a hard mask combination layer, a plurality of through holes are separately arranged in the hard mask combination layer, a plurality of first through holes are at least arranged in a row, the first through holes in the same row are arranged at equal intervals, and two adjacent through holes in the same row are respectively surrounded by hard mask layers formed at different stages. The through hole forming method realizes the micro-reduction of the key size of the through hole by means of secondary photoetching and alternate modes of multiple thin film deposition sacrificial layers and dry etching sacrificial layers, forms more through holes while reducing the key size of the through hole, and solves the problem that the through hole with smaller key size cannot be formed by direct exposure of yellow light.
Description
Technical Field
The invention belongs to the field of integrated circuits, and relates to a semiconductor structure and a method for forming a through hole.
Background
As the density of semiconductor devices increases, the required pattern pitch and width gradually decrease, and the feature size of Dynamic Random Access Memory (DRAM) gradually decreases.
Current mainstream lithographic techniques include:
(1)248nm Deep ultraviolet (Deep Ultra-Violet, DUV for short) technology (KrF excimer laser), the Characteristic Dimension (CD) of which is 100 nm;
(2)193nm DUV technology (ArF excimer laser), with a feature size of 90 nm;
(3)193nm immersion technology (ArF excimer laser) with a feature size of 65 nm.
Table 1 shows a year table of DRAM 1/2 pitches (pitch), and it can be seen that in 2017, DRAM 1/2 pitch is 18nm, which is already smaller than the exposure limit of 193nm immersion Lithography (ArF excimer laser), and before the next generation of Lithography (Extreme Ultraviolet Lithography, EUV Lithography) is not yet widespread, the continuous shrink of the process must be achieved by other methods, such as Self-aligned Double Patterning (SADP) technology, which can significantly reduce the line width.
TABLE 1 year table of DRAM characteristic dimensions
| Year of production | 2013 | 2017 | 2019 | 2024 |
| |
28 | 18 | 14 | 8 |
Therefore, how to provide a semiconductor structure and a method for forming a via hole to solve the problem in the prior art that the feature size of the via hole has reached the exposure limit of photolithography due to the continuous shrinkage of the process is an important technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a semiconductor structure and a method for forming a via hole, which are used to solve the problem in the prior art that the feature size of the via hole has reached the exposure limit of photolithography due to the continuous shrinkage of the process.
To achieve the above and other related objects, the present invention provides a method for forming a via hole, comprising the steps of:
s1: providing a first hard mask layer, forming a plurality of first through holes in the first hard mask layer, wherein the first through holes are at least arranged in a row, and the first through holes in the same row are arranged at equal intervals;
s2: forming a first sacrificial layer on the side wall of the first through hole to reduce the opening area of the first through hole;
s3: filling a second sacrificial layer in the residual space in the first through hole to obtain a first column positioned in the first through hole;
s4: removing the first sacrificial layer in the first through hole to obtain a first gap surrounding the first column;
s5: filling a second hard mask layer in the first gap, wherein the second hard mask layer and the rest of the first hard mask layer are jointly used as a first hard mask combination layer;
s6: forming a plurality of second through holes in the first hard mask combination layer, wherein the second through holes and the first columns are arranged at intervals in the row direction;
s7: forming a third sacrificial layer on the side wall of the second through hole to reduce the opening area of the second through hole;
s8: filling a fourth sacrificial layer in the remaining space in the second through hole to obtain a second column body located in the second through hole;
s9: removing the third sacrificial layer in the second through hole to obtain a second gap surrounding the second column body;
s10: filling a third hard mask layer in the second gap, wherein the third hard mask layer and the rest of the first hard mask combination layer are jointly used as a second hard mask combination layer;
s11: and removing the first cylinder and the second cylinder to obtain a plurality of third through holes in the hard mask second combination layer.
Optionally, the first hard mask layer is formed on a substrate, and the substrate includes a substrate layer and an inorganic material layer formed on the substrate layer.
Optionally, in the step S1, the forming the plurality of first vias in the first hard mask layer includes the following steps:
s1-1: forming a photoresist layer on the first hard mask layer;
s1-2: patterning the photoresist layer to obtain a plurality of photoresist layer through holes in the photoresist layer;
s1-3: etching the first hard mask layer by taking the patterned photoresist layer as a mask to obtain a plurality of first through holes;
s1-4: and removing the photoresist layer.
Optionally, in the step S2, the forming the first sacrificial layer on the sidewall of the first via includes the following steps:
s2-1: depositing the first sacrificial layer, wherein the first sacrificial layer covers the upper surface of the first hard mask layer, the side wall of the first through hole and the bottom surface of the first through hole;
s2-2: and removing the first sacrificial layer on the upper surface of the first hard mask layer and the bottom surface of the first through hole.
Optionally, the depositing comprises chemical vapor deposition or atomic layer deposition.
Optionally, the first sacrificial layer on the upper surface of the first hard mask layer and the bottom surface of the first through hole is removed by dry etching, wherein the etching gas used in the dry etching includes CF4、CH2F2、CHF3And C4F8Any one of the group formed.
Optionally, in the step S3, the forming the first pillar includes the following steps:
s3-1: depositing the second sacrificial layer, wherein the second sacrificial layer covers the upper surface of the first hard mask layer and is filled into the residual space in the first through hole;
s3-2: and removing the second sacrificial layer on the upper surface of the first hard mask layer.
Optionally, the second sacrificial layer on the upper surface of the first hard mask layer is removed by chemical mechanical polishing.
Optionally, in the step S5, the step of filling the second hard mask layer in the first gap includes the steps of:
s5-1: depositing the second hard mask layer, wherein the second hard mask layer covers the upper surface of the first hard mask layer and is filled into the first gap;
s5-2: and removing the second hard mask layer on the upper surface of the first hard mask layer.
Optionally, the second hard mask layer 11 on the upper surface of the first hard mask layer is removed by chemical mechanical polishing.
Optionally, in the step S6, the forming the second through holes in the first combination layer of the hard mask includes the following steps:
s6-1: forming a photoresist layer on the first hard mask layer;
s6-2: patterning the photoresist layer to obtain a plurality of photoresist layer through holes in the photoresist layer;
s6-3: etching the first hard mask layer by taking the patterned photoresist layer as a mask to obtain a plurality of second through holes;
s6-4: and removing the photoresist layer.
Optionally, in the step S7, the forming the third sacrificial layer on the sidewall of the second via includes the following steps:
s7-1: depositing the third sacrificial layer, wherein the third sacrificial layer covers the upper surface of the first combination layer of the hard mask, the upper surface of the first column, the side wall of the second through hole and the bottom surface of the second through hole;
s7-2: and removing the third sacrificial layer on the upper surface of the first combination layer of the hard mask, the upper surface of the first column and the bottom surface of the second through hole.
Optionally, the depositing comprises chemical vapor deposition or atomic layer deposition.
Optionally, in the step S7-2, the first sacrificial layer on the upper surface of the first combination layer of the hard mask, the upper surface of the first pillar, and the bottom surface of the first via is removed by dry etching, and an etching gas used in the dry etching includes CF4、CH2F2、CHF3And C4F8Any one of the group formed.
Optionally, in the step S8, the forming the second cylinder includes the following steps:
s8-1: depositing the fourth sacrificial layer, wherein the fourth sacrificial layer covers the upper surface of the first combination layer of the hard mask and is filled into the residual space in the second through hole;
s8-2: and removing the fourth sacrificial layer on the upper surface of the first combination layer of the hard mask.
Optionally, in the step S10, the step of filling the third hard mask layer in the second gap includes the steps of:
s10-1: depositing the third hard mask layer, wherein the third hard mask layer covers the upper surface of the first combination layer of the hard mask and is filled into the second gap;
s10-2: and removing the third hard mask layer on the upper surface of the first hard mask combination layer.
Optionally, the third hard mask layer 19 on the upper surface of the first hard mask combination layer is removed by chemical mechanical polishing.
Optionally, the first column and the second column are removed by dry etching or wet cleaning.
Optionally, the second through hole has the same opening size as the first through hole.
Optionally, the forming of the second via hole employs offset exposure with respect to the forming of the first via hole.
Optionally, the third via is used to form a bit line connection line of the dram.
Optionally, the first hard mask layer is made of any one of the groups consisting of polysilicon, silicon oxide, and silicon nitride, the first hard mask layer, the second hard mask layer, and the third hard mask layer are made of the same material, and the first sacrificial layer, the second sacrificial layer, the third sacrificial layer, and the fourth sacrificial layer are made of different materials from the first hard mask layer.
Optionally, the material of the first sacrificial layer includes silicon oxide, the material of the second sacrificial layer includes polysilicon, the material of the third sacrificial layer includes silicon oxide, and the material of the fourth sacrificial layer includes polysilicon.
The present invention also provides a semiconductor structure comprising:
a first hard mask layer;
the second hard mask layers are separately arranged in the first hard mask layer, the second hard mask layers are at least arranged in a row, and the second hard mask layers in the same row are arranged at equal intervals;
the plurality of third hard mask layers are separately arranged in the first hard mask layer and are arranged at intervals in the row direction with the second hard mask layer, and the first hard mask layer, the second hard mask layer and the third hard mask layer are jointly used as hard mask combination layers;
and the through holes are separately arranged in the hard mask combination layer, the through holes are at least arranged in one line, and the through holes in the same line are arranged at equal intervals, wherein one through hole is surrounded by the second hard mask layer and the other through hole is surrounded by the third hard mask layer in two adjacent through holes in the same line.
Optionally, the third hard mask layer and the second hard mask layer are connected to each other.
Optionally, the semiconductor structure further includes a substrate, the substrate includes a substrate layer and an inorganic material layer formed on the substrate layer, and the first hard mask layer, the second hard mask layer and the third hard mask layer are formed on the inorganic material layer.
Optionally, the opening shape of the through hole includes any one of a circle and a polygon.
Optionally, the aperture of the via is less than 65 nm.
Optionally, in the row direction, a distance between adjacent vias is less than 200 nm.
Optionally, a cross-sectional area of the third hard mask layer is greater than a cross-sectional area of the second hard mask layer.
As described above, the semiconductor structure and the method for forming a via hole according to the present invention have the following advantages: in the invention, a technology similar to Self-aligned Double Patterning (SADP) is adopted to realize the micro-shrinkage of the through hole, wherein the Critical Dimension (CD) of the through hole is micro-shrunk in a mode of alternating a secondary photoetching and a plurality of times of thin film deposition sacrificial layers and dry etching sacrificial layers, so as to realize the Double imaging of the through hole. The through hole forming method can form more through holes while reducing the CD of the through hole, thereby solving the problem that the through hole with smaller key size cannot be formed by direct exposure of yellow light.
Drawings
Fig. 1-10 illustrate a method of forming a plurality of first vias in a first hard mask layer according to the present invention.
Fig. 11-14 are schematic diagrams illustrating the formation of a first sacrificial layer on the sidewall of a first via according to the method for forming a via of the present invention.
Fig. 15-18 are schematic views illustrating a method for forming a via hole according to the present invention, filling a second sacrificial layer in a remaining space of the first via hole to obtain a first pillar located in the first via hole.
Fig. 19-20 are schematic diagrams illustrating the method for forming a via according to the present invention removing the first sacrificial layer in the first via to obtain a first void surrounding the first pillar.
FIGS. 21-24 are schematic diagrams illustrating the method for forming a via hole of the present invention filling a second hard mask layer in the first void to obtain a first combination layer of hard masks.
FIGS. 25-32 are schematic diagrams illustrating the formation of a plurality of second vias in the first combination layer of the hardmask according to the method of forming vias of the present invention.
FIGS. 33-36 are schematic views illustrating the formation of a third sacrificial layer on the sidewall of the second via according to the method for forming a via of the present invention.
Fig. 37-40 are schematic views illustrating a method for forming a via hole according to the present invention, filling the remaining space of the fourth sacrificial layer in the second via hole to obtain a second pillar in the second via hole.
Fig. 41-42 are schematic diagrams illustrating a method for forming a via hole according to the present invention, in which the third sacrificial layer in the second via hole is removed to obtain a second void surrounding the second pillar.
FIGS. 43-46 are schematic diagrams illustrating the method for forming a via hole of the present invention filling a third hard mask layer in the second gap to obtain a second combination layer of hard mask.
Fig. 47-48 illustrate schematic views of the method for forming a via hole of the present invention removing the first pillar and the second pillar to obtain a plurality of third via holes in the second combination layer of the hard mask.
FIG. 49 is a top view of a semiconductor structure of the present invention.
Description of the element reference numerals
1 substrate layer
2 layer of inorganic material
3 first hard mask layer
4 Photoresist layer
5 Photoresist layer through hole
6 first through hole
7 first sacrificial layer
8 second sacrificial layer
9 first cylinder
10 first gap
11 second hard mask layer
12 Photoresist layer
13 photoresist layer vias
14 second through hole
15 third sacrificial layer
16 fourth sacrificial layer
17 second column
18 second gap
19 third hard mask layer
20 third through hole
21. 22 through hole
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 49. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
The invention provides a method for forming a through hole, which comprises the following steps:
referring to fig. 1 to 10, step S1 is executed: providing a first hard mask layer 3, forming a plurality of first through holes 6 in the first hard mask layer 3, wherein the plurality of first through holes 6 are at least arranged in a row, and the plurality of first through holes 6 in the same row are arranged at equal intervals.
Specifically, as shown in fig. 1 and fig. 2, which are respectively a cross-sectional view and a top view of the first hard mask layer 3, in this embodiment, the first hard mask layer 3 is formed on a substrate, and the substrate includes a substrate layer 1 and an inorganic material layer 2 formed on the substrate layer 1. The substrate layer 1 may be a silicon wafer substrate, and the material of the inorganic material layer 2 includes, but is not limited to, any one of the group consisting of silicon Oxide (Oxide), silicon Nitride (Nitride), silicon carbide (SiC), and silicon oxynitride (SiON). The material of the first hard mask layer 3 includes, but is not limited to, any one of the group consisting of polysilicon (poly), silicon Oxide (Oxide), and silicon Nitride (Nitride), and in this embodiment, the material of the first hard mask layer 3 is silicon Nitride.
As an example, forming a plurality of the first vias 6 in the first hard mask layer 3 includes the following steps:
step S1-1: as shown in fig. 3 and 4, a photoresist layer 4 is formed on the first hard mask layer 3 by spin coating, wherein fig. 3 is a cross-sectional view of the present step, and fig. 4 is a top view of the present step;
step S1-2: as shown in fig. 5 and 6, the photoresist layer 4 is patterned by photolithography processes such as exposure and development to obtain a plurality of photoresist layer through holes 5 in the photoresist layer 4, wherein fig. 5 is a cross-sectional view of the present step, and fig. 6 is a top view of the present step;
step S1-3: as shown in fig. 7 and 8, the patterned photoresist layer 4 is used as a mask to etch the first hard mask layer 3 until the inorganic material layer 2 stops, so as to transfer the photoresist pattern to the first hard mask layer 3, thereby obtaining a plurality of first through holes 6, wherein fig. 7 is a cross-sectional view presented in this step, and fig. 8 is a top view presented in this step;
step S1-4: as shown in fig. 9 and fig. 10, the photoresist layer is removed by a wet or dry process, wherein fig. 9 is a cross-sectional view of the step, and fig. 10 is a top view of the step.
It should be noted that, in the present embodiment, the opening shape of the first through hole 6 is circular or substantially circular, and in other embodiments, the first through hole with other opening shapes may also be formed, and the protection scope of the present invention should not be limited excessively herein.
Referring to fig. 11 to 14, step S2 is executed: a first sacrificial layer 7 is formed on the sidewall of the first via 6 to reduce the open area of the first via 6.
Specifically, the material of the first sacrificial layer 7 includes, but is not limited to, SiO2、Si3N4And Si. It should be noted that the first sacrificial layer 7 and the first hard mask layer 3 are made of different materials. In this embodiment, the first hard mask layer 3 is made of silicon nitride, and the first sacrificial layer 7 is made of silicon oxide. The thickness of the first sacrificial layer 7 is determined by the size of the first via 6 and the degree of shrinkage, for example, the Critical Dimension (CD) of the first via after yellow exposure is 80nm, and a 20nm first sacrificial layer is formed, which can reduce the CD of the first via to 40 nm.
As an example, forming the first sacrificial layer 7 on the sidewall of the first via hole 6 includes the following steps:
step S2-1: as shown in fig. 11 and 12, a first sacrificial layer 7 is deposited by using a Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD) process, wherein the first sacrificial layer 7 covers the upper surface of the first hard mask layer 3, the sidewall of the first via 6 and the bottom surface of the first via 6, wherein fig. 11 is a cross-sectional view of this step, and fig. 12 is a top view of this step;
step S2-2: as shown in fig. 13 and 14, the first sacrificial layer 7 on the upper surface of the first hard mask layer 3 and the bottom surface of the first via 6 is removed by dry etching, wherein fig. 13 is a cross-sectional view of this step, and fig. 14 is a top view of this step.
As an example, a halogen-containing gas (e.g., CF) is used4、CH2F2、CHF3And C4F8Plasma gas) in a Capacitively Coupled Plasma (CCP) chamber or an inductively coupled plasma (IC)P) carrying out side wall and plane high-selectivity etching on the cavity, etching away the deposited films at the bottom and the top, and leaving the side walls to finally achieve the purpose of reducing the characteristic dimension.
Referring to fig. 15-18, step S3 is executed: and filling the remaining space of the second sacrificial layer 8 in the first through hole 6 to obtain a first column 9 positioned in the first through hole 6. In this step, the first-formed reduced through holes are filled into the sacrificial layer, so as to prepare for increasing the number of the through holes.
Specifically, the second sacrificial layer 8 and the first hard mask layer 3 are made of different materials. In this embodiment, the first hard mask layer 3 is made of silicon nitride, and the second sacrificial layer 8 is made of polysilicon.
As an example, forming said first cylinder 9 comprises the following steps:
step S3-1: as shown in fig. 15 and 16, a second sacrificial layer 8 is deposited, and the second sacrificial layer 8 covers the upper surface of the first hard mask layer 3 and fills the remaining space in the first via hole 6, wherein fig. 15 is a cross-sectional view of this step and fig. 16 is a top view of this step.
Step S3-2: as shown in fig. 17, fig. 18, which is a level view of fig. 17, a chemical mechanical polishing process or other processes is used to remove the second sacrificial layer 8 on the upper surface of the first hard mask layer 3, wherein fig. 17 is a cross-sectional view of this step and fig. 18 is a top view of this step.
Referring to fig. 19-20, step S4 is executed: and removing the first sacrificial layer 7 in the first through hole 6 by wet cleaning or dry etching to obtain a first gap 10 surrounding the first pillar 9, where fig. 19 is a cross-sectional view of the step, and fig. 20 is a top view of the step.
Referring to fig. 21 to 24, step S5 is executed: and filling a second hard mask layer 11 in the first gap 10, wherein the second hard mask layer 11 and the rest of the first hard mask layer 3 are jointly used as a first hard mask combination layer.
Specifically, the first hard mask layer 3 and the second hard mask layer 11 are made of the same material. In this embodiment, the first hard mask layer 3 and the second hard mask layer 11 are made of silicon nitride.
As an example, filling the second hard mask layer 11 in the first voids 10 comprises the steps of:
step S5-1: as shown in fig. 21 and 22, depositing the second hard mask layer 11, wherein the second hard mask layer 11 covers the upper surface of the first hard mask layer 3 and fills the first gap 10, wherein fig. 21 is a cross-sectional view of the present step, and fig. 22 is a top view of the present step;
step S5-2: as shown in fig. 23 and 24, the second hard mask layer 11 on the upper surface of the first hard mask layer 3 is removed by chemical mechanical polishing, and the first pillar 9 is used as an end point of the chemical mechanical polishing, wherein fig. 23 is a cross-sectional view of the present step, and fig. 24 is a top view of the present step.
Referring to fig. 25-32, step S6 is executed: a plurality of second through holes 14 are formed in the hard mask first combination layer, and the second through holes 14 and the first pillars 9 are arranged at intervals in the row direction.
Specifically, the second through hole 14 has the same opening size as the first through hole 6. The second through holes 14 are formed by staggered exposure relative to the first through holes 6, so that the purpose of forming a larger number of through holes is achieved.
As an example, forming a plurality of said second vias 14 in said hardmask first combined layer comprises the steps of:
step S6-1: as shown in fig. 25 and 26, a photoresist layer 12 is formed on the first hard mask layer 3 by offset spin-on (SOD) process, wherein fig. 25 is a cross-sectional view of the present step, and fig. 26 is a top view of the present step;
step S6-2: as shown in fig. 27 and 28, the photoresist layer 12 is patterned by photolithography processes such as exposure and development to obtain a plurality of photoresist layer through holes 13 in the photoresist layer 12, wherein fig. 27 is a cross-sectional view of the present step, and fig. 28 is a top view of the present step;
step S6-3: as shown in fig. 29 and fig. 30, the patterned photoresist layer is used as a mask, and the first hard mask layer 3 is etched until the inorganic material layer 2 stops, so as to obtain a plurality of second through holes 14, wherein fig. 29 is a cross-sectional view presented in this step, and fig. 30 is a top view presented in this step;
step S6-4: as shown in fig. 31 and fig. 32, the photoresist layer 12 is removed by wet etching or dry etching, wherein fig. 31 is a cross-sectional view of the step, and fig. 32 is a top view of the step.
Referring to fig. 33-36, step S7 is executed: a third sacrificial layer 15 is formed on the sidewall of the second via hole 14 to reduce the open area of the second via hole 14.
Specifically, the third sacrificial layer 15 and the first hard mask layer 3 are made of different materials. In this embodiment, the first hard mask layer 3 is made of silicon nitride, and the third sacrificial layer 15 is made of silicon oxide. The thickness of the third sacrificial layer 15 is determined by the size of the second via 14 and the degree of shrinkage, for example, the Critical Dimension (CD) of the second via after yellow exposure is 80nm, and a 20nm third sacrificial layer is formed, which can reduce the CD of the second via to 40 nm.
As an example, forming the third sacrificial layer 15 on the sidewall of the second via hole 14 includes the following steps:
step S7-1: as shown in fig. 33 and 34, a third sacrificial layer 15 is deposited by using a chemical vapor deposition method or an atomic layer deposition method, the third sacrificial layer 15 covers the upper surface of the first combination layer of the hard mask, the upper surface of the first pillar 9, the sidewall of the second via 14 and the bottom surface of the second via 14, wherein fig. 33 is a cross-sectional view of this step, and fig. 34 is a top view of this step;
step S7-2: as shown in fig. 35 and 36, the third sacrificial layer 15 on the upper surface of the first combination layer of the hard mask, the upper surface of the first pillar 9 and the bottom surface of the second via 14 is removed by dry etching, wherein fig. 35 is a cross-sectional view in this step, and fig. 36 is a top view in this step.
As an example, a halogen-containing gas (e.g., CF) is used4、CH2F2、CHF3And C4F8Plasma) is performed on the side wall and the plane high selectivity etching in a Capacitive Coupling Plasma (CCP) chamber or an Inductive Coupling Plasma (ICP) chamber, the deposited films at the bottom and the top are etched away, the side wall is left, and finally the purpose of reducing the characteristic dimension is achieved.
Referring to fig. 37 to 40, step S8 is executed: and filling the remaining space of the fourth sacrificial layer 16 in the second through hole 14 to obtain a second pillar 17 located in the second through hole 14.
Specifically, the fourth sacrificial layer 16 and the first hard mask layer 3 are made of different materials. In this embodiment, the first hard mask layer 3 is made of silicon nitride, and the fourth sacrificial layer 16 is made of polysilicon.
As an example, forming the second cylinder 17 comprises the steps of:
step S8-1: as shown in fig. 37 and 38, a fourth sacrificial layer 16 is deposited, and the fourth sacrificial layer 16 covers the upper surface of the first combination layer of the hard mask and fills the remaining space in the second via 14, wherein fig. 37 is a cross-sectional view of this step and fig. 38 is a top view of this step;
step S8-2: as shown in fig. 39 and 40, the fourth sacrificial layer 16 on the upper surface of the first combination layer of the hard mask is removed by chemical mechanical polishing or other methods, wherein fig. 39 is a cross-sectional view of this step and fig. 40 is a top view of this step.
Referring to fig. 41 to 42, step S9 is executed: and removing the third sacrificial layer 15 in the second via hole 14 by wet cleaning or dry etching to obtain a second gap 18 surrounding the second pillar 17, where fig. 41 is a cross-sectional view of the step, and fig. 42 is a top view of the step.
Referring to fig. 43 to 46, step S10 is executed: and filling a third hard mask layer 19 in the second gap 18, wherein the third hard mask layer 19 and the remaining hard mask first combination layer jointly serve as a hard mask second combination layer.
Specifically, the first hard mask layer 3, the second hard mask layer 11, and the third hard mask layer 19 are made of the same material. In this embodiment, the first hard mask layer 3, the second hard mask layer 11, and the third hard mask layer 19 are made of silicon nitride.
As an example, filling the third hard mask layer 19 in the second voids 18 comprises the steps of:
step S10-1: as shown in fig. 43 and 44, depositing the third hard mask layer 19, wherein the third hard mask layer 19 covers the upper surface of the first combination layer of hard masks and fills the second gap 18, wherein fig. 43 is a cross-sectional view of the present step, and fig. 44 is a top view of the present step;
step S10-2: as shown in fig. 45 and 46, the third hard mask layer 19 on the upper surface of the first combination layer of hard mask is removed by chemical mechanical polishing, and the second post 17 is used as the end point of the chemical mechanical polishing, wherein fig. 45 is a cross-sectional view of the step, and fig. 46 is a top view of the step.
Referring to fig. 47-48, step S11 is executed: and removing the first pillar 9 and the second pillar 17 by dry etching or wet cleaning to obtain a plurality of third through holes 20 in the second combined layer of the hard mask, where fig. 47 is a cross-sectional view in this step, and fig. 48 is a top view in this step.
At this moment, the key size of the through holes is reduced and the number of the through holes is doubled by means of secondary photoetching and alternate modes of film deposition sacrificial layers and dry etching sacrificial layers for multiple times. The third via 20 can be used to form a bit line connection of a dram.
The through hole forming method of the invention firstly transfers the through hole pattern after yellow light exposure to a lower layer material, deposits a sacrificial layer material, removes the top and bottom parts of the sacrificial layer by an etching method, and reserves the side wall part, thereby achieving the purpose of shrinkage cavity, and then fills the formed through hole with another sacrificial layer. And then, yellow light dislocation exposure is adopted, then the dislocation exposure photoetching pattern is transferred to a lower layer material, a sacrificial layer material is deposited, the top and bottom parts of the sacrificial layer are removed by an etching method, the side wall part is reserved, so that the purpose of shrinkage is achieved, the formed through hole is filled by using another sacrificial layer, and finally the other sacrificial layer is removed, so that the method similar to Self-aligned Double imaging (SADP for short) through hole formation can be realized. The through hole forming method can form more through holes while reducing the CD of the through hole, thereby solving the problem that the through hole with smaller key size cannot be formed by direct exposure of yellow light.
Example two
The present invention further provides a semiconductor structure, please refer to fig. 49, which is a top view of the semiconductor structure, and includes a first hard mask layer 3, a plurality of second hard mask layers 11, a plurality of third hard mask layers 19, and a plurality of through holes, wherein the plurality of second hard mask layers 11 and the plurality of third hard mask layers 19 are separately disposed in the first hard mask layer 3, wherein the plurality of second hard mask layers 11 are at least arranged in a row, the plurality of second hard mask layers 11 in the same row are arranged at equal intervals, and the third hard mask layers 19 and the second hard mask layers 11 are arranged at intervals in a row direction.
Specifically, the first hard mask layer 3, the second hard mask layer 11 and the third hard mask layer 19 are collectively used as a hard mask combination layer, the plurality of through holes are separately arranged in the hard mask combination layer, the plurality of through holes are at least arranged in a row, and the plurality of through holes in the same row are arranged at equal intervals, wherein one through hole 21 is surrounded by the second hard mask layer 11, and the other through hole 22 is surrounded by the third hard mask layer 19 in two adjacent through holes in the same row.
In this embodiment, the first hard mask layer 3, the second hard mask layer 11, and the third hard mask layer 19 are made of the same material, but the first hard mask layer 3, the second hard mask layer 11, and the third hard mask layer 19 are formed at different stages.
Specifically, the third hard mask layer 19 is connected to the second hard mask layer 11, and the cross-sectional area of the third hard mask layer 19 is larger than that of the second hard mask layer 11. In this embodiment, the third hard mask layer 19 is tangent to the via 21 surrounded by the second hard mask layer 11. In other embodiments, the third hard mask layer 19 may not reach the boundary of the via 21.
As an example, the semiconductor structure further includes a substrate, the substrate includes a substrate layer and an inorganic material layer formed on the substrate layer, and the first hard mask layer 3, the second hard mask layer 11, and the third hard mask layer 19 are all formed on the inorganic material layer. The substrate layer may be a silicon wafer substrate, and the material of the inorganic material layer includes, but is not limited to, any one of the group consisting of silicon Oxide (Oxide), silicon Nitride (Nitride), silicon carbide (SiC), and silicon oxynitride (SiON). The first hard mask layer is made of any one of a group including, but not limited to, polysilicon (poly), silicon Oxide (Oxide), and silicon Nitride (Nitride).
As an example, the opening shape of the through hole includes any one of a circle and a polygon, the aperture of the through hole is less than 65nm, and the distance between adjacent through holes in the row direction is less than 200 nm. It should be noted that, the distance between adjacent through holes is the distance between the center points of adjacent through holes.
In summary, the semiconductor structure and the method for forming a via hole of the present invention adopt a technology similar to Self-aligned Double Patterning (SADP) to achieve the shrinking of the via hole, wherein the Critical Dimension (CD) of the via hole is shrunk by performing a second photolithography and alternately depositing a sacrificial layer and etching the sacrificial layer by a dry method for multiple times, so as to achieve the Double imaging of the via hole. The through hole forming method can form more through holes while reducing the CD of the through hole, thereby solving the problem that the through hole with smaller key size cannot be formed by direct exposure of yellow light. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (16)
1. A method for forming a via hole, comprising the steps of:
providing a first hard mask layer, forming a plurality of first through holes in the first hard mask layer, wherein the first through holes are at least arranged in a row, and the first through holes in the same row are arranged at equal intervals;
forming a first sacrificial layer on the side wall of the first through hole to reduce the opening area of the first through hole;
filling a second sacrificial layer in the residual space in the first through hole to obtain a first column positioned in the first through hole;
removing the first sacrificial layer in the first through hole to obtain a first gap surrounding the first column;
filling a second hard mask layer in the first gap, wherein the second hard mask layer and the rest of the first hard mask layer are jointly used as a first hard mask combination layer;
forming a plurality of second through holes in the first hard mask combination layer, wherein the second through holes and the first columns are arranged at intervals in the row direction;
forming a third sacrificial layer on the side wall of the second through hole to reduce the opening area of the second through hole;
filling a fourth sacrificial layer in the remaining space in the second through hole to obtain a second column body located in the second through hole;
removing the third sacrificial layer in the second through hole to obtain a second gap surrounding the second column body;
filling a third hard mask layer in the second gap, wherein the third hard mask layer and the rest of the first hard mask combination layer are jointly used as a second hard mask combination layer;
and removing the first cylinder and the second cylinder to obtain a plurality of third through holes in the hard mask second combination layer.
2. The method of claim 1, wherein forming the plurality of first vias in the first hard mask layer comprises:
forming a photoresist layer on the first hard mask layer, wherein the first hard mask layer is formed on a substrate, and the substrate comprises a substrate layer and an inorganic material layer formed on the substrate layer;
patterning the photoresist layer to obtain a plurality of photoresist layer through holes in the photoresist layer;
etching the first hard mask layer by taking the patterned photoresist layer as a mask to obtain a plurality of first through holes;
and removing the photoresist layer.
3. The method of claim 1, wherein forming the first sacrificial layer on the sidewall of the first via comprises:
depositing the first sacrificial layer, wherein the first sacrificial layer covers the upper surface of the first hard mask layer, the side wall of the first through hole and the bottom surface of the first through hole;
and removing the first sacrificial layer on the upper surface of the first hard mask layer and the bottom surface of the first through hole.
4. The method of forming a via according to claim 1, wherein forming the first pillar comprises:
depositing the second sacrificial layer, wherein the second sacrificial layer covers the upper surface of the first hard mask layer and is filled into the residual space in the first through hole;
and removing the second sacrificial layer on the upper surface of the first hard mask layer by adopting a chemical mechanical polishing method.
5. The method of claim 1, wherein filling the second hard mask layer in the first voids comprises:
depositing the second hard mask layer, wherein the second hard mask layer covers the upper surface of the first hard mask layer and is filled into the first gap;
and removing the second hard mask layer on the upper surface of the first hard mask layer by adopting a chemical mechanical polishing method.
6. The method of claim 1, wherein forming the second plurality of vias in the first combination of hardmask layers comprises:
forming a photoresist layer on the first hard mask layer;
patterning the photoresist layer to obtain a plurality of photoresist layer through holes in the photoresist layer;
etching the first hard mask layer by taking the patterned photoresist layer as a mask to obtain a plurality of second through holes;
and removing the photoresist layer.
7. The method of claim 1, wherein forming the third sacrificial layer on the sidewall of the second via comprises:
depositing the third sacrificial layer, wherein the third sacrificial layer covers the upper surface of the first combination layer of the hard mask, the upper surface of the first column, the side wall of the second through hole and the bottom surface of the second through hole;
removing the third sacrificial layer on the upper surface of the first combination layer of the hard mask, the upper surface of the first column and the bottom surface of the second through hole; and forming the second post comprises the steps of:
depositing the fourth sacrificial layer, wherein the fourth sacrificial layer covers the upper surface of the first combination layer of the hard mask and is filled into the residual space in the second through hole;
and removing the fourth sacrificial layer on the upper surface of the first combination layer of the hard mask.
8. The method of claim 1, wherein the removing the first pillar and the second pillar by dry etching or wet cleaning, and the filling the third hard mask layer in the second gap comprises:
depositing the third hard mask layer, wherein the third hard mask layer covers the upper surface of the first combination layer of the hard mask and is filled into the second gap;
and removing the third hard mask layer on the upper surface of the first hard mask combination layer by adopting a chemical mechanical polishing method.
9. The method of forming a via according to claim 1, wherein: the size of the second through hole is the same as that of the first through hole, and dislocation exposure is adopted for forming the second through hole relative to forming the first through hole.
10. The method of forming a via according to claim 1, wherein: the material of the first hard mask layer comprises any one of groups formed by polysilicon, silicon oxide and silicon nitride, the first hard mask layer, the second hard mask layer and the third hard mask layer are made of the same material, the first sacrificial layer, the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer are made of different materials with the first hard mask layer, the material of the first sacrificial layer comprises silicon oxide, the material of the second sacrificial layer comprises polysilicon, the material of the third sacrificial layer comprises silicon oxide, and the material of the fourth sacrificial layer comprises polysilicon.
11. A semiconductor structure, comprising:
a first hard mask layer;
the second hard mask layers are separately arranged in the first hard mask layer, the second hard mask layers are at least arranged in a row, and the second hard mask layers in the same row are arranged at equal intervals;
the plurality of third hard mask layers are separately arranged in the first hard mask layer and are arranged at intervals in the row direction with the second hard mask layer, and the first hard mask layer, the second hard mask layer and the third hard mask layer are jointly used as hard mask combination layers;
and the through holes are separately arranged in the hard mask combination layer, the through holes are at least arranged in one line, and the through holes in the same line are arranged at equal intervals, wherein one through hole is surrounded by the second hard mask layer and the other through hole is surrounded by the third hard mask layer in two adjacent through holes in the same line.
12. The semiconductor structure of claim 11, wherein: the third hard mask layer is interconnected with the second hard mask layer.
13. The semiconductor structure of claim 11, wherein: the opening shape of the through hole includes any one of a circle and a polygon.
14. The semiconductor structure of claim 11, wherein: the aperture of the through hole is less than 65 nm.
15. The semiconductor structure of claim 11, wherein: and in the row direction, the distance between adjacent through holes is less than 200 nm.
16. The semiconductor structure of claim 11, wherein: the cross-sectional area of the third hard mask layer is greater than the cross-sectional area of the second hard mask layer.
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