CN115602536A - Method for improving etching stop layer depression in side wall etching - Google Patents
Method for improving etching stop layer depression in side wall etching Download PDFInfo
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- CN115602536A CN115602536A CN202211164141.8A CN202211164141A CN115602536A CN 115602536 A CN115602536 A CN 115602536A CN 202211164141 A CN202211164141 A CN 202211164141A CN 115602536 A CN115602536 A CN 115602536A
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- etching
- sacrificial layer
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- side wall
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Abstract
The invention provides a method for improving the etching stop layer depression in side wall etching, which comprises the steps of providing a substrate, forming a lamination layer on the substrate, and forming a sacrificial layer on the lamination layer; forming a photoresist layer on the sacrificial layer, opening the photoresist layer by photoetching to expose the sacrificial layer below the photoresist layer, and etching part of the exposed sacrificial layer to form a groove so that part of the sacrificial layer is reserved between the bottom of the groove and the lamination layer to form a core mold pattern; forming a mask layer on the core mold pattern; etching the hard mask layer and the sacrificial layer below the hard mask layer to the upper part of the lamination layer to form a side wall, so that the sacrificial layer except the lower part of the side wall is exposed; and etching to remove the exposed sacrificial layer. According to the method, when the mandrel pattern is etched, a layer of amorphous silicon is left in the non-mandrel pattern region by adjusting the etching time, and when the side wall is etched, the layer of amorphous silicon left in the non-mandrel pattern region is used as an etching buffer layer to protect the etching stop layer at the bottom, so that the problem of sinking is solved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for improving the depression of an etching stop layer in side wall etching.
Background
In the prior art, a FinFET (fin transistor) with a three-dimensional structure is adopted as a transistor of an integrated circuit in a 14nm process. The process can obtain the three-dimensional structure of the FinFET only after hard mask layer deposition, core mold pattern (mandrel) etching (core mold pattern is formed by etching a sacrificial layer), side wall etching, SIT (side wall image transfer) and Fin etching.
At present, the sidewall etching process includes the following steps:
step one, providing a substrate 101, wherein a lamination layer is formed on the substrate 101, and a sacrificial layer 105 is formed on the lamination layer to form a structure shown in fig. 1;
step two, forming a photoresist layer on the sacrificial layer 105, opening the photoresist layer by photolithography to expose the sacrificial layer 105 therebelow, etching the exposed sacrificial layer 105 to form a groove to expose the lamination layer 105 therebelow, so as to form a mandrel pattern 106, thereby forming the structure shown in fig. 2;
step three, forming a mask layer 107 on the mandrel pattern 106 to form the structure shown in fig. 3;
etching the hard mask layer 107 to the upper part of the laminated layer to form a side wall 108, wherein when the side wall 108 is etched, a depression 109 is generated on the laminated layer on the non-core-mold area;
and step five, etching to remove the exposed sacrificial layer 105, and forming the structure shown in fig. 4.
There is a problem that the over-etching is performed twice in order to remove the mandrel pattern, causing a recess 109 to be generated in an etch stop layer (typically, an oxide layer) of a non-mandrel pattern region. This problem will be passed on to subsequent processes, resulting in Fin structures of different lengths.
In order to solve the above problems, a novel method for improving the dishing of the etching stop layer in the sidewall etching is needed.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a method for improving the dishing of an etch stop layer in sidewall etching, which is used to solve the problem in the prior art that in a sidewall etching process, two over-etches are performed to remove a mandrel pattern, which causes the dishing of the etch stop layer in a non-mandrel pattern region, and this problem is transferred to a subsequent process, resulting in the formation of Fin structures with different lengths.
In order to achieve the above and other related objects, the present invention provides a method for improving the recess of an etch stop layer in sidewall etching, comprising:
providing a substrate, wherein a laminated layer is formed on the substrate, and a sacrificial layer is formed on the laminated layer;
step two, forming a photoresist layer on the sacrificial layer, opening the photoresist layer by photoetching to expose the sacrificial layer below the photoresist layer, and etching the partially exposed sacrificial layer to form a groove so that a part of the sacrificial layer is reserved between the bottom of the groove and the lamination layer to form a core mold pattern;
step three, forming a mask layer on the core mold pattern;
etching the hard mask layer and the sacrificial layer below the hard mask layer to the upper part of the laminated layer to form a side wall, so that the sacrificial layer except the lower part of the side wall is exposed;
and fifthly, etching to remove the exposed sacrificial layer.
Preferably, the substrate in the first step is a silicon substrate.
Preferably, the laminated layer in the first step is composed of a first oxide layer, a nitride layer and a second oxide layer from bottom to top.
Preferably, the material of the sacrificial layer in the first step is amorphous silicon.
Preferably, in the second step, the groove is formed by etching part of the exposed sacrificial layer by a dry etching method.
Preferably, the material of the mask layer in the third step is silicon nitride.
Preferably, the etching method in the fourth step is dry etching.
Preferably, in the fifth step, the exposed sacrificial layer is removed by a wet etching method.
Preferably, any of the methods described above are used for 14nm and below technology node processes.
As described above, the method for improving the etching stop layer recess in the sidewall etching of the present invention has the following beneficial effects:
compared with the situation that the amorphous silicon of the non-core mold pattern area is completely etched in the prior art, the method has the advantages that when the core mold pattern is etched, the etching time is adjusted, so that a layer of amorphous silicon is remained in the non-core mold pattern area, and when the side wall is etched, the remaining layer of amorphous silicon of the non-core mold pattern area is used as an etching buffer layer to protect an etching stop layer at the bottom, so that the problem of sinking is solved.
Drawings
FIG. 1 is a schematic diagram illustrating the formation of a sacrificial layer according to the prior art;
FIG. 2 is a schematic diagram of a prior art mandrel pattern formation;
FIG. 3 is a schematic diagram of a prior art deposited mask layer;
FIG. 4 is a schematic diagram illustrating the formation of a sidewall in the prior art;
FIG. 5 is a schematic diagram of forming a sacrificial layer according to the present invention;
figure 6 shows a schematic view of a pattern of the forming mandrel of the present invention;
FIG. 7 is a schematic view of a deposited mask layer of the present invention;
FIG. 8 is a schematic view of forming a sidewall of the present invention;
FIG. 9 is a schematic process flow diagram of the present invention;
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Referring to fig. 9, the present invention provides a method for improving the recess of the etch stop layer in the sidewall etching, including:
step one, providing a substrate 201, forming a lamination layer on the substrate 201, and forming a sacrificial layer 205 on the lamination layer to form the structure shown in fig. 5;
preferably, the substrate 201 in the first step is a silicon substrate 201.
Preferably, the stack in the first step is composed of a first oxide layer 202, a nitride layer 203, and a second oxide layer 204 from bottom to top, the second oxide layer 204 can be used as an etching barrier layer, the material of the first and second oxide layers is typically silicon dioxide, and the material of the nitride layer 203 is typically silicon nitride.
Preferably, the material of the sacrificial layer 205 in the first step is amorphous silicon, and is typically formed by a chemical vapor deposition method.
Step two, forming a photoresist layer on the sacrificial layer 205, opening the photoresist layer by photolithography to expose the sacrificial layer 205 therebelow, etching a part of the exposed sacrificial layer 205 to form a groove, and leaving a part of the sacrificial layer 205 between the bottom of the groove and the lamination layer to form a mandrel pattern 206, wherein compared with the prior art in which amorphous silicon in the non-mandrel region of the mandrel pattern 106 is completely etched, a layer of amorphous silicon is left in the non-mandrel region by adjusting the etching time to form the structure shown in fig. 6;
preferably, in the second step, a portion of the exposed sacrificial layer 205 is etched by dry etching to form a recess.
Step three, forming a mask layer 207 on the mandrel pattern 206 to form the structure shown in fig. 7;
preferably, the material of the mask layer 207 in step three is silicon nitride, and the formation method thereof is usually chemical vapor deposition.
Etching the hard mask layer 207 and the sacrificial layer 205 below the hard mask layer to the upper part of the lamination to form a side wall 208, so that the sacrificial layer 205 except the lower part of the side wall 208 is exposed, and when the side wall 208 is etched, a layer of amorphous silicon remained in the region of the non-core mold pattern 207 is used as an etched buffer layer to protect an etching stop layer at the bottom, thereby improving the sinking problem;
preferably, the etching method in the fourth step is dry etching.
Step five, the exposed sacrificial layer 205 is removed by etching, and the structure shown in fig. 8 is formed.
Preferably, in step five, the exposed sacrificial layer 205 is removed by wet etching.
Preferably, the etch stop layer at the bottom is protected by a layer of amorphous silicon remaining in the non-mandrel pattern 207 regions to act as an etch buffer, which forms a recess 209 that is smaller than the recess 109 of FIG. 4.
Preferably, any of the methods described above are used for 14nm and below technology node processes.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
In summary, when the mandrel pattern is etched, compared with the situation that the amorphous silicon in the non-mandrel pattern area is completely etched in the prior art, the mandrel pattern area is enabled to remain a layer of amorphous silicon by adjusting the etching time, and when the sidewall is etched, the remaining layer of amorphous silicon in the non-mandrel pattern area is used as an etching buffer layer to protect an etching stop layer at the bottom, so that the problem of dishing is solved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.
Claims (9)
1. A method for improving the etching stop layer depression in the side wall etching is characterized by at least comprising the following steps:
providing a substrate, wherein a laminated layer is formed on the substrate, and a sacrificial layer is formed on the laminated layer;
step two, forming a photoresist layer on the sacrificial layer, opening the photoresist layer by photoetching to expose the sacrificial layer below the photoresist layer, and etching the partially exposed sacrificial layer to form a groove so that a part of the sacrificial layer is reserved between the bottom of the groove and the lamination to form a core mold pattern;
step three, forming a mask layer on the core mold pattern;
etching the hard mask layer and the sacrificial layer below the hard mask layer to the upper part of the laminated layer to form a side wall, so that the sacrificial layer except the lower part of the side wall is exposed;
and fifthly, etching to remove the exposed sacrificial layer.
2. The method for improving the recession of the etch stop layer in the sidewall etching as claimed in claim 1, wherein: the substrate in the first step is a silicon substrate.
3. The method for improving the etching stop layer recess in the sidewall etching according to claim 1, wherein: the lamination in the first step is composed of a first oxidation layer, a nitridation layer and a second oxidation layer from bottom to top.
4. The method for improving the etching stop layer recess in the sidewall etching according to claim 1, wherein: in the first step, the sacrificial layer is made of amorphous silicon.
5. The method for improving the recession of the etch stop layer in the sidewall etching as claimed in claim 1, wherein: and in the second step, etching part of the exposed sacrificial layer by a dry etching method to form the groove.
6. The method for improving the recession of the etch stop layer in the sidewall etching as claimed in claim 1, wherein: and the material of the mask layer in the third step is silicon nitride.
7. The method for improving the etching stop layer recess in the sidewall etching according to claim 1, wherein: the etching method in the fourth step is dry etching.
8. The method for improving the etching stop layer recess in the sidewall etching according to claim 1, wherein: and fifthly, removing the exposed sacrificial layer by a wet etching method.
9. The method for improving the etching stop layer recess in the sidewall etching according to claim 1, wherein: the method is used for the technology of technology nodes of 14nm and below.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211164141.8A CN115602536A (en) | 2022-09-23 | 2022-09-23 | Method for improving etching stop layer depression in side wall etching |
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| CN202211164141.8A CN115602536A (en) | 2022-09-23 | 2022-09-23 | Method for improving etching stop layer depression in side wall etching |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116207039A (en) * | 2023-04-28 | 2023-06-02 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor structure and semiconductor structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116207039A (en) * | 2023-04-28 | 2023-06-02 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor structure and semiconductor structure |
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