CN114093762A - Method for manufacturing honeycomb pattern and method for manufacturing DRAM - Google Patents

Method for manufacturing honeycomb pattern and method for manufacturing DRAM Download PDF

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Publication number
CN114093762A
CN114093762A CN202010751563.XA CN202010751563A CN114093762A CN 114093762 A CN114093762 A CN 114093762A CN 202010751563 A CN202010751563 A CN 202010751563A CN 114093762 A CN114093762 A CN 114093762A
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layer
pattern
honeycomb
mask
manufacturing
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车世浩
周娜
李俊杰
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Priority to CN202010751563.XA priority Critical patent/CN114093762A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

The invention relates to a manufacturing method of a honeycomb pattern and a manufacturing method of a Dynamic Random Access Memory (DRAM), belongs to the technical field of semiconductors, and solves the problems of increased production cost, process difference and low product yield caused by the increase of the number of photoetching processes for obtaining the honeycomb pattern in the prior art. The manufacturing method of the hole comprises the steps of providing a semiconductor substrate → depositing a first mask material, forming a first mask material layer → etching the first mask material layer to obtain the first mask layer → depositing the material layer → etching the side wall material layer → filling → removing the side wall material → forming a first honeycomb-shaped pattern with a first pattern and a second pattern. The invention reduces the times of photoetching process, reduces the production cost and increases the product yield.

Description

Method for manufacturing honeycomb pattern and method for manufacturing DRAM
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a honeycomb pattern and a manufacturing method of a DRAM (dynamic random access memory).
Background
Memory is a device or component used in digital systems to store large amounts of information and is an important component in computers and digital devices. Memories may be divided into two broad categories, Random Access Memories (RAMs) and Read Only Memories (ROMs). The RAM includes DRAM, PRAM, MRAM, and the like, and the capacitor is one of the key components for manufacturing these RAMs. Each memory cell in a DRAM device consists of 1T1C (i.e., 1 transistor and 1 capacitor).
With the integration of semiconductor manufacturing processes and the gradual reduction of pattern pitches, in the prior art, a honeycomb pattern must be formed by a repeated photolithography patterning process when forming a DRAM capacitor to solve the problem, but the increase of photolithography (Litho) process times leads to the increase of production cost, the increase of process time, and the loss, and as semiconductor patterns become finer, the patterning method using photolithography process reaches its limit.
Disclosure of Invention
In view of the above analysis, the present invention is directed to a method for manufacturing a honeycomb pattern and a method for manufacturing a DRAM, so as to solve the problems of increased production cost, process variation, and low product yield caused by the increased number of photolithography processes for obtaining the honeycomb pattern in the conventional process.
The purpose of the invention is mainly realized by the following technical scheme:
in one aspect, the present invention provides a first method for manufacturing a honeycomb pattern, comprising: providing a semiconductor substrate, wherein a layer to be etched is arranged on the semiconductor substrate; forming a first mask material layer on the layer to be etched; etching the first mask material layer to obtain a first mask layer with a first pattern; depositing a side wall material layer; etching the side wall material layer to form a side wall and a plurality of holes which are positioned on the side wall of the first pattern, wherein the holes expose the upper surface of the layer to be etched; filling the plurality of holes with a second mask material to form a second mask layer with a second pattern; and removing the side walls to form a first honeycomb-shaped pattern with a first pattern and a second pattern.
Based on a further improvement of the above manufacturing method, the first mask layer having the first pattern includes a plurality of first pillars located at six vertices and a center of the first regular hexagon.
Based on the further improvement of the manufacturing method, the deposition thickness of the side wall material layer is larger than half of the distance between two adjacent first columns.
In a further improvement of the above manufacturing method, the step of filling the plurality of holes with the second mask material includes: covering the surfaces of the first side wall and the second side wall with the second mask material; and after the second mask material is used for filling the plurality of holes and before the side wall material layer is removed, etching back is further included so as to etch the second mask material on the surfaces of the first side wall and the second side wall.
Based on the further improvement of the manufacturing method, the back etching adopts dry etching.
Based on a further improvement of the manufacturing method, the second mask layer with the second pattern is composed of a plurality of second pillars, and the second pillars are located at the centers of equilateral triangles formed by three adjacent first pillars.
Based on a further improvement of the above manufacturing method, the cross section of the first cylinder and the second cylinder comprises a circle, a square, a rectangle or a diamond.
Based on the further improvement of the manufacturing method, the side wall material and the second mask material are different materials.
Based on the further improvement of the manufacturing method, the material of the side wall is silicon oxide, silicon nitride or polysilicon.
On the other hand, the invention also provides a first DRAM manufacturing method, which comprises any step of the manufacturing method of the honeycomb-shaped pattern, and the first honeycomb-shaped pattern is used as a mask to etch the layer to be etched to form honeycomb-shaped columns; forming a storage medium layer on the pillar; forming an upper electrode on the storage medium layer; the layer to be etched comprises a conductive material, and the layer to be etched, the storage medium layer and the upper electrode form a cylindrical capacitor.
In addition, the present invention provides a second method for manufacturing a honeycomb pattern, comprising any one of the steps of the first method for manufacturing a honeycomb pattern, and forming a third mask material layer over the entire surface of the semiconductor substrate after forming the first honeycomb mask; etching back the third mask material layer until the top of the first honeycomb-shaped mask is exposed; removing the first honeycomb mask to leave a second honeycomb pattern that is inverse to the first honeycomb pattern.
The invention also provides a second DRAM manufacturing method, which comprises a second honeycomb pattern manufacturing method and a step of etching the layer to be etched by taking the second honeycomb pattern as a mask to form honeycomb-shaped distributed capacitor holes; and forming a cylindrical capacitor consisting of a lower electrode, a dielectric layer and an upper electrode in the capacitance hole.
Compared with the prior art, the invention can realize at least one of the following beneficial effects:
1. the method for forming the honeycomb pattern does not need to carry out a plurality of times of photoetching (Litho) processes, because photoetching machines used in the photoetching (Litho) processes are very expensive, and the photoresist is high in cost and consumable material, so that the more times of photoetching, the higher the cost. The manufacturing method only needs one photoetching (Litho) process, and the manufacturing cost is greatly reduced.
2. Because the photolithography process has the problem of alignment deviation, if the deviation is too large, the size and the interval of the pattern are inconsistent with the preset value, so that the product yield is reduced. The method for forming the honeycomb pattern only needs to carry out a photoetching (Litho) process once, does not generate process difference due to multiple photoetching processes, and greatly increases the yield of products.
In the invention, the technical schemes can be combined with each other to realize more preferable combination schemes. Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, wherein like reference numerals are used to designate like parts throughout.
FIG. 1 is a top view and a schematic cross-sectional view at A-A of a first pattern in a method of manufacturing a honeycomb pattern according to an embodiment of the present invention;
FIG. 2 is a schematic top view and a schematic cross-sectional view at A-A of a deposited side wall material layer in the method for manufacturing a honeycomb pattern according to the embodiment of the invention;
FIG. 3 is a schematic top view and a schematic cross-sectional view at A-A of an etched spacer material layer in the method for manufacturing a honeycomb pattern according to the embodiment of the present invention;
FIG. 4 is a top view and a corresponding cross-sectional view A-A of a second masking material used to fill the trenches in a method of fabricating a honeycomb pattern in accordance with an embodiment of the present invention;
FIG. 5 is a schematic top view and a schematic cross-sectional view at A-A of a back etching performed in the method for manufacturing a honeycomb pattern according to the embodiment of the present invention;
FIG. 6 is a schematic top view and a schematic cross-sectional view at A-A of main etching performed in the method for manufacturing a honeycomb pattern according to the embodiment of the present invention;
FIG. 7 is a schematic top view and a schematic cross-sectional view at A-A of a honeycomb semiconductor substrate pattern obtained after removing the first mask material layer and the second mask material layer in the method for manufacturing a honeycomb pattern according to the embodiment of the present invention;
fig. 8 is a diagram illustrating a positional relationship between adjacent first pillars forming the first pattern according to an embodiment of the present invention.
Reference numerals
101-a semiconductor substrate; 102-a first cylinder; 201-bump; 202-side wall material layer; 301-side walls; 303-holes; 501-a second column body; p1 — first pattern; p2 — second pattern; p3-third pattern; p4-honeycomb semiconductor substrate pattern.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
Example one
In one embodiment of the present invention, a method of making a honeycomb pattern is disclosed. Hereinafter, a method of manufacturing the honeycomb pattern will be described in detail with reference to fig. 1 to 8.
First, as shown in fig. 1, a semiconductor substrate (not shown) is provided on which a layer 101 to be etched is to be etched. The material of the semiconductor substrate may be single crystalline silicon.
Next, a first mask material is formed over the layer to be etched 101. The first mask material may include polysilicon, silicon nitride, an Amorphous Carbon Layer (ACL), or a spin-on organic hard mask (SOH). The process of forming the first mask material may be Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD).
Referring to fig. 1, after forming a first mask material layer, a first patterning process is performed on the first mask material layer to obtain a first mask layer having a first pattern P1, and the first mask layer having a first pattern P1 may be composed of a plurality of first pillars 102 located at corners and centers of a regular hexagon. The cross-section of the first cylinder comprises a circle, a square, a rectangle or a diamond.
In one possible embodiment, the first patterning process may etch the first mask material layer using a photolithography process. After obtaining the first mask layer with the first pattern P1, a process of depositing a sidewall material layer follows, which will be described in detail with reference to fig. 2.
And depositing side wall materials on both sides and the top surface of the first column to form side wall material layers. Due to the influence of the first pillar on the first mask layer, a protrusion 201 is correspondingly formed on the sidewall material layer 202.
In a possible embodiment, the deposition thickness of the sidewall material layer 202 is greater than half of the distance between two adjacent first pillars, so that the adjacent sidewall material layers 202 can be expanded to intersect after deposition, that is, the deposition thickness of the sidewall material layer 202 is greater than d/2, where d is the distance between two adjacent first pillars 102, as shown in fig. 8.
For example, when the distance between two first pillars is 60nm, the first partial sidewall material layer 202 is required to be deposited with a thickness greater than 30 nm.
In addition, in the BB direction perpendicular to AA, due to the effect between the adjacent first pillars, and since the thickness of the deposited sidewall material layer is greater than half of the distance between two first pillars, other protrusions 201 are generated. Although not shown in the drawings, in each oblique direction, other protrusions formed due to the deposition thickness of the sidewall material layer between the adjacent first pillars are also obtained.
In another possible embodiment, the material of the sidewall spacer may be silicon oxide, silicon nitride or polysilicon.
After the sidewall material layer is deposited, an anisotropic etching process is required to be performed on the sidewall material layer. Referring to fig. 3, after anisotropic etching is performed on the sidewall material layer, a sidewall 301 and a plurality of holes 303 are formed on the sidewall of the first pattern.
In an alternative embodiment, the sidewall material layer may be self-aligned etched by using a fluorine-containing plasma dry etching method according to different sidewall materials.
As shown in fig. 4, a filling process is next performed. Specifically, the filling process may be to fill the second mask material only in the plurality of holes to form a second mask layer with a second pattern P2, and then remove the sidewall material to etch the semiconductor substrate 101 with the first mask layer and the second mask layer as masks to form a first honeycomb pattern with a first pattern P1 and a second pattern P2.
The second mask layer having the second pattern P2 is composed of a plurality of second pillars 501, and the second pillars 501 are located at the centers of equilateral triangles composed of three adjacent first pillars 102, as shown in fig. 5. The second pillars 501 are obtained by filling a second mask material in the plurality of holes. The cross section of the second cylinder comprises a circle, a square, a rectangle or a rhombus.
Note that, although both the first pattern P1 and the second pattern P2 are regular hexagons, the size of the regular hexagons of the second pattern P2 is smaller than that of the first pattern P1.
In addition, the filling process can also be as follows: in addition to filling the plurality of holes with the second masking material, the second masking material is also deposited on the surface of the sidewall 301.
After depositing the second mask material on the surface of the sidewall 301, an etch-back process is added to etch the second mask material on the surface of the sidewall 301. The etch back process is shown in fig. 5. In this embodiment, the second mask material may be etched back by dry etching. The etch-back process is performed to obtain a third pattern P3, i.e., a honeycomb-like hard mask pattern, which is a combination of the first mask layer and the second mask layer, referring to fig. 5.
Illustratively, the second mask material may be polysilicon, silicon nitride, amorphous carbon layer, or a spin-on organic hard mask.
It should be noted that the second mask material and the sidewall material must be different materials. This is because, in the subsequent etch-back process, it is necessary to ensure that only the sidewall material is etched away, but the second mask material cannot be etched away, so as to form the honeycomb pattern. If the second mask material and the side wall material are the same material, the second mask material and the side wall material are etched together in the etch-back process, and the honeycomb pattern cannot be formed at all.
In one possible embodiment, the upper portion of the first pillar 102 is also etched away, and the height of the first pillar 102 that is not etched is the same as the height of the second mask material in the hole that is not etched away, as shown in fig. 5.
Referring to fig. 6, after the etching back process, the sidewalls are further etched away to expose the first pillar 102 and the second pillar 501. And etching the layer to be etched by taking the first mask layer and the second mask layer as masks.
Next, the first mask layer material and the second mask layer material are removed to form a first honeycomb pattern having a first pattern and a second pattern, as shown in fig. 7.
The honeycomb pattern of the present invention is manufactured by forming a complicated honeycomb pattern using a Double Patterning Technology (DPT) without additionally performing a photolithography (Litho) process.
Specifically, the double patterning technique is to form a first pattern by using a photolithography process, deposit a material of the double patterning technique as a film material, form a sidewall on the sidewall, and etch the sidewall using the sidewall as a mask to form 1/2-pitch patterns.
In addition, in the manufacturing method for forming the honeycomb pattern, the deposition of the sidewall material layer and the subsequent processes thereof may be performed more than once. Forming a Pattern (Pattern) with the multiple of 2 when the side wall material layer is deposited for the first time and the subsequent process is carried out; and forming a Pattern (Pattern) with the multiple of 4 when the side wall material layer is deposited twice and the subsequent processes are carried out.
Compared with the prior art, the method for forming the honeycomb pattern does not need to carry out a photolithography (Litho) process for multiple times, because a photoetching machine used in the photolithography (Litho) process is very expensive, and the photoresist is a consumable material with higher cost, so the more times the photoetching is carried out, the higher the cost is. The embodiment only needs one photoetching process, and the manufacturing cost is greatly reduced.
In addition, because the photolithography process has the problem of alignment deviation, if the deviation is too large, the dimension and the interval of the pattern are inconsistent with the preset value, so that the product yield is reduced. The method for forming the honeycomb pattern only needs to carry out a photoetching (Litho) process once, does not generate process difference due to multiple photoetching processes, and greatly increases the yield of products.
Example two
Another embodiment of the present invention discloses a method for manufacturing a DRAM, which, based on the manufacturing method of the embodiment, further includes: etching the layer to be etched by taking the first honeycomb-shaped pattern as a mask to form a honeycomb-shaped cylinder; forming a storage medium layer on the honeycomb cylinder; and forming an upper electrode on the storage medium layer.
The layer to be etched comprises a conductive material, and the layer to be etched, the storage medium layer and the upper electrode form a cylindrical capacitor.
EXAMPLE III
In another embodiment of the present invention, another method for manufacturing a honeycomb pattern is disclosed, which comprises the following steps in addition to the manufacturing method of the first embodiment: after forming the first honeycomb mask, forming a third mask material layer on the whole surface of the semiconductor substrate; etching back the third mask material layer until the top of the first honeycomb-shaped mask is exposed; the first honeycomb mask is removed to leave a second honeycomb pattern that is the inverse of the first honeycomb pattern.
Example four
This embodiment provides another method for manufacturing a DRAM, which includes, in addition to the manufacturing method of the third embodiment: etching the layer to be etched by taking the second honeycomb-shaped pattern as a mask to form honeycomb-shaped distributed capacitor holes; a cylindrical capacitor composed of a lower electrode, a dielectric layer and an upper electrode is formed in the capacitor hole.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (12)

1. A method of manufacturing a honeycomb pattern, comprising:
providing a semiconductor substrate, wherein a layer to be etched is arranged on the semiconductor substrate;
forming a first mask material layer on the layer to be etched;
etching the first mask material layer to obtain a first mask layer with a first pattern;
depositing a side wall material layer;
etching the side wall material layer to form a side wall and a plurality of holes which are positioned on the side wall of the first pattern, wherein the holes expose the upper surface of the layer to be etched;
filling the plurality of holes with a second mask material to form a second mask layer with a second pattern;
and removing the side walls to form a first honeycomb-shaped pattern with a first pattern and a second pattern.
2. The method of manufacturing a honeycomb pattern according to claim 1, wherein the first mask layer having the first pattern comprises a plurality of first pillars located at six vertices and the center of the first regular hexagon.
3. The method of claim 1, wherein the sidewall material layer is deposited to a thickness greater than half of a spacing between two adjacent first pillars.
4. The method for manufacturing a honeycomb pattern according to claim 1, wherein the step of filling the plurality of holes with a second mask material comprises:
covering the surfaces of the first side wall and the second side wall with the second mask material; and after the second mask material is used for filling the plurality of holes and before the side wall material layer is removed, etching back is further included so as to etch the second mask material on the surfaces of the first side wall and the second side wall.
5. The method for manufacturing a honeycomb pattern according to claim 4, wherein the etching back is dry etching.
6. A method for fabricating a honeycomb pattern according to any one of claims 2 to 5, wherein the second mask layer having the second pattern is composed of a plurality of second pillars located at the centers of equilateral triangles composed of three adjacent first pillars.
7. The method of manufacturing a honeycomb pattern according to claim 6, wherein the cross-section of the first cylinder and the second cylinder includes a circle, a square, a rectangle, or a diamond.
8. The method of claim 6, wherein the sidewall material and the second mask material are different materials.
9. A method for manufacturing a honeycomb pattern according to any one of claims 1 to 5, wherein the material of the sidewall is silicon oxide, silicon nitride or polysilicon.
10. A method of manufacturing a DRAM, characterized in that the method comprises the steps of any one of claims 1 to 9; and
etching the layer to be etched by taking the first honeycomb-shaped pattern as a mask to form a honeycomb-shaped cylinder;
forming a storage medium layer on the pillar;
forming an upper electrode on the storage medium layer;
the layer to be etched comprises a conductive material, and the layer to be etched, the storage medium layer and the upper electrode form a cylindrical capacitor.
11. A method for manufacturing a honeycomb pattern, comprising the steps of any one of claims 1 to 9; and
after forming the first honeycomb mask, forming a third mask material layer on the whole surface of the semiconductor substrate;
etching back the third mask material layer until the top of the first honeycomb-shaped mask is exposed;
removing the first honeycomb mask to leave a second honeycomb pattern that is inverse to the first honeycomb pattern.
12. A method of manufacturing a DRAM, characterized in that said method comprises the steps of claim 11, and
etching the layer to be etched by taking the second honeycomb-shaped pattern as a mask to form honeycomb-shaped distributed capacitor holes;
and forming a cylindrical capacitor consisting of a lower electrode, a dielectric layer and an upper electrode in the capacitance hole.
CN202010751563.XA 2020-07-30 2020-07-30 Method for manufacturing honeycomb pattern and method for manufacturing DRAM Pending CN114093762A (en)

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CN202010751563.XA CN114093762A (en) 2020-07-30 2020-07-30 Method for manufacturing honeycomb pattern and method for manufacturing DRAM

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010751563.XA CN114093762A (en) 2020-07-30 2020-07-30 Method for manufacturing honeycomb pattern and method for manufacturing DRAM

Publications (1)

Publication Number Publication Date
CN114093762A true CN114093762A (en) 2022-02-25

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