CN114068310A - Etching method for holes in square arrangement - Google Patents

Etching method for holes in square arrangement Download PDF

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Publication number
CN114068310A
CN114068310A CN202010754924.6A CN202010754924A CN114068310A CN 114068310 A CN114068310 A CN 114068310A CN 202010754924 A CN202010754924 A CN 202010754924A CN 114068310 A CN114068310 A CN 114068310A
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Prior art keywords
pattern
material layer
layer
mask
etching
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Chinese (zh)
Inventor
尹洪权
贺晓彬
刘金彪
李亭亭
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Priority to CN202010754924.6A priority Critical patent/CN114068310A/en
Publication of CN114068310A publication Critical patent/CN114068310A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention discloses an etching method of holes in square arrangement, which relates to the technical field of semiconductors and aims to obtain a hole structure with the size and the distance meeting the requirements of a semiconductor device, so that the problems of poor contact and electric leakage are solved. The etching method of the holes in square arrangement comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a layer to be etched; forming a double-layer mask material layer on the layer to be etched; processing the double-layer mask material layer by adopting a twice photoetching process to obtain a first pattern structure and a second pattern structure which are distributed in a staggered manner; forming side walls on the side walls of the first pattern structure and the second pattern structure; removing the first pattern and the second pattern, and reserving the side wall; and etching the layer to be etched by taking the side wall as a mask to form the holes arranged in a square shape.

Description

Etching method for holes in square arrangement
Technical Field
The invention relates to the field of manufacturing of semiconductor devices, in particular to an etching method of holes arranged in a square shape.
Background
As the integration degree of semiconductor devices increases, the size of the semiconductor devices is gradually reduced. In the manufacturing process of the existing small-sized semiconductor device, the sizes of the contact holes and the distances between the contact holes cannot reach required values due to the limitation of a photoetching process. Therefore, the specifications of the contact resistance between wirings and the leakage current between wirings of the semiconductor device do not meet the requirements of the semiconductor device, and the problems of poor contact and leakage current are easily caused.
Disclosure of Invention
The invention aims to provide an etching method of holes arranged in a square mode, so that a hole structure with the size and the distance meeting the requirements of a semiconductor device is obtained, and the problems of poor contact and electric leakage are solved.
In a first aspect, the present invention provides a method for etching holes arranged in a square, the method comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a layer to be etched;
forming a double-layer mask material layer on the layer to be etched;
processing the double-layer mask material layer by adopting a twice photoetching process to obtain a first pattern structure and a second pattern structure which are distributed in a staggered manner;
forming side walls on the side walls of the first pattern structure and the second pattern structure;
removing the first pattern and the second pattern;
and etching the layer to be etched by taking the side walls as masks to form holes in square arrangement.
Compared with the prior art, the etching method for the holes arranged in the square shape provided by the invention has the advantages that the first pattern structure and the second pattern structure which are distributed in a staggered mode are formed by utilizing two photoetching processes. Because the first pattern structure and the second pattern structure are distributed in a staggered way, namely, a partial area of the second pattern structure formed by the second photoetching is formed in the gap of the first pattern structure formed by the first photoetching. On the basis, side walls are formed on the side walls of the first pattern structure and the second pattern structure, after the first pattern structure and the second pattern structure on the first substrate are removed, the layer to be etched is etched by taking the side walls as masks, and holes in square arrangement are formed. The finally obtained holes in the square arrangement are obtained by taking the side walls formed on the side walls of the first pattern structure and the second pattern structure which are formed by two times of photoetching and are distributed in a staggered manner as masks, so that the holes in the square arrangement manufactured by the method are relatively holes manufactured by only one time of photoetching process, the distance between adjacent holes in the square arrangement is reduced, and the problem that the sizes of the holes and the distance between the adjacent holes cannot reach required values due to the photoetching process is solved. And the problems of poor contact and electric leakage of the semiconductor device caused by the fact that the size of the holes and the distance between the holes cannot reach the required value are solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings, when a diagram n shows a plan view of a structure at a certain stage in a method for etching holes arranged in a square shape, a diagram nA shows a cross-sectional view taken along a direction a-a in the diagram n, a diagram nB shows a cross-sectional view taken along a direction B-B in the diagram n, and a diagram nC shows a cross-sectional view taken along a direction C-C in the diagram n;
FIGS. 1-13 show top views of structures obtained at various stages in an embodiment of an etching method for forming a square array of holes;
3A-6A show cross-sectional views along section lines A-A' in FIGS. 3-6;
FIGS. 7B-8B show cross-sectional views taken along section lines B-B' in FIGS. 7-8; and
fig. 13C shows a cross-sectional view along section line C-C' of fig. 13.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed. In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In semiconductor devices, contact holes are widely used for electrical connection between conductive structures. As the integration degree of semiconductor devices increases, the size of the semiconductor devices is gradually reduced. In the manufacturing process of the existing small-sized semiconductor device, due to the limitation of a photoetching process, the sizes of contact holes and the distances between the contact holes cannot reach required values, so that the specifications of contact resistance between wirings of the semiconductor device and electric leakage between the wirings do not meet the requirements of the semiconductor device, and the problems of poor contact and electric leakage are easily caused.
Accordingly, the embodiment of the invention provides an etching method for holes in square arrangement.
FIGS. 1-13 show top views of structures obtained at various stages in an embodiment of an etching method for forming a square array of holes; 3A-6A show cross-sectional views along section lines A-A' in FIGS. 3-6; FIGS. 7B-8B show cross-sectional views taken along section lines B-B' in FIGS. 7-8; and FIG. 13C shows a cross-sectional view along section line C-C' of FIG. 13.
Referring to fig. 1, a layer to be etched 20 may be formed on a semiconductor substrate 10. The semiconductor substrate 10 may be any one of a silicon substrate, a silicon oxide substrate, a silicon nitride substrate, a carbon substrate, a tungsten nitride substrate, and a titanium nitride substrate.
Referring to fig. 2, a two-layer mask layer is formed on the layer to be etched 20. Specifically, the bilayer masking material layer includes a bottom masking material layer 30 and a top masking material layer 40. As a possible implementation, the bottom mask material layer 30 and the top mask material layer 40 have the same stack structure. The laminated structure can be a carbon material layer, a silicon oxynitride material layer and an oxide mask material layer which are laminated together from bottom to top.
After the forming of the double-layer mask material layer, the etching method of the square holes in the embodiment of the invention further includes: a first lithographic pattern is formed on the top layer of masking material using a lithographic process.
Illustratively, referring to fig. 3, 3A, 4 and 4A, forming a first lithographic pattern on the top mask material layer using a lithographic process includes: a first layer of photolithographic patterning material 501 is deposited over the top layer of masking material 40. The first lithographic pattern material layer 501 may be a laminated structure of a carbon material layer and a silicon oxynitride material layer. A first photoresist pattern 502 having a first photolithography pattern is formed on the first photolithography pattern material layer 501 using a photolithography process. And etching the first photoetching pattern material layer 501 by taking the first photoetching pattern 502 as a mask until the oxide material layer 403 in the top mask material layer is exposed, and removing the first photoetching pattern 502 to obtain a first photoetching pattern 503.
Specifically, the forming of the first photoresist pattern 502 having the first photolithography pattern on the first photolithography pattern material layer 501 using a photolithography process includes: a photoresist is coated on the first photoresist pattern material layer 501 and then processed using a process such as exposure, development, etc., thereby forming a first photoresist pattern 502 on the first photoresist pattern material layer 501.
The etching can be performed on the first photoetching pattern material layer by using etching liquid with high etching selectivity, and the etching rate of the etching liquid on the first photoetching pattern material layer is far higher than that of the etching liquid on the first photoresist pattern material layer. And stopping etching to expose the top mask material layer by controlling the etching time. When the first photoetching pattern material layer is etched to the top mask material layer, the etching liquid basically cannot generate an etching effect on the first photoresist pattern. At this time, the same pattern as the first photoresist pattern is formed on the top mask material layer, and the first photoresist pattern on the top of the pattern is removed to obtain a first photoresist pattern 503.
Referring to fig. 5 and 5A, the oxide material layer in the top mask material layer is etched using the first photolithography pattern as a mask, so as to obtain a top mask pattern 504.
To form the second lithographic pattern using the second photolithography process, a second lithographic pattern may be formed using a photolithography process on the layer of silicon oxynitride material in the top layer of mask material.
Illustratively, forming a second lithographic pattern on the layer of silicon oxynitride material in the top layer of mask material using a lithographic process includes: and forming a second photoetching pattern material layer on the silicon oxynitride material layer in the top mask material layer around the top mask pattern.
Referring to fig. 6 and 6A, in order to simplify the planarization process, the top of the second photolithographic pattern material layer 601 may be flush with the top of the top mask pattern 504. Specifically, the second lithography pattern material layer 601 may be a stacked structure of a carbon material layer and a silicon oxynitride material layer.
Thereafter, referring to fig. 7 and 7B, a second photoresist pattern 602 having a second photolithography pattern is formed on the second photolithography pattern material layer using a photolithography process. It is understood that the second photoresist pattern 602 is formed in the same manner as the first photoresist pattern. Finally, the second photoresist pattern 602 may be used as a second lithography pattern.
Refer to fig. 8 and 8B. And etching the top mask material and the bottom mask layer by taking the top mask pattern and the second photoetching pattern as masks to obtain a first pattern structure 701 and a second pattern structure 702 which are distributed in a staggered manner.
As a specific example, the process of forming the first pattern structure 701 and the second pattern structure 702 may specifically be: and etching the second photoetching pattern material layer and the oxide material layer in the top mask layer by taking the second photoetching pattern as a mask, and continuously etching by taking the top mask pattern and the second photoetching pattern as masks until the layer to be etched 20 is exposed to obtain a bottom mask pattern. The carbon material layer and the silicon oxynitride material layer in the bottom mask pattern are remained to obtain a first pattern structure 701 and a second pattern structure 702. Referring to fig. 8, the first pattern structures 701 and the second pattern structures 702 are alternately distributed on the layer to be etched 20.
Referring to fig. 8B, the first pattern structure 701 includes a plurality of first pillars; every fourth first column forms a first square pattern 703. The second pattern structure 702 includes a plurality of second pillars, and each four second pillars form a second square pattern 704; a second pillar is formed at the center of each first square pattern 703, and a first pillar is formed at the center of each second square pattern 704. In the structure, the first pattern structure 701 and the second pattern structure 702 are formed by utilizing two photoetching processes, so that the limitation of the photoetching process is improved, and the distance between the first column and the adjacent second column is reduced. Similarly, the distance between the second column body and the adjacent first column body is reduced, and the size of a hole formed subsequently can be improved.
Illustratively, to reduce process manufacturing difficulty, the cross-sectional shapes of the first cylinder and the second cylinder include a circle, a square, a long direction, or a diamond.
Illustratively, each of the first pillars in the first pattern structure includes a carbon layer and a silicon oxynitride layer stacked together from bottom to top. Each second pillar in the second pattern structure includes a carbon layer and a silicon oxynitride layer stacked together from bottom to top. The carbon material layer is an amorphous carbon layer or a carbon organic film formed by a spin coating method.
Fig. 9 shows a cross-sectional view of a structure after a spacer material layer is deposited on the first pattern structure and the second pattern structure, and fig. 10 shows a cross-sectional view of another structure after a spacer material layer is deposited on the first pattern structure and the second pattern structure. Referring to fig. 9 and 10, a sidewall material layer 801 is deposited on the first pattern structure 701 and the second pattern structure 702. The thickness of the side wall material layer can be determined according to the distance between the first column and the adjacent first column, the distance between the second column and the adjacent second column and the required parameters of the honeycomb-shaped holes. For example, when the distance between the first pillar and the adjacent first pillar is large, the diameter of the required honeycomb-shaped hole is small, and the distance between the holes is relatively large, the thickness of the side wall material layer may be set to be greater than half of the distance between the first pillar and the adjacent second pillar.
Referring to fig. 9 and 10, in the embodiment of the present invention, the process of forming the spacer material layer 801 on the first pattern structure 701, the second pattern structure 702, and the layer to be etched 20 may be: sidewall materials are deposited on the upper surface and the sidewalls of the first pattern structure 701, the upper surface and the sidewalls of the second structure pattern 702, and the layer to be etched 20, so as to form a sidewall material layer 801.
For example, the method for depositing the sidewall material may be CVD (Chemical Vapor Deposition), or ALD (Atomic Layer Deposition).
Illustratively, the sidewall spacer material includes one or more of a silicon material, a silicon oxide material, a silicon nitride material, a titanium nitride material, and a tungsten nitride material.
Fig. 11 shows a cross-sectional view after forming a sidewall with the structure of fig. 9. Fig. 12 shows a cross-sectional view after forming a sidewall with the structure of fig. 10.
The forming of the side wall may include: and etching the side wall material layer by adopting an anisotropic etching method to form side walls 802 on the side walls of the first pattern structure and the second pattern structure.
As an example, in the anisotropic etching method, the first pattern structure, the second pattern structure and the sidewall material may be processed by using plasma, so as to retain the sidewall material layers of the sidewalls of the first pattern structure and the second pattern structure, and obtain the sidewall. And the selection ratio of etching gas in the plasma to the first pattern structure and the second pattern structure is higher than that of the material layer to be etched. Illustratively, the plasma includes one or more of oxygen, nitrogen, and hydrogen.
As another example, the first pattern structure, the second pattern structure, and the sidewall material may be processed by wet etching, so as to retain the sidewall material layer of the sidewalls of the first pattern structure and the second pattern structure, and obtain the sidewall. During wet etching, the first pattern structure and the second pattern structure may be removed by using an etching solution with a high selective etching ratio, and the sidewall material layers of the sidewalls of the first pattern structure and the second pattern structure are retained, so as to obtain the sidewall 802.
Referring to fig. 13 and 13A, after obtaining the sidewall 802, the layer to be etched 20 is etched using the sidewall 802 as a mask until the substrate is exposed, and after removing the sidewall, holes 803 arranged in a square shape are formed in the layer to be etched 20. Illustratively, the layer to be etched 20 may be a stacked structure formed by overlapping a plurality of support layers and oxide layers.
In the etching method of the honeycomb-shaped holes, provided by the invention, the first pattern structure and the second pattern structure which are distributed in a staggered manner are formed by utilizing two photoetching processes. Because the first pattern structure and the second pattern structure are distributed in a staggered way, namely, a partial area of the second pattern structure formed by the second photoetching is formed in the gap of the first pattern structure formed by the first photoetching. On the basis, side walls are formed on the side walls of the first pattern structure and the second pattern structure, after the first pattern structure and the second pattern structure on the first substrate are removed, the layer to be etched is etched by taking the side walls as masks, and holes in square arrangement are formed. The finally obtained square-arranged holes are obtained by taking the side walls formed on the side walls of the first pattern structure and the second pattern structure which are formed by two times of photoetching and are distributed in a staggered manner as masks, so that the square-arranged holes are relatively holes which are manufactured by only one time of photoetching process, the distance between adjacent holes in the contact structure is reduced, and the problem that the sizes of the contact holes and the distance between the contact holes cannot reach required values due to the limitation of the photoetching process is solved. And the problems of poor contact and electric leakage of the semiconductor device caused by the fact that the size of the contact holes and the distance between the contact holes cannot reach the required value are solved.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (12)

1. A method for etching holes in square arrangement is characterized by comprising the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a layer to be etched;
forming a double-layer mask material layer on the layer to be etched;
processing the double-layer mask material layer by adopting a twice photoetching process to obtain a first pattern structure and a second pattern structure which are distributed in a staggered manner;
forming side walls on the side walls of the first pattern structure and the second pattern structure;
removing the first pattern and the second pattern, and reserving the side wall;
and etching the layer to be etched by taking the side walls as masks to form holes in square arrangement.
2. The method of etching holes in square arrangement according to claim 1, wherein the first pattern structure comprises a plurality of first pillars, and every four first pillars form a first square structure;
the second pattern structure comprises a plurality of second columns, and every four second columns form a second square structure;
the center of each first square structure is provided with one second cylinder, and the center of each second square structure is provided with one first cylinder.
3. The method according to claim 2, wherein the forming of the sidewalls on the sidewalls of the first pattern structure and the second pattern structure comprises:
depositing a side wall material layer on the first pattern structure and the second pattern structure; the thickness of the side wall material layer is larger than half of the distance between the first column and the adjacent second column;
and etching the side wall material layer by adopting an anisotropic etching method to form side walls on the side walls of the first pattern structure and the second pattern structure.
4. The method of etching a hole having a square arrangement according to claim 2, wherein the cross-sectional shapes of the first and second pillars include a circle, a square, a long direction, or a diamond.
5. The method of etching a square array of holes of claim 2, wherein the first pillar and the second pillar each comprise a carbon layer.
6. The method of etching a square array of holes of claim 1, wherein the bi-layer mask material layer comprises a bottom mask material layer and a top mask material layer stacked together from bottom to top;
and/or the top mask material layer and the bottom mask material layer respectively comprise a carbon material layer, a silicon oxynitride material layer and an oxide material layer which are laminated together from bottom to top.
7. The method of claim 6, wherein the processing the bilayer mask material layer by two photolithography processes to obtain the first and second patterns in a staggered arrangement comprises:
forming a first photolithographic pattern on the top mask material layer by utilizing a photolithographic process;
etching the oxide material layer in the top mask material layer by taking the first photoetching pattern as a mask to obtain a top mask pattern;
forming a second photoetching pattern on the silicon oxynitride material layer in the top mask material layer by utilizing a photoetching process;
and etching the carbon material layer, the silicon oxynitride material layer and the bottom mask layer in the top mask material by taking the top mask pattern and the second photoetching pattern as masks to obtain a first pattern structure and a second pattern structure which are distributed in a staggered manner.
8. The method of claim 6, wherein the forming a first lithographic pattern on the top masking material layer using a lithographic process comprises:
forming a first photolithographic pattern material layer on the top mask material layer;
forming a first photoresist pattern having a first photolithography pattern on the first photolithography pattern material layer using a photolithography process;
and etching the first photoetching pattern material layer by taking the first photoetching pattern as a mask until the top mask material layer is exposed, and removing the first photoetching pattern to obtain a first photoetching pattern.
9. The method of claim 8, wherein forming a second lithographic pattern on the layer of silicon oxynitride material in the top mask material layer using a lithographic process comprises:
forming a second photoetching pattern material layer on the silicon oxynitride material layer in the top mask material layer around the top mask pattern, wherein the top of the second photoetching pattern material layer is flush with the top of the top mask pattern;
and forming a second photoresist pattern with a second photoetching pattern on the second photoetching pattern material layer by utilizing a photoetching process, wherein the second photoresist pattern is used as the second photoetching pattern.
10. The method according to claim 7, wherein the step of etching the carbon material layer, the silicon oxynitride material layer and the bottom mask layer in the top mask material by using the top mask pattern and the second lithography pattern as masks to obtain the first pattern structure and the second pattern structure in a staggered distribution comprises:
etching the carbon material layer, the silicon oxynitride material layer and the bottom mask layer in the top mask material by taking the top mask pattern and the second photoetching pattern as masks until the layer to be etched is exposed, so as to obtain a bottom mask pattern;
and reserving the carbon material layer and the silicon oxynitride material layer in the bottom mask pattern to obtain a first pattern structure and a second pattern structure which are distributed in a staggered mode.
11. The method for etching holes in a square arrangement according to any of claims 6 to 10, wherein the carbon material layer is an amorphous carbon layer or a carbonaceous organic film formed by spin coating.
12. The method of etching a square array of holes of any of claims 1-10, wherein the sidewall material comprises one or more of a silicon material, a silicon oxide material, a silicon nitride material, a titanium nitride material, and a tungsten nitride material.
CN202010754924.6A 2020-07-30 2020-07-30 Etching method for holes in square arrangement Pending CN114068310A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024087320A1 (en) * 2022-10-27 2024-05-02 长鑫存储技术有限公司 Method for forming semiconductor structure and semiconductor structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024087320A1 (en) * 2022-10-27 2024-05-02 长鑫存储技术有限公司 Method for forming semiconductor structure and semiconductor structure

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