KR20090072794A - Semiconductor memory device having a capacitor of double-layer cylinder structure and method for forming the same - Google Patents

Abstract

A semiconductor memory device having a capacitor of a double layer cylinder structure and a manufacturing method thereof are provided to arrange a storage node of high density by changing an arrangement of the storage node into a diamond shape. An electrode pillar and a bottom storage node(310) of a cylindrical type are arranged on a semiconductor substrate(300) by turns. A first dielectric film(312) is formed on a surface of the bottom storage node and the electrode pillar. A bottom plate electrode(314) is formed on the first dielectric film. An interlayer insulation film(316) is formed on the substrate on which the bottom plate electrode is formed, and exposes the electrode pillar. A top storage node(328) of a cylindrical type is formed on the interlayer insulation film, and is connected to the electrode pillar. The bottom storage node is arranged into a diamond shape.

Description

Semiconductor memory device having a capacitor of double-layer cylinder structure and method for manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a highly integrated semiconductor memory device having a capacitor having a multilayer cylinder structure, and a method of manufacturing the same.

As the degree of integration of semiconductor memory devices increases and design rules rapidly decrease, it becomes more difficult to implement a capacitor having sufficient capacitance in a limited area. In particular, in the case of volatile memory devices such as DRAM, a refresh process is required to periodically replenish charges in order to continuously store data in a cell. The flash process consumes a lot of power, which can be very disadvantageous, especially for mobile products. Therefore, it is necessary to overcome this problem by increasing the refresh period.

In order to increase the refresh period of the memory device, there is a method of increasing the capacitance Cs in the cell or decreasing the parasitic capacitance Cb parasitic in the cell. As a method for securing a certain level of capacitance (Cs), various methods, such as using a dielectric film having a large dielectric constant, increasing the effective area of a capacitor, or reducing the distance between electrodes, have been implemented. Among these, efforts have been made to form a cylindrical storage electrode, increase the height of the cylinder, and increase the diameter of the cylinder as much as possible to increase the area of the capacitor.

However, due to the drastic reduction of design rules, the diameter of the cylinder is significantly reduced compared to the previous generation technology, and the height of the cylinder is further increased to compensate for the reduction in capacitance. This increase in the height of the cylinders increases the difficulty of subsequent processes, such as etching for forming contact holes, resulting in further increases in the step between the cell area and the peripheral circuit area.

On the other hand, in the case of semiconductor memory devices, particularly DRAM devices, as integration is advanced, efforts to reduce chip size have been made. As an example of such an effort, a case of changing a cell structure, specifically, a planar arrangement or layout of active regions may be considered. Currently, the layout of the active area is an 8F2 structure, in which two storage nodes are arranged on one active area. In the case of the 8F2 structure, when a circular cylinder storage node is employed, the space between the storage node contact and the storage node can be offset to maintain the same distance from neighboring storage nodes. There is an advantage that can form.

1 is a diagram illustrating an arrangement of cells of a conventional DRAM having an 8F2 structure.

Referring to FIG. 1, two storage nodes 111 and 112 are arranged in one active area 100. The storage nodes 111 and 112 of the first column are shifted down, and the storage nodes 121, 122 and 123 of the second column adjacent thereto are shifted up. Therefore, the final layout of the storage node is changed to a rhombus rather than a square layout. This is arranged in a rhombus form to form a storage node, usually consisting of the following process.

First, an etch stop layer is formed on a semiconductor substrate on which a storage node contact is formed, and then a mold insulating layer is stacked thereon in one layer or multiple layers. Although the height of the final cylinder is about 12,000 mm 3, the height of the mold insulating film is about 13,000 mm 3 in consideration of the loss in the subsequent etching process. Thereafter, a photolithography process is performed to etch the mold insulating layer and the etch stop layer corresponding to the inner surface of the cylinder to expose the storage node contacts. Titanium nitride (TiN) with good step coverage is deposited on the front surface to form a storage electrode, and then etched back and the mold insulating film is removed using a cleaning or etching apparatus. The node is formed. Next, a dielectric film is deposited on the front surface of the cylindrical storage node, and then a conductive film for the upper electrode is deposited to complete the cylindrical capacitor.

According to the conventional method of manufacturing a cylindrical capacitor, there are some problems due to the rapid reduction of design rules. In other words, it is necessary to maintain a certain gap between the cylinder for forming the storage node and the cylinder in order to proceed with the subsequent dielectric film deposition process, and sticking between the cylinders during the dip out process of removing the mold insulating film outside the cylinder. You can prevent it. Normally, when the design rule is 66 nm, the spacing between cylinders should be maintained at approximately 80 nm or more, and mass production is considered suitable when the diameter of the cylinder is about 100 nm. In this situation, if the design rule is reduced to 50 nm, assuming that the cylinder spacing is reduced to 70 nm, the diameter of the cylinder is only 70 nm, making it difficult to form a storage node of this size during manufacturing. If the diameter of the cylinder is small, the difficulty of the etching process increases, so that not only the desired profile is formed, but also the area in which the dielectric film is formed is reduced, and the cell capacitance Cs is drastically reduced. To compensate for the cell capacitance (Cs) caused by the reduction in the diameter of the cylinder as a whole, the height of the cylinder must be approximately 1.6 times, which means that the difficulty of forming the cylindrical storage node is that much higher.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor memory device having a structure capable of manufacturing a highly integrated memory device by securing sufficient cell capacitance without increasing process difficulty.

Another object of the present invention is to provide a method for manufacturing a highly integrated semiconductor memory device capable of securing sufficient cell capacitance without increasing process difficulty.

In order to achieve the above technical problem, a semiconductor memory device according to the present invention includes a cylindrical lower storage node and an electrode pillar, which are alternately arranged so as not to be adjacent to each other, and formed on a surface of the lower storage node and the electrode pillar on a semiconductor substrate. On the interlayer insulating film formed on the first dielectric film, the lower plate electrode formed on the first dielectric film, the resultant product on which the lower plate electrode is formed, and the electrode pillar, and on the interlayer insulating film, the electrode pillar It characterized in that it comprises a cylindrical upper storage node formed to connect with.

The lower storage node may be arranged in a rhombus shape.

The lower storage node and the upper storage node may be made of titanium nitride (TiN).

The upper storage node may be connected to the electrode pole through a contact formed in the interlayer insulating layer.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, including forming a storage node contact on a semiconductor substrate so that two storage nodes are arranged in one active region, and a cylinder connected to the storage node contact. Forming a storage node and an electrode pillar of a type, and alternately disposing the storage node and the electrode pillar so that the cylinders do not neighbor each other, and forming a first dielectric layer and a lower plate electrode on the surfaces of the storage node and the electrode pillar. Forming an interlayer insulating film covering the resultant; etching the interlayer insulating film so that the electrode pillars are exposed; and on the interlayer insulating film on the electrode pillars, a cylindrical upper portion connected to the electrode pillars. Forming a storage node.

The storage node contacts are preferably arranged in a rhombus shape.

The forming of the lower storage node and the electrode pillar may include forming a mold insulating film on the interlayer insulating film on which the storage node contact is formed, etching the mold insulating film in the region where the lower storage node is to be formed, and on the resultant. The method may include forming a cylindrical lower storage node connected to the storage node contact by etching back after forming the conductive layer, and removing the mold insulating layer.

Before forming the mold insulating layer, the method may include forming an etch stop layer on the interlayer insulating layer.

In the forming of the conductive film, the conductive film may be deposited to fill a space between the cylinders.

The lower storage node and the electrode pillar may be formed of titanium nitride (TiN).

The forming of the cylindrical upper storage node connecting to the electrode pillar may include forming a contact hole for etching the interlayer insulating layer to expose the electrode pillar, and filling the contact hole with a conductive layer to form a contact plug. Forming a mold, forming a mold insulating film on the interlayer insulating film on which the contact plug is formed, etching the mold insulating film to expose a region including the contact plug, and depositing a conductive film on the resultant. And backing up to form an upper storage node connected with the contact plug.

The contact plug may be formed of titanium (Ti) / titanium nitride (TiN).

According to the present invention, by changing the arrangement of storage nodes into a rhombus, it is possible to place the storage nodes at a higher density. In addition, by configuring the storage nodes in multiple layers, it is possible to increase the distance between the storage nodes arranged in the same layer, increase the diameter of the cylinder and reduce the height of the desired cylinder. Therefore, sufficient cell capacitance can be secured without increasing the difficulty of the process.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.

In the case of DRAM having 8F2 structure, two storage nodes are arranged in one active area. Implementing storage nodes in the form of circular cylinders allows for higher density storage nodes by changing the array of storage nodes from square arrays to diamonds. In the present invention, the storage node is configured in a plurality of layers, one storage node (lower storage node) is configured in the form of a cylinder directly above the storage node contact, the other storage node contacts connecting the upper storage node and the storage node contact Only form a plug. When the process of forming the lower storage node is completed, the upper storage node is formed to complete the multilayer storage node.

2 is a diagram illustrating a cell arrangement of a highly integrated semiconductor memory device according to an exemplary embodiment of the present invention, and illustrates an arrangement of storage node contacts.

Referring to FIG. 2, lower cylindrical storage nodes 211 and 212 are disposed in a first column, and only electrode pillars 221, 222, and 223 are disposed in a second column adjacent thereto. As such, when cylinders are arranged on one plane (see FIG. 1), cylinder-shaped storage nodes and electrode pillars are alternately arranged on the same plane, and cylindrical storage nodes are alternately arranged on different planes. In addition, the space between the cylinders can be secured, and the diameter of the cylinder can be increased. Thus, sufficient cell capacitance can be secured without increasing the difficulty of the process.

3 to 9 are cross-sectional views illustrating a method of manufacturing a highly integrated semiconductor memory device having a multilayer storage node according to an exemplary embodiment of the present invention, taken along line AA ′ of FIG. 2.

Referring to FIG. 3, a contact hole is formed by etching the interlayer insulating layer 302 formed on the semiconductor substrate 300, and then filling the contact hole with a conductive material to form storage node contacts 304 and 305. The etching process for forming the contact hole may be performed in a multi-step process, and the storage node contacts 304 and 305 may be formed by depositing a conductive material to a predetermined thickness on the resultant contact hole and then etching back or chemically. It may be formed by performing a mechanical polishing (CMP) process. In order to implement the 8F2 structure, two storage node contacts 304 and 305 are formed in one active region. Although not shown, an isolation layer defining an active region is formed on the semiconductor substrate 300, and substructures such as a transistor and a bit line formed of a gate and a source / drain are formed on the semiconductor substrate 300. Of course.

Referring to FIG. 4, an etch stop layer 306 is formed by depositing, for example, a nitride layer having a thickness of about 500 μm to 600 μm on a resultant product on which the storage node contacts 304 and 305 are formed. The etch stop layer 306 serves as a mask for the lower layer when patterning the mold insulating layer for subsequent cylinder formation. In general, when the mold insulating layer is formed of an oxide layer, the etch stop layer 306 may have an etching selectivity with respect to the oxide layer. A nitride film having

A mold insulating film 308 is formed on the etch stop film 306 by, for example, laminating an oxide film in a single layer or multiple layers. In consideration of the loss caused by the subsequent etching process, the mold insulating film 308 is formed to a thickness of about 13,000 to 15,000 Å.

Next, a photolithography process is performed to etch the mold insulating layer 308 in the region where the storage node is to be formed, and then the etch stop layer 306 on the storage node contacts 304 and 305 is removed to remove the storage node contact 304. 305). At this time, the size of the region where the mold insulating film is etched is different, as shown, the portion where the mold insulating film 308 is widely etched and the narrowly etched portions are alternately formed. A cylindrical lower storage node connected to the storage node contact 304 is formed in a portion where the mold insulating layer 308 is widely etched, and a portion of the mold insulating layer 308 that is narrowly etched is filled with a conductive layer to form a storage node contact ( 305 and an electrode pillar to connect the upper storage node is formed.

Referring to FIG. 5, the conductive layer 310a for the storage node is deposited on the entire surface of the resultant on the semiconductor substrate with a thickness of about 200 to 250 Å. As described above, in the highly integrated memory device, since the height of the cylinder is high and the diameter is small, the conductive layer 310a for the storage node should be formed of a material having excellent step coverage, and such a material is titanium nitride (TiN). In this case, the region where the mold insulating layer 308 is narrowly etched is filled with the conductive layer 310a for the storage node to form an electrode pillar connected to the storage node contact 305.

Next, the storage node conductive layer 310a deposited on the mold insulating layer 308 is removed by an etch back process so that the storage nodes are separated in units of cells.

Referring to FIG. 6, when the mold insulating layer 308 of FIG. 3 remaining between the cylindrical storage nodes is removed by a dip-out process, the cylindrical storage node 310 and the electrode pillar ( Only 311) remains. By removing the mold insulating film, both the inner and outer surfaces of the cylinder can be used as the effective capacitor area, thereby increasing the cell capacitance. In this way, one electrode pillar 311 is formed between the two cylindrical lower storage nodes 310.

Next, a dielectric film 312 is formed on the entire surface of the resultant in which the storage node is formed. The dielectric film 312 may be formed by, for example, an atomic layer deposition (ALD) method using a material widely used as a dielectric film of a capacitor. Next, a plate thickness conductive film 314 is deposited on the dielectric film 312. The plate electrode conductive film 314 may be formed by stacking titanium nitride (TiN) and a doped polysilicon film with a thickness of 500 to 800 kPa and 300 kPa, respectively. Subsequently, the conductive film 314 for the plate electrode in the peripheral circuit region is etched, and then an oxide film having a thickness of about 20,000 mW is deposited on the entire surface to eliminate the step difference between the cell region and the peripheral circuit region. The deposited oxide film is planarized by, for example, a chemical mechanical polishing (CMP) process to form an interlayer insulating film 316.

A photolithography process is performed on the interlayer insulating film 316 to form a contact hole for connecting the conductive film 314 for the plate electrode in the peripheral circuit region with the metal wiring layer. Next, the contact hole is filled with a conductive film such as aluminum (Al) to form a contact 318. This contact 318 is connected to another contact made at the upper storage node and then to the metallization layer.

Referring to FIG. 7, in order to connect the electrode pillars 311 formed between the lower storage nodes with the upper storage node, the interlayer insulating layer 316 and the conductive layer 314 for plate electrodes on the electrode pillars 311 are connected. By etching, the electrode pillars 311 are exposed. At this time, since the conductive film 314 for the plate electrode of the hole sidewall is exposed by etching, in order to insulate it from the other conductive layers, an insulating film 320 such as nitride is formed on the resultant of about 300 to 500 kV. Form to thickness. Next, the insulating layer 320 formed on the electrode pillar 311 is removed, and then, for example, a doped polysilicon layer is deposited to a thickness of about 300 to 500 kV to fill the hole formed on the electrode pillar 311. Next, the contact plug 322 connected to the electrode pillar 311 is formed by removing the polysilicon film formed in the remaining area.

Next, for example, nitride is deposited to a thickness of about 500 to 600 kPa on the resultant in which the contact plug is formed to form an etch stopper 324. The etch stop layer 324 may prevent the lower layers from being etched when the mold insulating layer is etched to form the upper storage node.

Referring to FIG. 8, a mold insulating layer 326 is formed on the etch stop layer 324 to form an upper storage node by, for example, depositing an oxide layer having a thickness of about 9,000 to 10,000 Å. Next, the mold insulating layer 326 is patterned to expose a region including the contact plug 322 by performing a photolithography process, and then a conductive film for an electrode such as titanium nitride (TiN) is formed on the resultant. It deposits in thickness of about 300-350 Pa. Next, the cylindrical upper storage node 328 is formed by etching back and removing the electrode conductive film formed on the mold insulating film 326. The upper storage node 328 is connected to the storage node contact 304 through the contact plug 322 and the electrode pillar 311.

Referring to FIG. 9, the upper storage node 328 is completed by removing the mold insulating layer through a dip-out process. Subsequently, a dielectric film 330 and an upper plate electrode conductive film 332 are formed on the resultant to complete a capacitor having a multilayer cylinder structure. Thereafter, the contact 336 for connecting the interlayer insulating film 334 and the metal wiring layer is performed in the same manner as in the case of the lower storage node.

In the storage node of the cylinder structure, the biggest effect of implementing the cylinder in the upper and lower layers is that the space for forming the cylinder in the lower layer is increased to form a larger diameter cylinder. As the diameter of the cylinder is increased, the area of the dielectric film is increased to allow a margin of cell capacitance, thereby reducing the height of the cylinder. This prevents sticking between cylinders and creates a highly productive capacitor.

For example, when constructing a cylinder in a conventional manner in a design rule of 50 nm, a multilayer cylinder structure, assuming that the thickness of the cylinder wall is 20 nm, the distance between the cylinders is 70 nm, and the outer diameter of the cylinder is 70 nm. By applying, the outer diameter of the cylinder can be increased to 100 nm. This increase in the outer diameter results in an increase in the area of the dielectric film, resulting in an increase in cell capacitance. Therefore, the height of the cylinder can be reduced by that increase. According to the experiment, the height of the cylinder can be reduced by about 16.7% compared to the conventional single cylinder structure under the above conditions.

In the multilayer cylinder structure of the present invention, the upper storage node may be formed of a cylinder having a larger diameter than the lower storage node. It is necessary to form an electrode pillar (311 of FIG. 9) for connecting the upper storage node to the storage node contact in the lower layer, but it is possible to increase the cylinder diameter as much as it is not necessary to form an electrical pillar in the upper layer. In this case, it is possible to increase the outer diameter of the cylinder to 130 nm when maintaining the distance from the neighboring cylinder at 70 nm as in the prior art. Accordingly, the height of the cylinder can be reduced by 54.5% compared with the conventional.

In addition, since the dielectric film 312 and the lower plate electrode conductive film 314 are formed on the surface of the electrode pillar (311 of FIG. 9) formed between the lower storage nodes, the electrode pillar itself serves as a capacitor. That is, since there is an effect of increasing the cell capacitance corresponding to the surface area of the electrode pillar, it becomes a factor that can further lower the height of the cylinder.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

1 is a diagram illustrating an arrangement of cells of a conventional DRAM having an 8F2 structure.

2 is a view showing a cell arrangement of a highly integrated semiconductor memory device according to the present invention.

3 to 9 are cross-sectional views illustrating a method of manufacturing a highly integrated semiconductor memory device having a multilayer storage node according to the present invention.

Claims (12)

Cylindrical lower storage nodes and electrode pillars alternately arranged on the semiconductor substrate so as not to be adjacent to each other; A first dielectric layer formed on a surface of the lower storage node and the electrode pillar; A lower plate electrode formed on the first dielectric layer; An interlayer insulating film formed on the resultant material on which the lower plate electrode is formed to expose the electrode pillar; And And a cylindrical upper storage node formed on the interlayer insulating film so as to be connected to the electrode pillar. The method of claim 1, And the lower storage node is arranged in a rhombus shape. The method of claim 1, And the lower storage node and the upper storage node are made of titanium nitride (TiN). The method of claim 1, And the upper storage node is connected to the electrode pillar through a contact formed in the interlayer insulating layer. Forming a storage node contact on the semiconductor substrate such that two storage nodes are disposed in one active region; Forming cylindrical storage nodes and electrode pillars connected to the storage node contacts, and alternately disposing the storage node and the electrode pillars so that the cylinders do not neighbor each other; Forming a first dielectric layer and a lower plate electrode on surfaces of the storage node and the electrode pillar; Forming an interlayer insulating film covering the resultant; Etching the interlayer insulating film to expose the electrode pillars; And And forming a cylindrical upper storage node on the interlayer insulating layer on the electrode pillar, the cylindrical upper storage node being connected to the electrode pillar. The method of claim 5, And the storage node contacts are arranged in a rhombus shape. The method of claim 5, Forming the lower storage node and the electrode pillar, Forming a mold insulating film on the interlayer insulating film on which the storage node contacts are formed; Etching the mold insulating layer in a region where a lower storage node is to be formed; Forming a cylindrical lower storage node connected to the storage node contact by etching back after forming a conductive film on the resultant, and And removing the mold insulating film. The method of claim 7, wherein Before forming the mold insulating film, And forming an etch stop layer on the interlayer insulating film. The method of claim 7, wherein In the step of forming the conductive film, And depositing a conductive film to fill the space between the cylinders. The method of claim 5, The lower storage node and the electrode pillars are formed of titanium nitride (TiN). The method of claim 5, Forming a cylindrical upper storage node in contact with the electrode pillar, Etching the interlayer insulating film to form a contact hole exposing the electrode pillar; Filling the contact hole with a conductive film to form a contact plug; Forming a mold insulating film on the interlayer insulating film on which the contact plug is formed; Etching the mold insulating film to expose a region including the contact plug, and And depositing a conductive film on the resultant to etch back to form an upper storage node connected to the contact plug. The method of claim 11, The contact plug is a method of manufacturing a highly integrated semiconductor memory device, characterized in that formed of titanium (Ti) / titanium nitride (TiN).

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