CN110634733A

CN110634733A - Method for preparing semiconductor memory capacitor hole

Info

Publication number: CN110634733A
Application number: CN201810654407.4A
Authority: CN
Inventors: 不公告发明人
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2018-06-22
Filing date: 2018-06-22
Publication date: 2019-12-31

Abstract

The invention provides a preparation method of a semiconductor memory capacitor hole, which comprises the following steps: providing a semiconductor substrate, and forming a capacitance supporting sacrificial structure layer, a hard mask consumption layer, a double-pattern integration layer, a first pattern migration layer and a first mask layer; forming a second pattern layer, a first interval sacrificial layer and a first filling mask layer along a first direction; planarizing to the second pattern layer; forming an etching stop layer, a second pattern transfer layer and a second mask layer; forming a fourth pattern layer, a second interval sacrificial layer and a second filling mask layer along the second direction; planarizing to the second spacer sacrificial layer; forming a pattern transfer layer; and etching the capacitor support sacrificial structure layer to form a semiconductor memory capacitor hole. The invention utilizes two directions to respectively form the side wall layers for pattern doubling, improves the definition of characteristic dimension in the device structure, solves the problem of big and small holes, improves the pattern precision by improving the double-pattern integration layer in the etching process, improves the structure layer and improves the yield.

Description

Method for preparing semiconductor memory capacitor hole

Technical Field

The invention belongs to the technical field of semiconductor device manufacturing, and particularly relates to a preparation method of a capacitor hole of a semiconductor memory.

Background

Dynamic Random Access Memory (DRAM) is a semiconductor Memory device commonly used in computers, and is composed of many repetitive Memory cells. Each memory cell typically includes a capacitor and a transistor; the grid electrode of the transistor is connected with the word line, the drain electrode/source electrode of the transistor is connected with the bit line, and the source electrode/drain electrode of the transistor is connected with the capacitor; the voltage signal on the word line can control the transistor to be turned on or off, so that data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor through the bit line for storage.

As the semiconductor industry evolves, the size of integrated circuits continues to decrease, due to a number of factors, including the need for increased portability, computing power, storage capacity, and energy efficiency in modern electronic devices. To facilitate this size reduction, methods of reducing the size of the constituent features of integrated circuits, examples of which include capacitors, electrical contacts, interconnect lines, and other electrical devices, continue to be investigated. The trend to reduce feature sizes is very evident in memory circuits or devices, such as Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM), among others.

There is an increasing demand for ever decreasing feature sizes, and accordingly, for techniques for forming such features, and additionally, the concept of pitch, which is the distance between the same points in two adjacent features, can be used to describe the size of such features. Currently, certain photoresist materials react only to certain wavelengths, one common wavelength range that can be used is the Ultraviolet (UV) range, as many photoresist materials react selectively to certain wavelengths, so the lithography techniques each have a minimum pitch, however, below which a particular lithography technique cannot reliably form features, this minimum pitch is typically determined by the wavelengths of light that can be used with it, so the minimum pitch of the lithography technique can limit feature size reduction. Accordingly, there is a need to reduce the size of integrated circuits and increase the operable density of arrays of electrical devices on computer chips, to provide improved methods of forming smaller features, improved methods for increasing feature density, methods that will produce more efficient arrays, and techniques that will provide more compact arrays without compromising feature resolution.

Therefore, how to provide a method for preparing a capacitor hole of a semiconductor memory is necessary to solve the above problems in the prior art.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a method for fabricating a capacitor hole of a semiconductor memory, which is used to solve the problems of the prior art, such as difficulty in fabricating a scaled semiconductor structure, inaccurate patterning due to non-uniform dimensions, and the existence of holes with a characteristic dimension of a sidewall.

To achieve the above and other related objects, the present invention provides a method for fabricating a capacitor hole structure of a semiconductor memory, comprising the steps of:

1) providing a semiconductor substrate, and sequentially forming a capacitance supporting sacrificial structure layer, a hard mask consumption layer, a double-pattern integration layer, a first pattern transfer layer and a first mask layer on the semiconductor substrate, wherein the first mask layer comprises at least one of an ashable hard mask layer (AHM) and a diamond-like carbon film layer (DLC);

2) forming a first pattern layer arranged along a first direction on the first mask layer, wherein the first pattern layer comprises a plurality of first pattern units arranged in parallel at intervals;

3) transferring the pattern on the first pattern layer to the first pattern transfer layer through the first mask layer to form a second pattern layer, wherein the second pattern layer comprises a plurality of second pattern units which are arranged in parallel at intervals;

4) forming a first spacing sacrificial layer on the top and the side wall of the second pattern unit and the surface of the double-pattern integration layer between the second pattern units, forming a first gap groove on the surface of the first spacing sacrificial layer between the adjacent second pattern units, and forming a first filling mask layer on the surface of the first spacing sacrificial layer, wherein the first filling mask layer covers the first spacing sacrificial layer and fills the first gap groove;

5) removing a first transverse part of the first spacing sacrificial layer positioned on the top of the second pattern unit, the first filling mask layer and a part of the first filling mask layer positioned in the first gap groove, wherein a size limiting unit and a pattern auxiliary unit positioned between the size limiting units are formed between the adjacent second pattern units, a first longitudinal part of the first spacing sacrificial layer positioned on the side wall of the second pattern unit forms the size limiting unit, a second transverse part of the first spacing sacrificial layer positioned on the double-pattern integration layer and the rest of the first filling mask layer positioned on the second transverse part form the pattern auxiliary unit;

6) forming an etching stop layer, a second pattern migration layer and a second mask layer on the structure obtained in the step 5) in sequence;

7) forming a third pattern layer arranged along a second direction on the second mask layer, wherein the third pattern layer comprises a plurality of third pattern units arranged in parallel at intervals, and an intersection angle is formed between the second direction and the first direction;

8) transferring the pattern on the third pattern layer to the second pattern transfer layer through the second mask layer to form a fourth pattern layer, wherein the fourth pattern layer comprises a plurality of fourth pattern units which are arranged in parallel at intervals;

9) forming second spacer sacrificial layers on the tops and the side walls of the four pattern units and the surfaces of the etching stop layers between the fourth pattern units, forming second gap grooves on the surfaces of the second spacer sacrificial layers between the adjacent fourth pattern units, and forming second filling mask layers on the surfaces of the second spacer sacrificial layers, wherein the second filling mask layers cover the second spacer sacrificial layers and fill the second gap grooves;

10) planarizing the structure obtained in the step 9) until the top surface of the second spacer sacrificial layer is exposed, and remaining second filling mask layers between second longitudinal portions of the second spacer sacrificial layer on the sidewalls of the fourth pattern units remain;

11) etching to remove a third transverse part and a second longitudinal part of the second spacing sacrificial layer on the top of the fourth pattern unit so as to expose the etching stop layer and obtain a fifth pattern layer, wherein the fifth pattern layer comprises a plurality of fifth pattern units which are arranged in parallel at intervals, and a fifth pattern unit is formed by a laminated layer formed by the fourth pattern unit on the etching stop layer, a fourth transverse part of the second spacing sacrificial layer on the surface of the etching stop layer and the residual second filling mask layer on the fourth transverse part;

12) selectively etching and removing the etching stop layer and the size limiting unit by taking the fifth pattern unit as a mask so as to transfer the pattern on the fifth pattern layer to the second pattern layer to form a pattern transfer layer on the double-pattern integration layer, wherein the pattern transfer layer comprises a plurality of first pitch multiplication units which are arranged in parallel at intervals along the first direction and a plurality of second pitch multiplication units which are arranged in parallel at intervals along the second direction and connected with the first pitch multiplication units, the first pitch multiplication units are formed by the second pattern unit and the pattern auxiliary unit, and the second pitch multiplication units are formed by transferring the fifth pattern unit; and

13) and transferring the pattern on the pattern transfer layer to the hard mask consumption layer through the double-pattern integration layer to obtain a patterned hard mask consumption layer, and etching the capacitance supporting sacrificial structure layer based on the patterned hard mask consumption layer so as to form a plurality of semiconductor memory capacitor holes uniformly distributed at intervals in the capacitance supporting sacrificial structure layer.

As a preferable embodiment of the present invention, in step 1), the double-pattern integrated layer sequentially includes a first cushion layer, a second cushion layer, a third cushion layer, and a fourth cushion layer from bottom to top.

As a preferable aspect of the present invention, a material of the first pad layer includes any one of silicon oxide and tetraethyl orthosilicate (TEOS), and a thickness of the first pad layer is between 100nm and 500 nm; the second cushion layer is made of any one of amorphous silicon, silicon oxynitride and silicon nitride, and the thickness of the second cushion layer is between 100nm and 800 nm; the third cushion layer is made of any one of silicon oxide and ethyl orthosilicate layers, and the thickness of the third cushion layer is between 100nm and 500 nm; the fourth pad layer is made of any one of amorphous silicon, silicon oxynitride and silicon nitride, and the thickness of the fourth pad layer is 50 nm-200 nm.

As a preferable aspect of the present invention, before the step 13) of transferring the pattern on the pattern transfer layer into the hard mask consumption layer, the step further includes: transferring the graph on the graph transfer layer to the double-graph integration layer, and the specific steps comprise:

13-1) etching the fourth cushion layer by taking the pattern transfer layer as a mask to obtain a first intermediate pattern transfer layer, and reserving the pattern transfer layer left after etching;

13-2) depositing a pattern optimization sacrificial layer on the surface of the structure obtained in the step 13-1), wherein the pattern optimization sacrificial layer fills gaps between the first middle pattern transfer layer and the patterns on the rest pattern transfer layer and covers the rest pattern transfer layer;

13-3) planarizing the pattern optimized sacrificial layer to the remaining pattern transfer layer and removing the remaining pattern transfer layer, wherein the pattern optimized sacrificial layer is converted into a second intermediate pattern transfer layer;

13-4) removing the second intermediate pattern transfer layer, etching the third cushion layer based on the first intermediate pattern transfer layer obtained by etching in the step 13-1) to obtain a third intermediate pattern transfer layer, and adjusting the sizes of the patterns in the first direction and the second direction in the process of etching the third cushion layer; and

13-5) etching the second cushion layer to obtain a fourth intermediate pattern transfer layer, and etching the first cushion layer by using the fourth intermediate pattern transfer layer obtained by etching as a mask to obtain a fifth intermediate pattern transfer layer so as to transfer the pattern on the pattern transfer layer to the first cushion layer.

As a preferable embodiment of the present invention, in step 1), the first pattern transfer layer includes a bottom pattern transfer layer and an upper pattern transfer layer located on the bottom pattern transfer layer, where the bottom pattern transfer layer includes at least one of a silicon oxide layer and a tetraethyl orthosilicate (TEOS) layer, and the upper pattern transfer layer includes a silicon-rich photoresist layer; and in the step 3), transferring the pattern on the first pattern layer to the bottom pattern transfer layer to form the second pattern layer.

As a preferable embodiment of the present invention, step 3) includes: etching the first mask layer to transfer the pattern on the first pattern layer to the first mask layer, wherein the process parameters for etching the first mask layer comprise: the etching gas comprises at least one of O2, AR, N2 and CH4, the etching pressure is between 5mT and 20mT, the source power is between 200W and 600W, and the bias voltage is between 200V and 600V; the step 3) also comprises the following steps: etching the upper pattern transfer layer and the bottom pattern transfer layer to transfer the pattern on the first pattern layer to the bottom pattern transfer layer, wherein the process parameters for etching the upper pattern transfer layer comprise: the etching gas comprises at least one of N2, O2 and HE; the technological parameters for etching the bottom layer pattern transfer layer comprise: the etching gas at least comprises CH4 and CHF3, the ratio of CH4 to CHF3 is 3: 1-1: 1, the etching pressure is 1 mT-10 mT, the source power is 300W-800W, and the bias voltage is 10V-100V.

As a preferable aspect of the present invention, step 4) further includes: and depositing a planarization auxiliary layer on the surface of the first filling mask layer.

As a preferable aspect of the present invention, the planarization auxiliary layer includes at least one of an ashable hard mask layer (AHM) and a diamond-like thin film layer (DLC); the thickness of the planarization auxiliary layer is between 20nm and 100 nm.

As a preferable aspect of the present invention, the step 5) of planarizing the structure obtained in the step 4) to the second pattern layer includes: etching the planarization auxiliary layer, etching the first filling mask layer and etching the first transverse part of the first interval sacrificial layer at the top of the second pattern unit, wherein the process parameters for etching the planarization auxiliary layer comprise: the etching gas comprises at least one of O2, AR, N2 and CH4, the etching pressure is between 5mT and 20mT, the source power is between 200W and 600W, and the bias voltage is between 200V and 600V; the technological parameters for etching the first filling mask layer comprise: the etching gas at least comprises CH4 and CHF3, the proportion of CH4 to CHF3 is 3: 1-1: 1, the etching pressure is 1 mT-10 mT, the source power is 300W-800W, and the bias voltage is 10V-100V; the process parameters for etching the first spacing sacrificial layer on the top of the second pattern unit comprise: the etching gas comprises at least one of CHF3, CH4 and SF6, the etching pressure is between 5mT and 30mT, the source power is between 300W and 600W, and the bias voltage is between 50V and 250V.

As a preferable embodiment of the present invention, the step 6) further includes: forming a stress relieving layer between the etching stop layer and the second pattern migration layer; and 11) etching the stress relieving layer simultaneously in the process of etching and removing the second longitudinal part of the second interval sacrificial layer.

As a preferable aspect of the present invention, step 8) includes: etching the second mask layer to transfer the pattern of the third pattern layer to the second mask layer, wherein the process parameters for etching the second mask layer comprise: the etching gas comprises at least one of O2, AR, N2 and CH4, the etching pressure is between 5mT and 20mT, the source power is between 200W and 600W, and the bias voltage is between 200V and 600V; step 8) also includes: etching the second pattern migration layer to transfer the pattern of the third pattern layer to the second pattern migration layer, wherein the process parameters for etching the second pattern migration layer include: the etching gas comprises at least one of N2, O2 and HE.

As a preferable aspect of the present invention, the step 10) of planarizing the structure obtained in the step 9) to the second spacer sacrificial layer includes: and etching the second filling mask layer, wherein the technological parameters for etching the second filling mask layer comprise: the etching gas comprises at least one of O2, AR, N2 and CH4, the etching pressure is between 5mT and 20mT, the source power is between 200W and 600W, and the bias voltage is between 200V and 600V.

As a preferable aspect of the present invention, in step 11), the process parameters for etching and removing the third lateral portion and the second longitudinal portion of the second spacer sacrificial layer include: the etching gas comprises at least one of O2, CH4 and CHF3, the etching pressure is between 1mT and 10mT, the source power is between 300W and 800W, and the bias voltage is between 10V and 100V.

In a preferred embodiment of the present invention, the pattern transfer layer is formed to include at least one of a checkered pattern transfer layer and a diamond-shaped pattern transfer layer.

As a preferable scheme of the invention, in step 1), the capacitance supporting sacrificial structure layer includes an etching barrier layer on the semiconductor substrate, and at least one dielectric sacrificial layer and at least one supporting layer on the etching barrier layer; step 13) comprises: and etching the supporting layer, the medium sacrificial layer and the etching barrier layer based on the patterned hard mask consumption layer, and removing the patterned hard mask consumption layer left after etching so as to etch and form a plurality of semiconductor memory capacitor holes which are uniformly distributed at intervals and positioned in the capacitor supporting sacrificial structure layer on the semiconductor substrate.

As a preferred scheme of the invention, the support layer, the dielectric sacrificial layer and the etching barrier layer are etched by adopting a pulse radio frequency etching mode, wherein an etching period of the pulse radio frequency etching comprises one pulse on and one pulse off, the etching is carried out when the pulse is on, by-products are discharged when the pulse is off, and the pulse on time accounts for 70% -90% of the etching period of the pulse radio frequency etching.

As a preferred embodiment of the present invention, the dielectric layer includes a first dielectric sacrificial layer, a second dielectric sacrificial layer, and a third dielectric sacrificial layer, the support layer includes a first support layer and a second support layer, and the first dielectric sacrificial layer, the second dielectric sacrificial layer, the first support layer, the third dielectric sacrificial layer, and the second support layer are sequentially stacked from bottom to top.

As a preferred scheme of the invention, the etching barrier layer comprises a silicon nitride layer, and the thickness of the etching barrier layer is between 10nm and 80 nm; the material of the first dielectric layer comprises at least one of phosphorus-doped silicon oxide (PSG), boron-phosphorus-doped silicon oxide (BPSG) and fluorine-doped silicon oxide glass (FSG), and the thickness of the first dielectric layer is between 100nm and 600 nm; the hardness of the second dielectric layer is greater than that of the first dielectric layer, the material of the second dielectric layer comprises TEOS, and the thickness of the second dielectric layer is between 300nm and 1000 nm; the third dielectric layer is made of at least one of silicon oxide and TEOS, and the thickness of the third dielectric layer is 300 nm-1000 nm; the material of the first support layer comprises silicon nitride, and the thickness of the first support layer is between 10nm and 80 nm; the material of the second support layer comprises silicon nitride, and the thickness of the second support layer is between 50nm and 200 nm.

In a preferred embodiment of the present invention, in the step 6), the second mask layer includes at least one of an ashable hard mask layer (AHM) and a diamond-like thin film layer (DLC); in step 9), the second fill mask layer comprises at least one of an ashable hard mask layer (AHM) and a diamond-like carbon film layer (DLC).

As described above, the method for manufacturing a capacitor hole of a semiconductor memory according to the present invention has the following advantageous effects:

the invention relates to a semiconductor structure layer based on space multiplication, which utilizes two directions to respectively form side wall layers (spacers) for pattern doubling in the preparation of the semiconductor structure layer based on the space multiplication, can achieve pattern micro-shrinkage in a process of 30nm and below based on the space doubling technology, further achieves good uniformity of space doubling patterns by controlling the sizes of two directions in the preparation process, further improves the definition of characteristic sizes in a device structure, solves the problem of large and small holes, corrects the patterns in the preparation process by improving a double-pattern integration layer in the etching process, improves the pattern accuracy, and improves the structure layer, thereby achieving better selection ratio, improving the size defect of a capacitor and improving the yield.

Drawings

FIG. 1 is a process flow diagram illustrating a process for fabricating a capacitor hole of a memory according to the present invention.

FIG. 2 is a schematic diagram of a semiconductor substrate for forming a capacitor hole of a memory device according to the present invention.

FIG. 3 is a schematic structural diagram of a hard mask consumption layer, a first pattern migration layer and a first mask layer formed on a semiconductor substrate in the fabrication of a memory capacitor hole according to the present invention.

Fig. 4 is a schematic structural diagram of a dual pattern integration layer formed on the basis of fig. 3.

FIG. 5 is a schematic diagram of a first pattern layer formed in the fabrication of a capacitor hole of a memory according to the present invention.

Fig. 6 is a top view of fig. 5, and fig. 5 is a cross-sectional view taken at a position a-a' in fig. 6.

FIG. 7 is a schematic diagram illustrating a second pattern layer formed in the fabrication of a capacitor hole of a memory according to the present invention.

FIG. 8 is a schematic diagram of a structure of forming a first spacer sacrificial layer in the fabrication of a capacitor hole of a memory according to the present invention.

FIG. 9 is a schematic diagram of a first fill mask layer formed during the fabrication of a capacitor hole of a memory device according to the present invention.

FIG. 10 is a schematic diagram illustrating a planarization assistant layer formed in the fabrication of a capacitor hole of a memory according to the present invention.

FIG. 11 is a schematic view showing a structure of a planarized second pattern layer in the preparation of a capacitor hole of a memory according to the present invention.

FIG. 12 is a schematic structural diagram of an etching stop layer, a stress relieving layer, a second pattern migration layer and a second mask layer formed in the preparation of the memory capacitor hole according to the present invention.

FIG. 13 is a schematic view of a first direction structure of a third pattern layer formed in the fabrication of a capacitor hole of a memory according to the present invention.

FIG. 14 is a structural diagram illustrating a second direction for forming a third pattern layer in the fabrication of a capacitor hole of a memory according to the present invention.

FIG. 15 is a top view of a third pattern layer formed in the formation of a capacitor hole of a memory device according to the present invention, wherein FIG. 13 is a cross-sectional view taken along the line A-A 'in FIG. 15, and FIG. 14 is a cross-sectional view taken along the line B-B' in FIG. 15.

FIG. 16 is a structural diagram illustrating a second direction for forming a fourth pattern layer in the fabrication of a capacitor hole of a memory according to the present invention.

FIG. 17 is a schematic view of a first direction structure of a fourth pattern layer formed in the fabrication of a capacitor hole of a memory according to the present invention.

FIG. 18 is a top view of a fourth pattern layer formed in the formation of a capacitor hole of a memory device according to the present invention, wherein FIG. 16 is a cross-sectional view taken along the direction B-B 'in FIG. 18, and FIG. 17 is a cross-sectional view taken along the direction A-A' in FIG. 18.

FIG. 19 is a schematic diagram of a second spacer sacrificial layer formed in the fabrication of a capacitor hole of a memory device according to the present invention.

FIG. 20 is a structural diagram illustrating a second direction of forming a second filling mask layer in the fabrication of a capacitor hole of a memory device according to the present invention.

FIG. 21 is a schematic view of a first direction structure of a second filling mask layer formed in the fabrication of a capacitor hole of a memory device according to the present invention.

FIG. 22 is a top view of a second filled mask layer formed during the formation of a capacitor hole in a memory device of the present invention, wherein FIG. 20 is a cross-sectional view taken along the line B-B 'in FIG. 22, and FIG. 21 is a cross-sectional view taken along the line A-A' in FIG. 22.

FIG. 23 is a schematic view of the structure of the planarized to second spacer sacrificial layer in the fabrication of the capacitor hole of the memory device of the present invention.

FIG. 24 is a schematic diagram illustrating a fifth patterning layer formed in the fabrication of a capacitor hole of a memory device according to the present invention.

FIG. 25 is a structural diagram of a second direction of a pattern transfer layer for forming a relief layer in the fabrication of a capacitor hole of a memory according to the present invention.

FIG. 26 is a schematic view of a first direction structure of a pattern transfer layer for forming a relieving layer in the fabrication of a capacitor hole of a memory according to the present invention.

FIG. 27 is a top view of a patterned transfer layer for forming a relief layer in the formation of a capacitor hole of a memory device according to the present invention, wherein FIG. 25 is a cross-sectional view taken along the line B-B 'in FIG. 27, and FIG. 26 is a cross-sectional view taken along the line A-A' in FIG. 27.

FIG. 28 is a schematic diagram showing a second directional structure of a mesh pattern transfer layer formed in the formation of a capacitor hole of a memory device according to the present invention.

FIG. 29 is a schematic view of a first direction structure of a net-shaped pattern transfer layer formed in the formation of a capacitor hole of a memory according to the present invention.

FIG. 30 is a top view of a transfer layer formed in a mesh pattern in the formation of a memory capacitor hole according to the present invention, wherein FIG. 28 is a cross-sectional view taken along the direction B-B 'in FIG. 30, and FIG. 29 is a cross-sectional view taken along the direction A-A' in FIG. 30.

FIG. 31 is a schematic view of a second directional structure of a first intermediate pattern transfer layer formed in the formation of a capacitor hole of a memory device according to the present invention.

FIG. 32 is a schematic view showing a first directional structure of a first intermediate pattern transfer layer formed in the formation of a capacitor hole of a memory according to the present invention.

FIG. 33 is a schematic diagram of a structure of a patterned optimized sacrificial layer in the fabrication of a capacitor hole of a memory device according to the present invention.

FIG. 34 is a schematic view showing a structure of a second intermediate pattern transfer layer formed by planarization in the fabrication of a capacitor hole of a memory according to the present invention.

FIG. 35 is a schematic structural diagram illustrating the removal of the remaining mesh pattern transfer layer in the fabrication of a memory capacitor hole according to the present invention.

FIG. 36 is a schematic diagram showing a third intermediate pattern transfer layer formed in the formation of a capacitor hole of a memory according to the present invention.

FIG. 37 is a structural diagram illustrating a second direction of forming a fourth intermediate pattern transfer layer for memory capacitor hole fabrication according to the present invention.

FIG. 38 is a schematic view showing a first directional structure of a fourth intermediate pattern transfer layer formed in the formation of a capacitor hole of a memory according to the present invention.

FIG. 39 is a top view of a fourth intermediate pattern-transfer layer formed in the formation of a memory capacitor hole according to the present invention, wherein FIG. 37 is a cross-sectional view taken along the direction B-B 'in FIG. 39, and FIG. 38 is a cross-sectional view taken along the direction A-A' in FIG. 39.

FIG. 40 is a second schematic structural view illustrating formation of a fifth intermediate pattern transfer layer in the formation of a capacitor hole of a memory device according to the present invention.

FIG. 41 is a schematic view showing a first direction structure of a fifth intermediate pattern transfer layer formed in the formation of a capacitor hole of a memory according to the present invention.

FIG. 42 is a top view of a fifth intermediate pattern-transfer layer formed in the formation of a capacitor hole of a memory device according to the present invention, wherein FIG. 40 is a cross-sectional view taken along the line B-B 'in FIG. 42, and FIG. 41 is a cross-sectional view taken along the line A-A' in FIG. 42.

FIG. 43 is a structural diagram illustrating a second direction of forming a patterned hard mask consumption layer for memory capacitor hole preparation according to the present invention.

FIG. 44 is a schematic view showing a first direction structure of a patterned hard mask consumption layer formed in the fabrication of a memory capacitor hole according to the present invention.

FIG. 45 is a top view of a patterned hard mask sacrificial layer formed in the fabrication of a memory capacitor hole of the present invention, wherein FIG. 43 is a cross-sectional view taken along the line B-B 'in FIG. 45, and FIG. 44 is a cross-sectional view taken along the line A-A' in FIG. 45.

FIG. 46 is a diagram illustrating the formation of memory capacitor holes by etching a capacitor supporting sacrificial layer for the preparation of memory capacitor holes according to the present invention.

FIG. 47 is a schematic representation of the removal of the remaining patterned hardmask sacrificial layer in the fabrication of a memory capacitor hole of the present invention.

FIG. 48 is a top view of a memory capacitor hole formed in the fabrication of a memory capacitor hole according to the present invention, wherein FIG. 47 is a cross-sectional view taken along the line A-A' of FIG. 48.

Description of the element reference numerals

100 semiconductor substrate

101 hard mask sacrificial layer

102 double pattern integration layer

102a first pad layer

102b second pad layer

102c third pad layer

102d fourth pad layer

103 first pattern migration layer

103a bottom pattern transfer layer

103b upper pattern transfer layer

104 first mask layer

105 first pattern layer

105a first pattern unit

106 second pattern layer

106a second pattern unit

107 first spacer sacrificial layer

107a first clearance groove

107b first transverse portion

107c first longitudinal portion

107d second transverse portion

108 first fill mask layer

109 planarization auxiliary layer

110 size limiting unit

111 pattern auxiliary unit

112 etch stop layer

113 stress relief layer

114 second pattern migration layer

115 second mask layer

116 third pattern layer

116a third pattern unit

117 fourth pattern layer

117a fourth pattern unit

118 second spacer sacrificial layer

118a second clearance groove

118b third transverse portion

118c second longitudinal portion

118d fourth transverse portion

119 second fill mask layer

120 fifth pattern layer

120a fifth Pattern Unit

121 relief layer pattern transfer layer

121a relieving layer pattern transfer unit

122 pattern transfer layer

122a first pitch multiplication unit

122b second pitch multiplying unit

123 first intermediate pattern transfer layer

123a first direction first intermediate pattern transfer layer unit

123b second direction first intermediate pattern transfer layer unit

124 pattern optimized sacrificial layer

125 second intermediate pattern transfer layer

125b second direction second intermediate pattern transfer layer unit

126 third intermediate pattern transfer layer

126b second direction third intermediate pattern transfer layer unit

127 fourth intermediate pattern-transfer layer

127a first direction fourth intermediate Pattern transfer layer Unit

127b second-direction fourth intermediate Pattern transfer layer Unit

128 fifth intermediate pattern transfer layer

128a first direction fifth intermediate Pattern transfer layer Unit

128b second direction fifth intermediate Pattern transfer layer Unit

129 patterned hard mask sacrificial layer

129a polysilicon unit patterned in first direction

129b polysilicon cell patterned in second direction

300 capacitor supporting sacrificial structure layer

301 etch stop layer

302 first dielectric sacrificial layer

303 second dielectric sacrificial layer

304 first support layer

305 third dielectric sacrificial layer

306 second support layer

307 semiconductor device layer

307a semiconductor memory capacitor hole

308 first pattern mask replication layer

S1-S13 steps 1) -13)

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1 to 48. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

As shown in fig. 1 to 48, the present invention provides a method for preparing a capacitor hole of a semiconductor memory, comprising the following steps:

first, as shown in S1 of fig. 1 and fig. 2 to 4, step 1) is performed to provide a semiconductor substrate 100, and a capacitive supporting sacrificial layer 300, a hard mask consumption layer 101, a dual pattern integration layer 102, a first pattern migration layer 103 and a first mask layer 104 are sequentially formed on the semiconductor substrate 100, wherein the first mask layer 104 includes at least one of an ashable hard mask layer (AHM) and a diamond-like thin film layer (DLC).

Specifically, the present invention provides a step of forming a semiconductor memory capacitor hole based on a pitch multiplication technique, wherein a semiconductor substrate 100 and a patterned layer (patterned hard mask consumption layer 129) formed by patterning the hard mask consumption layer 101 based on the pitch multiplication technique are formed in the preparation process, the pitch multiplication technique of the present invention is a technique for achieving the micro-shrinkage of a capacitor pattern and the formation of a deep hole by the pitch multiplication technique in a process of 30nm or less, wherein the semiconductor substrate 100 may be a single-layer semiconductor material layer, such as a silicon material layer, or a laminated material layer formed by stacking multiple material layers, for example, a material layer constituting a certain semiconductor device structure, in addition, the patterned layer formed by patterning the hard mask consumption layer 101 may be used as a semiconductor mask layer, the semiconductor substrate 100 may be continuously etched based on the patterned hard mask consumption layer, to transfer a pattern onto the semiconductor substrate 100 to obtain a desired structure, such as a capacitor with a size of 30nm or less, wherein the hard mask consumption layer 101 may be selected from a polysilicon layer. In addition, for the concept of "pitch," which is the distance between identical points in two adjacent features, the feature size of a semiconductor can be described, wherein the pitch is multiplied by the number of pitches at a fixed interval.

As an example, as shown in fig. 4, in step 1), the dual pattern integration layer 102 includes a first pad layer 102a, a second pad layer 102b, a third pad layer 102c, and a fourth pad layer 102d in sequence from bottom to top.

Specifically, the present invention further forms a dual pattern integration layer 102 before forming the first pattern transfer layer 103, for performing pattern modification during the capacitor hole preparation process to obtain a more precise pattern transfer, and in addition, the dual pattern integration layer 102 in this example includes a structure of four pad layers, and compared with other structures such as two pad layers, the feature size of the pattern, such as the CD in the second direction, can be modified on the bottom pad layer (such as a-si/Oxide).

As an example, the material of the first pad layer 102a includes any one of silicon oxide and tetraethyl orthosilicate (TEOS), and can be used as a hard mask, and the thickness of the first pad layer 102a is between 100nm and 500 nm; the material of the second pad layer 102b includes any one of Amorphous silicon (a-Si), silicon oxynitride (silicon) and silicon Nitride (Nitride), and may be used as a hard mask, and the thickness of the second pad layer 102b is between 100nm and 800 nm; the third pad layer 102c is made of any one of silicon oxide and tetraethyl orthosilicate (TEOS), and can be used as a mask layer, and the thickness of the third pad layer 102c is between 100nm and 500 nm; the material of the fourth pad layer 102d includes any one of amorphous silicon, silicon oxynitride and silicon nitride, and may be used as an etching stop layer, and the thickness of the fourth pad layer 102d is between 50nm and 200 nm. In addition, the hard mask sacrificial layer 101 is formed to have a thickness of 300nm to 1000nm, for example, using a Chemical Vapor Deposition (CVD) process.

As an example, in step 1), the first pattern transfer layer 103 includes a bottom pattern transfer layer 103a and an upper pattern transfer layer 103b on the bottom pattern transfer layer 103 a.

As an example, the lower pattern transfer layer 103a includes at least one of a silicon oxide layer and a tetraethyl orthosilicate (TEOS) layer as an oxide transition layer, and the upper pattern transfer layer 103b (MLR) includes a silicon-rich photoresist layer.

Specifically, the thickness of the bottom layer pattern transfer layer 103a is between 50nm and 100nm, the thickness of the upper layer pattern transfer layer (MLR) 103b can be used as a mask layer, and the thickness is between 20nm and 150 nm.

Specifically, in step 1), the first mask layer 104 includes at least one of an ashable hard mask layer (AHM) and a diamond-like carbon thin film layer (DLC), and the thickness of the first mask layer 104 is between 50nm and 200 nm. Specifically, in this example, AHM (ashable hard mask) or DLC (diamond like Carbon) is used to replace the conventional Carbon as a mask layer, where AHM or DLC has a better selectivity than Carbon and is easier to be removed by O2 plasma, and Profile is more desirable, and certainly, in other examples, it may also be selected as Carbon, and in addition, the first mask layer 104 may also be a laminated structure composed of an ashable hard mask layer (AHM) and a diamond-like thin film layer (DLC), and preferably, the ashable hard mask layer (AHM) is located on the diamond-like thin film layer (DLC), thereby further improving stability in the device manufacturing process.

Next, as shown in S2 in fig. 1 and fig. 5 to 6, step 2) is performed to form a first pattern layer 105 arranged along a first direction on the first mask layer 104, where the first pattern layer 105 includes a plurality of first pattern units 105a arranged in parallel at intervals.

Specifically, the present invention is based on the pitch multiplication technique, and performs etching in at least two directions, for example, a first direction and a second direction are defined in a plane parallel to the semiconductor substrate 100, a certain degree of etching is performed in one direction, then deposition is performed on the etched structure layer, and the deposited structure and the previously formed material layer are etched in the other direction, where the two directions may be the first direction and the second direction defined in the present example, and may be perpendicular, or may be at another intersecting angle, such as 60 °. In addition, the first pattern layer 105 may be formed by a process of first coating a photoresist layer (PR) and then performing exposure and development, but may be formed in other manners known to those skilled in the art. Preferably, the first pattern units 105a are preferably arranged in parallel at equal intervals and in equal size. Of course, the setting can be selected according to actual requirements.

Next, as shown in S3 of fig. 1 and fig. 7, step 3) is performed to transfer the pattern on the first pattern layer 105 to the first pattern transfer layer 103 through the first mask layer 104 to form a second pattern layer 106, where the second pattern layer 106 includes a plurality of second pattern units 106a arranged in parallel and at intervals.

Specifically, in this step, the pattern formed in the first direction is transferred to the first pattern transfer layer 103, so as to form a second pattern layer 106, where the second pattern layer 106 is also the first pattern transfer layer after patterning, where the second pattern layer 106 duplicates the morphology of the first pattern layer 105, and in addition, the pattern transfer process includes a step of etching the first mask layer 104, where the step of etching the first mask layer 104 preferably uses an ICP etching machine, and the etching process parameters include: the etching gas comprises at least one of O2, AR, N2 and CH4, preferably selected from the group consisting of O2, AR, N2 and CH4, the etching pressure is 5 mT-20 mT, the source power is 200W-600W, and the bias voltage is 200V-600V.

As an example, as shown in fig. 7, when the first pattern transfer layer 103 includes a lower pattern transfer layer 103a and an upper pattern transfer layer 103b on the lower pattern transfer layer 103a, then in step 3), the pattern on the first pattern layer 105 is transferred to the lower pattern transfer layer 103a to form the second pattern layer 106, and in addition, it is preferable that the lower pattern transfer layer 103a includes at least one of a silicon oxide layer and a Tetraethylorthosilicate (TEOS) layer, and the upper pattern transfer layer 103b includes a silicon-rich photoresist layer.

As an example, when the first pattern transfer layer 103 includes a bottom pattern transfer layer 103a and an upper pattern transfer layer 103b, the step 3) further includes: etching the upper pattern transfer layer 103b and the bottom pattern transfer layer 103a to transfer the pattern on the first pattern layer 105 to the bottom pattern transfer layer 103a, wherein the process parameters for etching the upper pattern transfer layer 103b include: the etching gas comprises at least one of N2, O2 and HE; the process parameters for etching the bottom pattern transfer layer 103a include: the etching gas at least comprises CH4 and CHF3, and can also comprise O2, the etching gas preferably comprises O2, CH4 and CHF3, the ratio of CH4 to CHF3 is 3: 1-1: 1, the etching pressure is 1 mT-10 mT, the source power is 300W-800W, and the bias voltage is 10V-100V.

Next, as shown in S4 of fig. 1 and fig. 8 to 10, step 4) is performed to form a first spacing sacrificial layer 107 on the top and the sidewalls of the second pattern units 106a and on the surface of the dual pattern integration layer 102 between the second pattern units 106a, form a first spacing groove 107a on the surface of the first spacing sacrificial layer 107 between adjacent second pattern units 106a, and form a first filling mask layer 108 on the surface of the first spacing sacrificial layer 107, where the first filling mask layer 108 covers the first spacing sacrificial layer 107 and fills the first spacing groove 107a formed by the first spacing sacrificial layer 107.

Specifically, in this step, a continuous first Spacer sacrificial layer 107 is formed to define a subsequent feature size, where the first Spacer sacrificial layer 107 includes a first lateral portion 107b formed on the top of the second pattern unit 106, a first longitudinal portion 107c located on the sidewall of the second pattern unit 106, and a second lateral portion 107d located on the dual pattern integration layer 102, in the present invention, the first longitudinal portion 107c is subsequently etched away to be used as a feature size CD of the device, because the Nitride sidewall (the first longitudinal portion 107c) is up-side of the Spacer length, the thickness is consistent, and thus the CD size is consistent, thereby solving the problem that in the sidewall process in the prior art, the structures on both sides of the deposited sidewall form different CDs, that is, holes with odd-even sizes of the Spacer CD.

In addition, the thickness of the first spacer sacrificial layer 107 is between 10nm and 80nm, and in this example, the thickness of the first spacer sacrificial layer 107 (sidewall Nitride) determines the CD size in the first direction (e.g., X direction). In addition, a layer of the first filling mask layer 108 is deposited on the surface of the second spacer sacrificial layer 107, the thickness of the first filling mask layer 108 is between 20nm and 100nm, the material of the first filling mask layer 108 may include at least one of silicon oxide and TEOS, a part of the first filling mask layer 108 serves as a mask layer for subsequent etching, and preferably, the first filling mask layer 108 fills the first gap 107a, so that the etching precision is ensured, and the uniformity of the size of the capacitor hole is further improved.

As an example, as shown in fig. 10, step 4) further includes: depositing a planarization auxiliary layer 109 on the surface of the first fill mask layer 108, wherein the deposition of the planarization auxiliary layer 109 is used for optimizing the planarization effect of the subsequent step 5).

The planarization auxiliary layer 109 may include at least one of an ashable hard mask layer (AHM) and a diamond-like carbon thin film layer (DLC), and may be either one of them or a stacked structure layer composed of them. As an example, the planarization auxiliary layer 109 has a thickness of between 20nm and 100 nm.

Next, as shown in S5 of fig. 1 and fig. 11, step 5) is performed to remove the first lateral portion 107b of the first spacing sacrificial layer 107, the first filling mask layer 108 and a portion of the first filling mask layer 108 located in the first gap groove 107a, which are located on top of the second pattern unit 106a, from the structure obtained in the planarization step 4) to the second pattern layer 106, wherein a dimension defining unit 110 and a pattern auxiliary unit 111 located between the dimension defining units 110 are formed between adjacent second pattern units 106a, wherein the first longitudinal portion 107c of the first spacing sacrificial layer 107 located on the sidewall of the second pattern unit 106a forms the dimension defining unit 110, and the second lateral portion 107d of the first spacing sacrificial layer 107 and the remaining first filling mask layer 108a on the second lateral portion 107d on the surface of the double pattern integration layer 102 form the pattern auxiliary unit 110 111;

specifically, through the process of this step, a filler is formed between the second pattern units 106a on the second pattern layer 106, and the filler includes the U-shaped second spacer sacrificial layer remaining after planarization and a portion of the first filling mask layer filled between the U-shaped openings, that is, the filler is defined as a dimension defining unit 110 and a pattern auxiliary unit 111, where the dimension defining unit 110 is used to define a CD of a pattern, and is removed in a subsequent process, and the second pattern units 106a and the pattern auxiliary unit 111 therebetween serve as mask pattern structures for subsequent first-direction pattern etching.

As an example, in step 5), when the planarization auxiliary layer 109 is present, planarizing the structure obtained in step 4) to the second pattern layer 106 includes: etching the planarization auxiliary layer 109, etching the first filling mask layer 108, and etching the first lateral portion 107b of the first spacing sacrificial layer 107 on the top of the second pattern unit 106a, preferably using an ICP etching machine, wherein the process parameters for etching the planarization auxiliary layer 109 include: the etching gas comprises at least one of O2, AR, N2 and CH4, preferably comprises the four etching gases, the etching pressure is between 5mT and 20mT, the source power is between 200W and 600W, and the bias voltage is between 200V and 600V; the process parameters for etching the first fill mask layer 108 include: the etching gas at least comprises CH4 and CHF3, and can also comprise O2, preferably comprises three etching gases of O2, CH4 and CHF3, the proportion of CH4 to CHF3 is 3: 1-1: 1, the etching pressure is 1 mT-10 mT, the source power is 300W-800W, and the bias voltage is 10V-100V; the process parameters for etching the first spacer sacrificial layer 107b on top of the second pattern unit include: the etching gas comprises at least one of CHF3, CH4 and SF6, preferably comprises the three etching gases, the etching pressure is between 5mT and 30mT, the source power is between 300W and 600W, and the bias voltage is between 50V and 250V, so that a pattern with better surface planarization effect is finally achieved.

Then, as shown in S6 in fig. 1 and fig. 12, performing step 6), sequentially forming an etching stop layer 112, a second pattern transition layer 114, and a second mask layer 115 on the structure obtained in step 5);

as an example, step 6) further includes: a stress relief layer 113 is formed between the etch stop layer 112 and the second pattern migration layer 114.

In step 6), the second mask layer 115 may include at least one of an ashable hard mask layer (AHM) and a diamond-like carbon thin film layer (DLC), or may have a stacked structure of both layers.

Specifically, the material layer is deposited to be used as a material layer for subsequent pattern etching in the second direction, an etching stop layer 112 is deposited first to be used as an etching stop layer for subsequent etching, the material of the etching stop layer comprises silicon nitride, the thickness of the silicon nitride is 10nm to 80nm, in a preferred embodiment, the stress relieving layer 113 for relieving the stress of the etching stop layer 112 is formed on the etching stop layer 112, and the material of the stress relieving layer 113 comprises at least one of silicon oxide and TEOS, the thickness of the stress relieving layer is 50nm to 200 nm. In addition, the material of the second pattern Migration Layer (MLR) 114 is preferably a silicon-rich photoresist layer with a thickness of 20nm to 150nm, and the second mask layer 115 may be ahm (inert hard mask) or dlc (diamond like Carbon) or Carbon with a thickness of 50nm to 200 nm.

Next, as shown in S7 in fig. 1 and fig. 13 to 15, performing step 7), forming a third pattern layer 116 arranged along a second direction on the second mask layer 115, where the third pattern layer 116 includes a plurality of third pattern units 116a arranged in parallel at intervals, and an intersection angle is formed between the second direction and the first direction;

specifically, in the present example, the pattern structure is defined in another direction, and the first pattern layer 116 may be obtained by applying a photoresist layer (PR) and then performing exposure and development, but may be obtained by other methods known to those skilled in the art. Preferably, the first pattern units 116a are preferably arranged in parallel at equal intervals and in equal size. Of course, the setting can be selected according to actual requirements. In addition, the second direction is selected according to actual requirements, and the second direction may be perpendicular to the first direction, and may be an intersecting angle, such as 60 °.

Next, as shown in S8 in fig. 1 and fig. 16 to 18, performing step 8), transferring the pattern on the third pattern layer 116 to the second pattern transferring layer 114 through the second mask layer 115 to form a fourth pattern layer 117, where the fourth pattern layer 117 includes a plurality of fourth pattern units 117a arranged in parallel at intervals;

as an example, step 8) comprises: etching the second mask layer 115 to transfer the pattern of the third pattern layer 116 to the second mask layer 115, wherein the process parameters for etching the second mask layer 115 include: the etching gas comprises at least one of O2, AR, N2 and CH4, the etching pressure is between 5mT and 20mT, the source power is between 200W and 600W, the bias voltage is between 200V and 600V, and preferably, the second mask layer 115 comprises at least one of an ashable hard mask layer (AHM) and a diamond-like carbon film layer (DLC).

Specifically, in this step, the pattern formed in the second direction is transferred onto the second pattern transfer layer 114, so as to form a fourth pattern layer 117, where the fourth pattern layer 117 replicates the morphology of the third pattern layer 116, and in addition, the pattern transfer process includes a step of etching the first mask layer 104, where etching the second mask layer 115 preferably uses an ICP etching machine, and the etching process parameters include: the etching gas comprises at least one of O2, AR, N2 and CH4, preferably selected from the group consisting of the above etching gases, the etching pressure is 5 mT-20 mT, the source power is 200W-600W, and the bias voltage is 200V-600V. Step 8) also includes: etching the second pattern migration layer 114 to transfer the pattern of the third pattern layer 116 to the second pattern migration layer 114 to form a fourth pattern layer 117, wherein the process parameters for etching the second pattern migration layer include: the etching gas comprises at least one of N2, O2 and HE.

Next, as shown in S9 in fig. 1 and fig. 19 to 22, step 9) is performed to form a second spacer sacrificial layer 118 on the top and sidewalls of the four pattern units 117a and on the surface of the etch stop layer 112 between the fourth pattern units 117a, form a second gap trench 118a on the surface of the second spacer sacrificial layer 118 between adjacent fourth pattern units 117a, form a second filling mask layer 119 on the surface of the second spacer sacrificial layer 118, and form the second gap trench 118a by covering the second spacer sacrificial layer 118 with the second filling mask layer 119 and filling the second spacer sacrificial layer 118 with the second filling mask layer 119.

As an example, in step 9), the second fill mask layer 119 comprises at least one of an ashable hard mask layer (AHM) and a diamond-like thin film layer (DLC), and the thickness of the second fill mask layer 119 is between 50nm and 200 nm.

Specifically, a continuous second Spacer sacrificial layer 118 is formed in this step to define the subsequent feature size, where the second Spacer sacrificial layer 118 includes a third lateral portion 118b formed on the top of the fourth pattern unit 117a, a second longitudinal portion 118c on the sidewall of the fourth pattern unit 117a, and a fourth lateral portion 118d on the etch stop layer 112 (on the stress relieving layer 113 when the stress relieving layer 113 is present, as shown in fig. 19), in the present invention, the second longitudinal portion 118c is subsequently etched away as the feature size CD of the device, since the second longitudinal portions 118c are all Spacer-long and have uniform thickness, so that the CD size is uniform, and in addition, the thickness of the deposited second Spacer sacrificial layer 118 is between 10nm and 80nm, in this example, the thickness of the second Spacer sacrificial layer 118 (at least one of sidewall silicon oxide or TEOS) determines the second direction (e.g., Y direction) CD size. In addition, in a preferred embodiment, the high selection ratio of Oxide/Nitride is adopted in the pattern definition of the first direction and the second direction, so that the pattern is finer than other patterns.

Next, as shown in S10 in fig. 1 and fig. 23, step 10) is performed to planarize the structure obtained in step 9) until the top surface of the second spacer sacrificial layer 118 is exposed, and the remaining second filling mask layer 119a between the second longitudinal portions 118c of the second spacer sacrificial layer 118 on the sidewalls of the fourth pattern unit 117a remains;

specifically, in this step, planarization is performed through an etching process to remove a portion of the second filling mask layer 119, and expose the third lateral portion 118b of the second spacer sacrificial layer 118 on the top of the fourth pattern unit 117a, so as to perform a next process to prepare the pattern structure in the second direction.

As an example, the step 10) of planarizing the structure obtained in the step 9) to the second spacer sacrificial layer 118 includes: and etching the second filling mask layer 119, wherein the process parameters for etching the second filling mask layer 119 include: the etching gas comprises at least one of O2, AR, N2 and CH4, the etching pressure is between 5mT and 20mT, the source power is between 200W and 600W, and the bias voltage is between 200V and 600V.

Next, as shown in S11 in fig. 1 and fig. 24 to 27, step 11) is performed to etch and remove the third transverse portion 118b of the second sacrificial layer 118 located at the top of the fourth pattern unit 117a and the second longitudinal portion 118c of the second sacrificial layer 118 located on the sidewall of the fourth pattern unit 117a, so as to expose the etch stop layer 112 and obtain a fifth pattern layer 120, where the fifth pattern layer 120 includes a plurality of fifth pattern units 120a arranged in parallel at intervals, and a stack layer formed by the fourth pattern unit 117a located on the etch stop layer 112, the fourth transverse portion 118d of the second sacrificial layer 118 located on the surface of the etch stop layer, and the remaining second filling mask layer 119a thereon forms the fifth pattern unit 120 a.

As an example, when step 6) further includes forming a stress relief layer 113 between the etch stop layer 112 and the second pattern transfer layer 114, step 11) simultaneously etches the stress relief layer 113 during the process of etching away the second longitudinal portion 118c of the second spacer sacrificial layer 118 to form a relief layer pattern transfer layer 121.

Specifically, in this step, a pattern in the second direction is defined to finally form a capacitor hole structure, the fifth pattern unit 120a is composed of two parts, one part is the fourth pattern unit 117a, the other part is an etched stacked structure, and includes the fourth lateral portion 118d of the second spacer sacrificial layer 118 and the remaining second filling mask layer 119a thereon, in addition, when the stress relieving layer 113 is present, it is preferable that the material of the stress relieving layer 113 is the same as the material of the second spacer sacrificial layer 118, so that the stress relieving layer is also etched while the second longitudinal portion 118c is removed, and at this time, the formed fifth pattern layer 120 includes a structural layer etched by the stress relieving layer 113.

As an example, in step 11), the process parameters for etching and removing the third lateral portion 118b and the second longitudinal portion 118c of the second sacrificial spacer layer 118 include: the etching gas comprises at least one of O2, CH4 and CHF3, the etching gas preferably comprises three of O2, CH4 and CHF3, the etching pressure is between 1mT and 10mT, the source power is between 300W and 800W, and the bias voltage is between 10V and 100V.

In addition, as shown in fig. 25 to 27, when the stress relieving layer 113 exists, and the stress relieving layer 113 is etched at the same time when the fifth pattern layer 120 is formed, that is, the stress relieving layer 113 transfers the pattern on the fifth pattern layer 120 to form a relieving layer pattern transfer layer 121, which includes a plurality of relieving layer pattern transfer units 121a arranged in parallel at intervals, in a preferred embodiment, the method further includes a step of removing the fifth pattern layer 120 and retaining the relieving layer pattern transfer layer 121, as shown in fig. 25, and then a subsequent etching process is performed by using the relieving layer pattern transfer layer 121 as a mask.

Then, as shown in S12 in fig. 1 and fig. 28 to 30, step 12) is performed to selectively etch and remove the etch stop layer 112 and the dimension limiting unit 110 by using the fifth pattern unit as a mask, to transfer the pattern on the fifth pattern layer 120 onto the second pattern layer 106, to form a pattern transfer layer 122 on the dual pattern integration layer 102, the pattern transfer layer 122 includes a plurality of first pitch multiplying units 122a arranged in parallel and at intervals along the first direction and a plurality of second pitch multiplying units 122b arranged in parallel and at intervals along the second direction and connected to the first pitch multiplying units, wherein the first pitch multiplication unit 122a is composed of the second pattern unit 106a and the pattern auxiliary unit 111, the second pitch multiplication unit 122b is formed by transferring the fifth pattern unit 120 a;

illustratively, the pattern transfer layer 122 is formed to include at least one of a checkered pattern transfer layer and a diamond-shaped pattern transfer layer.

Specifically, in this step, the pattern in the first direction intersects with the pattern in the second direction, and in a preferred embodiment, the material of the etch stop layer 112 is the same as the material of the first spacing sacrificial layer 107, so as to facilitate the removal of the etch stop layer 112 and the size-defining unit formed by the first spacing sacrificial layer 107, and finally form the pattern transfer layer 122 as shown in fig. 28 and 29, so as to obtain a pattern for forming a capacitor hole by subsequent etching. Further, in a preferred embodiment, the material of the second pattern layer 106 is preferably the same as the material of the first filling mask layer 108, so as to facilitate the embodiment of the subsequent etching process, improve the uniformity of the pattern morphology, and improve the stability of the device performance. In addition, the pattern in the pattern transfer layer 122 formed in this example is selected according to actual conditions, and may be a mesh pattern, for example, when the first direction and the second direction are perpendicular to each other, the pattern topography in the pattern transfer layer 122 formed is in a cross-grid shape, that is, a plurality of grid shapes with uniform size and uniform array arrangement are formed, and of course, in other examples, the pattern may be selected according to requirements, such as a diamond-shaped pattern structure layer with uniform size.

Finally, as shown in S13 in fig. 1 and fig. 31 to 48, step 13) is performed to transfer the pattern on the pattern transfer layer 122 to the hard mask consumption layer 101 through the dual pattern integration layer 102 to obtain a patterned hard mask consumption layer 129, and the capacitance supporting sacrificial structure layer 300 is etched based on the patterned hard mask consumption layer 129 to form a plurality of semiconductor memory capacitor holes 307a uniformly spaced in the capacitance supporting sacrificial structure layer 300.

Specifically, the pattern on the pattern transfer layer 122 is transferred to the hard mask consumption layer 101, and the obtained patterned hard mask consumption layer 129 is used as a mask layer to perform a subsequent etching process of the capacitor hole, as shown in fig. 43 to 45. In a preferred embodiment, at least one etching gas of AR/CF4/O2 is used to open the surface layer under the conditions of 5-30 mt/HF, 200-500W/LF and 200-800W, and then at least one etching gas of HBR/NF3/O2 is used to open the hard mask consumption layer under the conditions of 30-200 mt/HF, 100-800W/LF and 500-1500W.

As an example, when the dual pattern integration layer 102 is present, the step 13) of transferring the pattern on the pattern transfer layer 122 into the hard mask consumption layer 101 further comprises: transferring the pattern on the pattern transfer layer 122 to the dual pattern integration layer 102, and comprises the following steps:

13-1) etching the fourth underlayer 102d with the pattern transfer layer 122 as a mask to obtain a first intermediate pattern transfer layer 123 and leave the pattern transfer layer remaining after etching, as shown in fig. 31 and 32, the fourth underlayer 102d is converted into the first intermediate pattern transfer layer 123, and the patterns in two directions of the pattern transfer layer 122 are transferred to form a first intermediate pattern transfer unit 123a in the first direction and a first intermediate pattern transfer unit 123b in the second direction;

13-2) depositing a pattern optimized sacrificial layer 124 on the surface of the structure obtained in the step 13-1), wherein the pattern optimized sacrificial layer 124 fills gaps between the first intermediate pattern transfer layer 123 and the patterns on the remaining pattern transfer layer 122 and covers the pattern transfer layer 122, as shown in fig. 33, wherein the same effect is generated in both the first direction and the second direction, which is only exemplified by the cross section in the second direction;

13-3) planarizing the pattern optimized sacrificial layer 124 to the remaining pattern transfer layer 122 and removing the remaining pattern transfer layer 122, wherein the pattern optimized sacrificial layer is transformed into a second intermediate pattern transfer layer 125 comprising a second direction second intermediate pattern transfer unit 125b, as shown in fig. 34 and 35, in the second direction, the pattern optimized sacrificial layer 124 is planarized to form the second intermediate pattern transfer layer 125, and thereafter, the remaining pattern transfer layer 122 is removed, leaving the fourth underlayer transfer layer 123, as shown in fig. 35, wherein the same effect is generated in both the first direction and the second direction, which is only exemplified by a cross section in the second direction;

13-4) removing the second intermediate pattern transfer layer 125, and etching the third pad layer 102c based on the first intermediate pattern transfer layer 123 obtained by etching in step 13-1), to obtain a third intermediate pattern transfer layer 126, including a second-direction third intermediate pattern transfer unit 126b, and adjusting the sizes of the patterns in the first direction and the second direction during etching the third pad layer, as shown in fig. 36, and adjusting the sizes of the patterns in the first direction and the second direction during etching the third pad layer 102c, in an example, where the pattern optimization sacrificial layer functions as shown in the figure, if the pattern optimization sacrificial layer is not present, the pattern transfer layer functions as a mask during direct etching, the materials are the same, the etching profile is distorted, if the pattern transfer layer is not removed first, since Oxide etching rate is faster, the underlying third pad layer is also damaged, so the topography is better. In addition, in this example, the CD size of the pattern obtained by the transfer in the first direction X is determined by the thickness of the sidewall deposition of Nitride (at this time, Nitride is the first spacer sacrificial layer 107), and here, whether the required CD size meets the requirement may be determined by the size of the CD in the transferred pattern (at this time, the CD may be the CD of the pattern in the fourth pad layer transfer layer 123 in fig. 35), and if the CD size is too large or too small, the CD size may be compensated and corrected by adjusting the time of etching the third pad layer, so as to correct the size of the pattern that is finally required to be obtained.

13-5) etching the second pad layer 102b to obtain a fourth intermediate pattern transfer layer 127, and etching the first pad layer 102a by using the fourth intermediate pattern transfer layer 127 obtained by etching as a mask to obtain a fifth intermediate pattern transfer layer 128, so as to transfer the pattern on the pattern transfer layer 122 into the first pad layer 102 a.

Specifically, in this step, the pattern on the pattern transfer layer 122 is transferred to the first pad layer 102a, so as to transfer the pattern on the pattern transfer layer 122 to the pattern trimming mask layer 102, and the present invention can obtain a pattern with precise topography through the design of the pattern trimming mask layer of the four pad layers, wherein the pattern on the pattern transfer layer 122 is not strictly an upper position and a lower position, and so on, and a person skilled in the art can determine the expressed meaning according to the illustration and the actual situation.

As an example, as shown in fig. 46, in step 1), the capacitive support sacrificial structure layer 300 includes an etching barrier layer 301 on the semiconductor substrate 100, and at least one dielectric sacrificial layer (302, 303, 305) and at least one support layer (304, 306) on the etching barrier layer 301; step 13) comprises: and etching the support layers (304, 306), the dielectric sacrificial layers (302, 303, 305) and the etch stop layer 301 based on the patterned hard mask consumption layer 129, and removing the patterned hard mask consumption layer 129 remaining after etching, so as to etch and form a plurality of semiconductor memory capacitor holes 307a uniformly spaced in the capacitor support sacrificial layer 300 on the semiconductor substrate 100.

Specifically, in this example, the capacitance support sacrificial structure layer 300 is etched, so that a capacitance hole structure on which a capacitor is subsequently fabricated can be obtained, wherein a semiconductor device layer 307 is formed, which includes a plurality of memory capacitance holes 307 a. In addition, in a preferred embodiment, the semiconductor base 100 may have a plurality of capacitor contacts in a memory array structure therein, the semiconductor base 100 may include a silicon substrate, a germanium-silicon substrate, a silicon carbide substrate, and the like, and in this embodiment, the semiconductor base 100 may be a silicon substrate. In addition, the memory array structure further comprises a transistor word line (Wordline) and a bit line (Bitline), and the capacitor contact is electrically connected with a transistor source electrode in the memory array structure. The capacitance contacts correspond to the arrangement of the subsequently manufactured capacitors. In addition, the capacitance contacts are isolated by a spacing layerThe material of (2) can be silicon nitride (SiN), silicon oxide (SiO)₂) Alumina (Al)₂O₃) In this embodiment, the material of the spacer layer is SiN.

As an example, the dielectric layer includes a first dielectric sacrificial layer 302, a second dielectric sacrificial layer 303, and a third dielectric sacrificial layer 305, and the support layer includes a first support layer 304 and a second support layer 306, where the first dielectric sacrificial layer 302, the second dielectric sacrificial layer 303, the first support layer 304, the third dielectric sacrificial layer 305, and the second support layer 306 are stacked in sequence from bottom to top.

As an example, the material of the etching barrier layer 301 includes silicon nitride, and the thickness of the etching barrier layer 301 is between 10nm and 80 nm; the material of the first dielectric layer 302 includes at least one of phosphorus-doped silicon oxide (PSG), boron-phosphorus-doped oxide layer (BPSG) and fluorine-doped silicon oxide glass (FSG), and the thickness of the first dielectric sacrificial layer 302 is between 100nm and 600 nm; preferably, the hardness of the second dielectric sacrificial layer 303 is greater than that of the first dielectric sacrificial layer 302 to improve the stability of a subsequent capacitor structure, the material of the second dielectric sacrificial layer 303 includes TEOS, and the thickness of the second dielectric sacrificial layer 303 is between 300nm and 1000 nm; the material of the third dielectric sacrificial layer 305 includes at least one of silicon oxide and TEOS, and the thickness of the third dielectric sacrificial layer 305 is between 300nm and 1000 nm; the material of the first support layer 304 comprises silicon nitride, and the thickness of the first support layer 304 is between 10nm and 80 nm; the material of the second support layer 306 comprises silicon nitride, and the thickness of the second support layer 306 is between 50nm and 200 nm.

Specifically, the present example provides a stacked material layer that can subsequently form the memory capacitor hole 307a, wherein a stacked dielectric sacrificial layer and a two-layer supporting layer structure are introduced, and the capacitor is easily toppled to form a short circuit due to the reduction of the size and the increase of the height of the capacitor, so that the two-layer supporting layer (Nitride) is introduced and matched with the configuration of the three dielectric sacrificial layers, so as to achieve the function of fixing the capacitor and prevent the short circuit problem caused by toppling of the capacitor. In addition, since the capacitor is deep hole etching, in order to reduce the occurrence of bottom underrout, the first dielectric sacrificial layer is preferably made of a relatively soft material, such as PSG/BPSG/FSG, and the hardness of the second dielectric sacrificial layer 303 is preferably greater than that of the first dielectric sacrificial layer 302, and may be TEOS or PSG/BPSG/FSG with a faster deposition rate than the first dielectric sacrificial layer 302. In addition, the third dielectric sacrificial layer 305 may be SiO2 or TEOS, etc. to achieve the required capacitance height.

In addition, during the process of etching the etching stop layer, the dielectric sacrificial layer and the support layer, a CCP machine is preferably used for etching, and the etching process of the second support layer 306 includes: the etching gas comprises at least one of C4F8, CHF3, CF4 and CH2F2 and is etched under the condition that the pressure is 5-50 mt/2MHZ 1000-5000W/27 MHZ 50-300W/60 MHZ 200-1000W; the etching process of the third dielectric sacrificial layer 305 includes: the etching gas comprises at least one of O2, C4F6 and NF3 and is etched under the condition that the pressure is 5-30 mt/2MHZ 4000-8000W/60 MHZ 500-1500W; the etching process of the first support layer 304 includes: the etching gas comprises at least one of C4F6, O2, C4F8, NF3 and CH2F2 and is used for etching under the condition that the pressure is 5-50 mt/2MHZ 1000-5000W/27 MHZ 100-500W/60 MHZ 200-800W; the etching process of the second dielectric sacrificial layer 303 comprises the following steps: the etching gas comprises at least one of C4F6, O2 and NF3 and is etched under the condition that the pressure is 5-30 mt 2MHZ 4000-8000W/60 MHZ 500-2000W; the etching process of the first dielectric sacrificial layer 302 comprises the following steps: the etching gas comprises at least one of C4F6, O2 and NF3 and is etched under the condition that the pressure is 5-30 mt 2MHZ 4000-8000W/60 MHZ 500-2000W; the etching process of the etching barrier layer 301 comprises the following steps: the etching gas comprises at least one of O2, CHF3 and CH2F2 and is etched under the condition of the pressure of 5-50 mt/2MHZ 200-1000W/27 MHZ 50-300W/60 MHZ 200-1000W.

As an example, the support layers (304, 306), the dielectric sacrificial layers (302, 303, 305) and the etching barrier layer 301 are etched by using a pulsed radio frequency etching method, wherein an etching period of the pulsed radio frequency etching method includes one time of pulse on and one time of pulse off, the pulse on is etched, the pulse off is removed by-products, and the pulse on time accounts for 70% to 90% of the etching period of the pulsed radio frequency etching.

Specifically, because the depth of etching is deeper, in order to make Profile better, a Pulse Etch mode is preferentially adopted, wherein the period of the radio frequency RF on is mainly changed from 100% to 70% -90% in Recipe setting, the whole radio frequency RF time is increased in the same proportion, and the radio frequency RF on time is ensured to be sufficient.

The present invention further provides a stacked structure in a process of manufacturing a capacitor hole of a semiconductor memory, as shown in fig. 28 to 30, where the stacked structure is preferably manufactured by a process in the process of manufacturing a capacitor hole of a semiconductor memory in this embodiment, and the process includes:

a semiconductor substrate 100;

the capacitance support sacrificial structure layer 300 comprises an etching barrier layer 301, and at least one dielectric sacrificial layer (302, 303, 305) and at least one support layer (304, 306) which are positioned on the etching barrier layer 301, wherein the etching barrier layer 301 is positioned on the surface of the semiconductor substrate 100;

a hard mask consumption layer 101 located on the surface of the capacitance support structure layer 300;

a dual pattern integration layer 102 on the surface of the hard mask consumption layer 101; and

the pattern transfer layer 122 is located on the dual pattern integration layer 102, and includes a plurality of first pitch multiplication units 122a arranged in parallel along a first direction at intervals, and a plurality of second pitch multiplication units 122b arranged in parallel along a second direction at intervals and connected to the first pitch multiplication units, an intersection angle is formed between the second direction and the first direction, a first pitch is generated between adjacent first pitch multiplication units, a second pitch is generated between adjacent second pitch multiplication units, and the first pitch and the second pitch are both defined by thicknesses of respective spaced sacrificial layers.

Specifically, the pattern in the pattern transfer layer 122 formed in this example is selected according to actual conditions, and may be a mesh pattern, for example, when the first direction and the second direction are perpendicular to each other, the pattern topography in the pattern transfer layer 122 formed is in a cross-grid shape, that is, a plurality of grid shapes with uniform size and uniform array arrangement are formed, and of course, in other examples, the pattern may be selected according to requirements, such as a diamond-shaped pattern structure layer with uniform size.

As an example, the stacked structure in the process of fabricating the capacitor hole of the semiconductor memory further includes a first pattern mask duplicate layer 308 for forming the first pitch multiplication unit 122a, the first pattern mask duplicate layer includes a plurality of first pattern units arranged in parallel at intervals and a plurality of second pattern units located between adjacent first pattern units, the second pattern units include a first bottom deposition layer and a first top deposition layer located on the first bottom deposition layer, and a distance between adjacent first pattern units and adjacent second pattern units is substantially the same as a thickness of the first bottom deposition layer.

Specifically, the present example provides a first pattern mask replication layer 308 capable of forming the first pitch multiplication unit 122a, which is specifically shown in fig. 11 of the present embodiment, the first pattern unit in the present example can be referred to as the second pattern unit 106a in fig. 11, and the second pattern unit in the present example can be referred to as the pattern auxiliary unit 111 in fig. 11, wherein the bottom deposition layer corresponds to the second lateral portion 107d of the first spacing sacrificial layer in the figure, and the top deposition layer corresponds to the remaining first filling mask layer 109a in the figure.

As an example, the stacked structure in the process of fabricating the capacitor hole of the semiconductor memory further includes a second pattern mask duplicate layer 120, in this case, the second pattern mask duplicate layer may be the fifth pattern layer in the process of fabricating the semiconductor memory in the embodiment of the present invention, the second pattern mask duplicate layer for forming the second pitch multiplication unit includes a plurality of third pattern units arranged in parallel at intervals and a plurality of fourth pattern units located between adjacent third pattern units, the fourth pattern units include a second bottom deposition layer and a second top deposition layer located on the second bottom deposition layer, and a pitch between adjacent third pattern units and the fourth pattern units is substantially the same as a thickness of the second bottom deposition layer.

Specifically, the present example provides a pattern capable of forming the second pitch multiplication unit 122b, which is specifically shown in fig. 23 and fig. 24 in the present embodiment, wherein the third pattern unit in the present example corresponds to the fourth pattern unit 117a in the figure, the fourth pattern unit in the present example corresponds to the fifth pattern unit 120a, the second bottom deposition layer corresponds to the fourth lateral portion 118d of the second spacer sacrificial layer in the figure, and the second top deposition layer corresponds to the remaining second filling mask layer 119 a.

As an example, the etching barrier layer 301 includes a silicon nitride layer, and the thickness of the etching barrier layer 301 is between 10nm and 80 nm; the first dielectric sacrificial layer 302 comprises at least one of a phosphorus-doped silicon oxide layer (PSG layer), a boron-phosphorus-doped oxide layer (BPSG layer) and a fluorine-doped silicon oxide glass layer (FSG layer), and the thickness of the first dielectric sacrificial layer 302 is between 100nm and 600 nm; preferably, the hardness of the second dielectric sacrificial layer 303 is greater than that of the first dielectric sacrificial layer 302 to improve the stability of a subsequent capacitor structure, the second dielectric sacrificial layer 303 includes a TEOS layer, and the thickness of the second dielectric sacrificial layer 303 is between 300nm and 1000 nm; the third dielectric sacrificial layer 305 comprises at least one of silicon oxide and a TEOS layer, and the thickness of the third dielectric sacrificial layer 305 is between 300nm and 1000 nm; the first support layer 304 comprises a silicon nitride layer, and the thickness of the first support layer 304 is between 10nm and 80 nm; the second support layer 306 comprises a silicon nitride layer, and the thickness of the second support layer 306 is between 50nm and 200 nm.

Specifically, the present example provides a stacked material layer that can subsequently form the capacitor support structure 307b and the memory capacitor hole 307a, wherein a stacked dielectric sacrificial layer and a two-layer support layer structure are introduced, and the capacitor is easily toppled to form a short circuit due to the reduction of the size and the increase of the height of the capacitor, so that the two-layer support layer (Nitride) is introduced and matched with the configuration of the three dielectric sacrificial layers, so that the effect of fixing the capacitor can be achieved, and the problem of short circuit caused by toppling of the capacitor can be prevented. In addition, since the capacitor is deep hole etching, in order to reduce the occurrence of bottom underrout, the first dielectric sacrificial layer is preferably made of a relatively soft material, such as PSG/BPSG/FSG, and the hardness of the second dielectric sacrificial layer 303 is preferably greater than that of the first dielectric sacrificial layer 302, and may be TEOS or PSG/BPSG/FSG with a faster deposition rate than the first dielectric sacrificial layer 302. In addition, the third dielectric sacrificial layer 305 may be SiO2 or TEOS, etc. to achieve the required capacitance height.

As an example, the intersection angle comprises 60 °; the first pitch multiplication units 122a are arranged in parallel at equal intervals, and the second pitch multiplication units 122b are arranged in parallel at equal intervals; the width of the first pitch multiplication unit is equal to that of the second pitch multiplication unit; the first and second pitches have the same width.

As an example, the dual pattern integration layer 102 in the stacked junction during the fabrication of the capacitor hole of the semiconductor memory is used to form the patterned hard mask consumption layer, as shown in fig. 28 to 30, wherein the dual pattern integration layer 102 includes, from bottom to top, a first pad layer 102a, a second pad layer 102b, a third pad layer 102c, and a fourth pad layer 102 d. According to the invention, by the design of the four cushion layers, the pattern can be corrected in the etching process, and the pattern with accurate appearance can be obtained.

For example, the first pad layer 102a is selected from any one of a silicon oxide layer and a tetraethyl orthosilicate (TEOS) layer, the second pad layer 102b is selected from any one of an amorphous silicon layer, a silicon oxynitride layer, and a silicon nitride layer, the third pad layer 102c is selected from any one of a silicon oxide layer and a tetraethyl orthosilicate (TEOS) layer, and the fourth pad layer 102d is selected from any one of an amorphous silicon layer, a silicon oxynitride layer, and a silicon nitride layer.

As an example, the stacked structure in the process of fabricating the capacitor hole of the semiconductor memory further includes a pattern transfer hard mask layer for pattern transfer forming at least one of the first pitch multiplying unit 122a and the second pitch multiplying unit 122b, wherein the pattern transfer hard mask layer includes at least one of an ashable hard mask layer (AHM) and a diamond-like thin film layer (DLC).

Specifically, in a preferred embodiment, the pattern transfer hard mask layer comprises a stacked structure of two material layers, including an Ashable hard mask layer (AHM) and a Diamond-like thin film layer (DLC) on the upper surface thereof, wherein the thickness of the Ashable hard mask layer is between 50nm and 200nm, preferably between 100nm and 150nm, and the thickness of the Diamond-like thin film layer is between 200nm and 300nm, preferably between 120nm and 180 nm; further preferably, the thickness of the diamond-like thin film layer is larger than that of the ashable hard mask layer, and the mask layer is subjected to the structural improvement for etching to form the first pattern pitch multiplication unit or for forming the second pattern pitch multiplication unit, so that compared with carbon and other mask materials, the mask layer has a better selection ratio, the migrated pattern is more accurate and is easier to remove by oxygen (O2).

As shown in fig. 47 and fig. 48, as an example, the capacitance supporting sacrificial structure layer 300 has a plurality of semiconductor memory capacitance holes 307a uniformly spaced; the invention also provides a semiconductor memory capacitor hole structure, which comprises a semiconductor device layer 307 formed by adopting the laminated structure layer in the preparation process of the semiconductor memory capacitor hole according to any scheme and etching the auxiliary structure layer based on the reticular pattern transfer layer, wherein the semiconductor device layer is positioned on the semiconductor substrate, and the semiconductor device layer 307 comprises a plurality of semiconductor memory capacitor holes 307a which are formed by etching and are uniformly distributed at intervals.

In summary, the present invention provides a method for preparing a capacitor hole of a semiconductor memory, including 1) providing a semiconductor substrate, and sequentially forming a capacitor supporting sacrificial structure layer, a hard mask consumption layer, a dual pattern integration layer, a first pattern migration layer and a first mask layer on the semiconductor substrate, wherein the first mask layer includes at least one of an ashable hard mask layer (AHM) and a diamond-like thin film layer (DLC); 2) forming a first pattern layer arranged along a first direction on the first mask layer, wherein the first pattern layer comprises a plurality of first pattern units arranged in parallel at intervals; 3) transferring the pattern on the first pattern layer to the first pattern transfer layer through the first mask layer to form a second pattern layer, wherein the second pattern layer comprises a plurality of second pattern units which are arranged in parallel at intervals; 4) forming a first spacing sacrificial layer on the top and the side wall of the second pattern unit and the surface of the double-pattern integration layer between the second pattern units, forming a first gap groove on the surface of the first spacing sacrificial layer between the adjacent second pattern units, and forming a first filling mask layer on the surface of the first spacing sacrificial layer, wherein the first filling mask layer covers the first spacing sacrificial layer and fills the first gap groove formed by the first spacing sacrificial layer; 5) removing a first transverse part of the first spacing sacrificial layer positioned on the top of the second pattern unit, the first filling mask layer and a part of the first filling mask layer positioned in the first gap groove, wherein a size limiting unit and a pattern auxiliary unit positioned between the size limiting units are formed between the adjacent second pattern units, a first longitudinal part of the first spacing sacrificial layer positioned on the side wall of the second pattern unit forms the size limiting unit, a second transverse part of the first spacing sacrificial layer positioned on the double-pattern integration layer and the rest of the first filling mask layer positioned on the second transverse part form the pattern auxiliary unit; 6) forming an etching stop layer, a second pattern migration layer and a second mask layer on the structure obtained in the step 5) in sequence; 7) forming a third pattern layer arranged along a second direction on the second mask layer, wherein the third pattern layer comprises a plurality of third pattern units arranged in parallel at intervals, and an intersection angle is formed between the second direction and the first direction; 8) transferring the pattern on the third pattern layer to the second pattern transfer layer through the second mask layer to form a fourth pattern layer, wherein the fourth pattern layer comprises a plurality of fourth pattern units which are arranged in parallel at intervals; 9) forming second spacer sacrificial layers on the tops and the side walls of the four pattern units and the surfaces of the etching stop layers between the fourth pattern units, forming a second gap groove on the surface of the second spacer sacrificial layer between the adjacent fourth pattern units, and forming a second filling mask layer on the surface of the second spacer sacrificial layer, wherein the second filling mask layer covers the second spacer sacrificial layer and fills the second gap groove formed by the second spacer sacrificial layer; 10) planarizing the structure obtained in the step 9) until the top surface of the second spacer sacrificial layer is exposed, and remaining second filling mask layers between second longitudinal portions of the second spacer sacrificial layer on the sidewalls of the fourth pattern units remain; 11) etching to remove a third transverse part of the second spacing sacrificial layer positioned at the top of the fourth pattern unit and the second longitudinal part of the second spacing sacrificial layer positioned on the side wall of the fourth pattern unit so as to expose the etching stop layer and obtain a fifth pattern layer, wherein the fifth pattern layer comprises a plurality of fifth pattern units which are arranged in parallel at intervals, and the fifth pattern unit is formed by a laminated layer formed by the fourth pattern unit positioned on the etching stop layer, a fourth transverse part of the second spacing sacrificial layer positioned on the surface of the etching stop layer and the residual second filling mask layer positioned on the fourth transverse part; 12) selectively etching and removing the etching stop layer and the size limiting unit by taking the fifth pattern unit as a mask so as to transfer the pattern on the fifth pattern layer to the second pattern layer to form a pattern transfer layer on the double-pattern integration layer, wherein the pattern transfer layer comprises a plurality of first pitch multiplication units which are arranged in parallel at intervals along the first direction and a plurality of second pitch multiplication units which are arranged in parallel at intervals along the second direction and connected with the first pitch multiplication units, the first pitch multiplication units are formed by the second pattern unit and the pattern auxiliary unit, and the second pitch multiplication units are formed by transferring the fifth pattern unit; and 13) transferring the pattern on the pattern transfer layer to the hard mask consumption layer through the double pattern integration layer to obtain a patterned hard mask consumption layer, and etching the capacitance support sacrificial structure layer based on the patterned hard mask consumption layer so as to form a plurality of semiconductor memory capacitance holes uniformly distributed at intervals in the capacitance support structure layer. Through the scheme, the two directions are respectively used for forming the side wall layers (spacers) for pattern doubling in the preparation of the semiconductor structure layer based on the pitch doubling, the pattern shrinking can be achieved in the process of 30nm and below based on the pitch doubling technology, further, the sizes of the two directions in the preparation process are controlled, the good uniformity of the pitch doubled patterns is achieved, further, the definition of the characteristic size in the device structure is improved, the problem of large and small holes is solved, the pattern correction is carried out in the preparation process through the improvement of the double pattern integration layer in the etching process, the pattern accuracy is improved, in addition, the structure layer is improved, the better selection ratio is achieved, the size defect of a capacitor is improved, and the yield is improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A method for preparing a capacitor hole of a semiconductor memory is characterized by comprising the following steps:

13) and transferring the graph of the graph transfer layer to the hard mask consumption layer through the double-graph integration layer to obtain a graphical hard mask consumption layer, and etching the capacitance supporting sacrificial structure layer based on the graphical hard mask consumption layer so as to form a plurality of semiconductor memory capacitor holes which are uniformly distributed at intervals in the capacitance supporting sacrificial structure layer.

2. The method as claimed in claim 1, wherein the dual pattern integration layer comprises a first pad layer, a second pad layer, a third pad layer and a fourth pad layer from bottom to top in sequence in step 1).

3. The method of claim 2, wherein the first pad layer comprises any one of silicon oxide and ethyl orthosilicate, and the thickness of the first pad layer is between 100nm and 500 nm; the second cushion layer is made of any one of amorphous silicon, silicon oxynitride and silicon nitride, and the thickness of the second cushion layer is between 100nm and 800 nm; the third cushion layer is made of any one of silicon oxide and tetraethoxysilane, and the thickness of the third cushion layer is between 100nm and 500 nm; the fourth pad layer is made of any one of amorphous silicon, silicon oxynitride and silicon nitride, and the thickness of the fourth pad layer is 50 nm-200 nm.

4. The method for forming a capacitor hole of a semiconductor memory according to claim 2, wherein before transferring the pattern on the pattern transfer layer into the hard mask consumption layer in step 13), further comprising: transferring the graph on the graph transfer layer to the double-graph integration layer, and the specific steps comprise:

13-5) etching the second cushion layer to obtain a fourth intermediate pattern transfer layer, and etching the first cushion layer by using the fourth intermediate pattern transfer layer obtained by etching as a mask to obtain a fifth intermediate pattern transfer layer so as to transfer the pattern on the pattern transfer layer into the first cushion layer.

5. The method of claim 1, wherein in step 1), the first pattern transfer layer comprises a bottom pattern transfer layer and a top pattern transfer layer on the bottom pattern transfer layer, wherein the bottom pattern transfer layer comprises at least one of a silicon oxide layer and a tetraethyl orthosilicate (TEOS) layer, and the top pattern transfer layer comprises a silicon-rich photoresist layer; and in the step 3), transferring the pattern on the first pattern layer to the bottom pattern transfer layer to form the second pattern layer.

6. The method for preparing a capacitor hole of a semiconductor memory according to claim 5, wherein the step 3) comprises: etching the first mask layer to transfer the pattern on the first pattern layer to the first mask layer, wherein the process parameters for etching the first mask layer include: the etching gas comprises at least one of O2, AR, N2 and CH4, the etching pressure is between 5mT and 20mT, the source power is between 200W and 600W, and the bias voltage is between 200V and 600V; the step 3) also comprises the following steps: etching the upper pattern transfer layer and the bottom pattern transfer layer to transfer the pattern on the first pattern layer to the bottom pattern transfer layer, wherein the process parameters for etching the upper pattern transfer layer comprise: the etching gas comprises at least one of N2, O2 and HE; the technological parameters for etching the bottom layer pattern transfer layer comprise: the etching gas at least comprises CH4 and CHF3, the ratio of CH4 to CHF3 is 3: 1-1: 1, the etching pressure is 1 mT-10 mT, the source power is 300W-800W, and the bias voltage is 10V-100V.

7. The method for preparing a capacitor hole of a semiconductor memory according to claim 1, wherein the step 4) further comprises: and depositing a planarization auxiliary layer on the surface of the first filling mask layer.

8. The method of claim 7, wherein the planarization auxiliary layer comprises at least one of an ashable hard mask layer (AHM) and a diamond-like thin film layer (DLC); the thickness of the planarization auxiliary layer is between 20nm and 100 nm.

9. The method of claim 7, wherein the step 5) of planarizing the structure obtained in step 4) to the second pattern layer comprises: etching the planarization auxiliary layer, etching the first filling mask layer and etching the first transverse part of the first interval sacrificial layer at the top of the second pattern unit, wherein the process parameters for etching the planarization auxiliary layer comprise: the etching gas comprises at least one of O2, AR, N2 and CH4, the etching pressure is between 5mT and 20mT, the source power is between 200W and 600W, and the bias voltage is between 200V and 600V; the technological parameters for etching the first filling mask layer comprise: the etching gas at least comprises CH4 and CHF3, the proportion of CH4 to CHF3 is 3: 1-1: 1, the etching pressure is 1 mT-10 mT, the source power is 300W-800W, and the bias voltage is 10V-100V; the process parameters for etching the first spacing sacrificial layer on the top of the second pattern unit comprise: the etching gas comprises at least one of CHF3, CH4 and SF6, the etching pressure is between 5mT and 30mT, the source power is between 300W and 600W, and the bias voltage is between 50V and 250V.

10. The method for preparing a capacitor hole of a semiconductor memory according to claim 1, further comprising the step of 6): forming a stress relieving layer between the etching stop layer and the second pattern migration layer; and 11) etching the stress relieving layer simultaneously in the process of etching and removing the second longitudinal part of the second interval sacrificial layer.

11. The method for preparing a capacitor hole of a semiconductor memory according to claim 1, wherein the step 8) comprises: etching the second mask layer to transfer the pattern of the third pattern layer to the second mask layer, wherein the process parameters for etching the second mask layer comprise: the etching gas comprises at least one of O2, AR, N2 and CH4, the etching pressure is between 5mT and 20mT, the source power is between 200W and 600W, and the bias voltage is between 200V and 600V; step 8) also includes: etching the second pattern migration layer to transfer the pattern of the third pattern layer to the second pattern migration layer, wherein the process parameters for etching the second pattern migration layer include: the etching gas comprises at least one of N2, O2 and HE.

12. The method for fabricating a capacitor hole of a semiconductor memory according to claim 1, wherein the step 10) of planarizing the structure obtained in the step 9) to the second spacer sacrificial layer comprises: and etching the second filling mask layer, wherein the technological parameters for etching the second filling mask layer comprise: the etching gas comprises at least one of O2, AR, N2 and CH4, the etching pressure is between 5mT and 20mT, the source power is between 200W and 600W, and the bias voltage is between 200V and 600V.

13. The method of claim 1, wherein the etching to remove the third lateral portion and the second longitudinal portion of the second spacer sacrificial layer in step 11) comprises: the etching gas comprises at least one of O2, CH4 and CHF3, the etching pressure is between 1mT and 10mT, the source power is between 300W and 800W, and the bias voltage is between 10V and 100V.

14. The method for forming a capacitor hole of a semiconductor memory according to claim 1, wherein the pattern transfer layer formed in step 12) comprises at least one of a checkered pattern transfer layer and a diamond-shaped pattern transfer layer.

15. The method for preparing the capacitor hole of the semiconductor memory according to claim 1, wherein in step 1), the capacitor supporting sacrificial structure layer comprises an etching barrier layer on the semiconductor substrate, and at least one dielectric sacrificial layer and at least one supporting layer on the etching barrier layer; step 13) comprises: and etching the supporting layer, the medium sacrificial layer and the etching barrier layer based on the patterned hard mask consumption layer, and removing the patterned hard mask consumption layer left after etching so as to etch and form a plurality of semiconductor memory capacitor holes which are uniformly distributed at intervals and positioned in the capacitor supporting sacrificial structure layer on the semiconductor substrate.

16. The method for preparing the capacitor hole of the semiconductor memory according to claim 15, wherein the supporting layer, the dielectric sacrificial layer and the etching barrier layer are etched by a pulse radio frequency etching method, wherein an etching period of the pulse radio frequency etching includes one pulse on and one pulse off, the pulse is etched when on, by-products are discharged when the pulse is off, and the pulse on time accounts for 70% -90% of the etching period of the pulse radio frequency etching.

17. The method of claim 15, wherein the dielectric layer comprises a first dielectric sacrificial layer, a second dielectric sacrificial layer and a third dielectric sacrificial layer, and the support layer comprises a first support layer and a second support layer, wherein the first dielectric sacrificial layer, the second dielectric sacrificial layer, the first support layer, the third dielectric sacrificial layer and the second support layer are sequentially stacked from bottom to top.

18. The method of claim 15, wherein the etch stop layer comprises silicon nitride, and has a thickness of 10nm to 80 nm; the material of the first dielectric layer comprises at least one of phosphorus-doped silicon oxide (PSG), boron-phosphorus-doped silicon oxide (BPSG) and fluorine-doped silicon oxide glass (FSG), and the thickness of the first dielectric layer is between 100nm and 600 nm; the hardness of the second dielectric layer is greater than that of the first dielectric layer, the material of the second dielectric layer comprises TEOS, and the thickness of the second dielectric layer is between 300nm and 1000 nm; the third dielectric layer is made of at least one of silicon oxide and TEOS, and the thickness of the third dielectric layer is 300 nm-1000 nm; the material of the first support layer comprises silicon nitride, and the thickness of the first support layer is between 10nm and 80 nm; the material of the second support layer comprises silicon nitride, and the thickness of the second support layer is between 50nm and 200 nm.

19. The method for forming a capacitor hole of a semiconductor memory according to any one of claims 1 to 18, wherein in the step 6), the second mask layer comprises at least one of an ashable hard mask layer (AHM) and a diamond-like thin film layer (DLC); in step 9), the second fill mask layer comprises at least one of an ashable hard mask layer (AHM) and a diamond-like carbon film layer (DLC).