KR940009611B1 - Manufacturing method of highly integrated semiconductor device capacitor - Google Patents

Abstract

forming a conductive layer on a semiconductor substrate; forming a groove on an isolation region for defining the conductive layer into unit cell; forming a first spacer on the sidewall of the groove; and etching the conductive layer using the first spacer as an etch mask to form a first storage electrode pattern; thereby improving the reliability of the capacitor.

Description

Capacitor Fabrication of Highly Integrated Semiconductor Devices Patterned Using Oxide Etch Masks (POEM Cells)

1A to 1C are cross-sectional views showing a capacitor manufacturing method of a highly integrated semiconductor device by a conventional method.

2 is a schematic layout diagram for manufacturing a capacitor of a highly integrated semiconductor device according to the present invention.

3A to 3E are cross-sectional views showing a first embodiment of a method of manufacturing a capacitor of a highly integrated semiconductor device patterned using an oxide film etching mask according to the present invention.

4 is a cross-sectional view of a memory device manufactured by a second embodiment of a method of manufacturing a capacitor of a highly integrated semiconductor device patterned using an oxide film etching mask according to the present invention.

5 is a cross-sectional view of a semiconductor device manufactured by a third embodiment of a method of manufacturing a capacitor of a highly integrated semiconductor device patterned using an oxide film etching mask according to the present invention.

6 is a cross-sectional view of a memory device manufactured by a fourth embodiment of a method of manufacturing a capacitor of a highly integrated semiconductor device patterned using an oxide film etching mask according to the present invention.

7 is a cross-sectional view of a semiconductor device manufactured by a fifth embodiment of a method of manufacturing a capacitor of a highly integrated semiconductor device patterned using an oxide film etching mask according to the present invention.

8A to 8C are cross-sectional views showing a sixth embodiment of a method of manufacturing a capacitor of a highly integrated semiconductor device patterned using an oxide film etching mask according to the present invention.

9 is a cross-sectional view of a semiconductor device manufactured by a seventh embodiment of a method of manufacturing a capacitor of a highly integrated semiconductor device patterned using an oxide film etching mask according to the present invention.

10A to 10E and 11 are cross-sectional views showing an eighth embodiment of a method of manufacturing a capacitor of a highly integrated semiconductor device patterned using an oxide film etching mask according to the present invention.

12A to 12C are sectional views showing a ninth embodiment of a method of manufacturing a capacitor of a highly integrated semiconductor device patterned using an oxide film etching mask according to the present invention.

13A to 13B are sectional views showing a tenth embodiment of a method of manufacturing a capacitor of a highly integrated semiconductor device patterned using an oxide film etching mask according to the present invention.

14A to 14E are sectional views showing an eleventh embodiment of a method of manufacturing a capacitor of a highly integrated semiconductor device patterned using an oxide film etching mask according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a highly integrated semiconductor device patterned by using an oxide film etching mask which presents a method of increasing cell capacitance and a method of manufacturing a reliable capacitor.

The reduction of cell capacitance due to the reduction of memory cell area is a serious obstacle to increasing the density of DRAM (Dynamic Random Access Memory), which not only reduces the readability of the memory cell and increases the soft error rate but also device operation at low voltage. This problem must be solved for high integration of the semiconductor memory device because it causes excessive power consumption during operation.

As a result of many studies to obtain the maximum cell capacitance in a limited area, a three-dimensional stack structure, a cylindrical structure capacitor, has been proposed, which is relatively simple in its manufacturing process and has high reliability and high capacitance. 1A to 1C, a method of manufacturing a cylindrical capacitor by the conventional method will be described.

A drain region 16 and a bit line in contact with the drain region are shared with each other in the active region of the semiconductor substrate 10, which is divided into an active region and an inactive region by the field oxide film 12. After forming the transistors having the 14 and the gate electrode 18, an insulating layer 19 is formed on the entire surface of the semiconductor substrate on which the transistor is formed to insulate the transistor from other elements, and the storage electrode Contact holes 9 for contacting the source regions 14 are formed. Subsequently, a material such as polyimide is thickly coated on the entire surface of the resultant, and then the surface is planarized, and the material is patterned using a mask pattern (not shown) for forming the storage electrode. A pattern 30 is formed (FIG. 1a), and a conductive material such as a material filling the contact hole on the entire surface of the semiconductor substrate on which the reverse pattern 30 for forming the storage electrode is formed, for example, is doped with impurities. After the polysilicon is deposited to a certain thickness and the result is thickly applied to the photoresist on the entire surface, the photoresist is etched back until the uppermost surface of the deposited conductive material is partially exposed. The photoresist pattern 72 is formed to fill the generated wells. Subsequently, anisotropic etching is performed over the entire surface of the semiconductor substrate using the photoresist pattern 72 as an etching mask, thereby limiting the conductive material to each cell unit (FIG. 1B). The storage electrode 100 is removed only when the inverse pattern 30 and the photoresist pattern 72 are removed. The polyimide used to form the inverse pattern is formed of a conductive material constituting the storage electrode. In the wet etching process, the etch selectivity is not good, and the thickness of the conductive material is thin (usually about 1,000 to 2,000Å), so that the cylinder forming the storage electrode of the cylindrical structure does not endure the etching process and collapses or breaks. There is a tendency to form a reliable storage electrode is difficult.

In order to improve this problem, the experiment was conducted by replacing the conductive material and the material having good etching selectivity with the material constituting the reverse pattern, but the basic problem solving was insufficient (FIG. 1C). In addition, the shape of the top surface of the exposed conductive material, that is, the top of the cylinder, is sharpened in the anisotropic etching process for limiting the conductive material on a cell-by-cell basis. Lowers.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a capacitor of a highly integrated semiconductor device patterned using an oxide film etching mask for manufacturing a cylindrical capacitor reliably.

Another object of the present invention is to provide a capacitor manufacturing method of a highly integrated semiconductor device patterned using an oxide film etching mask which can easily achieve an increase in cell capacitance.

In a first embodiment for achieving the above and other objects of the present invention, in a capacitor manufacturing method of a semiconductor device comprising a storage electrode, a dielectric film, and a plate electrode, the step for forming the storage electrode is a semiconductor substrate. Forming a conductive material layer on the substrate; Forming a groove having a predetermined depth in an isolation region for limiting the conductive material layer to each capacitor unit by using a mask pattern for forming a storage electrode; Forming a sidewall spacer made of a material having an etch rate different from that of the conductive material layer on the sidewall of the groove; Forming a cylindrical storage electrode by separating the conductive material layer by each capacitor unit by using the sidewall spacer as an etch mask; And removing the sidewall spacers.

According to a second embodiment of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor memory device including a memory cell including one transistor and one capacitor in a matrix shape on a semiconductor substrate. Applying a planarization material to the entire surface of the semiconductor substrate on which the transistor having a drain region and a gate electrode is formed; Forming a contact hole by partially exposing the source region of the transistor; Depositing a first conductive material to completely fill the contact hole and to have a predetermined thickness from the surface of the planarization material; Forming a storage electrode pattern on the first conductive material by etching the first conductive material by a predetermined depth using a mask pattern for forming a storage electrode; Applying an etch mask material to the entire surface of the resultant in which the storage electrode pattern is formed; Anisotropically etching the etching mask material to form a spacer-type etching mask on sidewalls of the storage electrode pattern; Forming a storage electrode defined for each cell unit by performing an anisotropic etching process using the etching mask as the end point of the planarization material; Removing the etching mask; Forming a dielectric film over the storage electrode; And forming a plate electrode by depositing a second conductive material on the entire surface of the resultant.

According to a third embodiment of the present invention, there is provided a method of forming a first storage electrode pattern on the first conductive material by using the mask pattern for forming a storage electrode. Forming a first etching mask, forming a second storage electrode pattern by etching the first conductive material again by a predetermined depth using the first etching mask, and forming a second storage electrode pattern on a sidewall of the second storage electrode pattern. A process of forming an etch mask and a process of completing a storage electrode by limiting the first conductive material to each cell unit by using the second etch mask. According to the third embodiment, not only a cylindrical capacitor having a double cylinder can be obtained, but also the cell capacitance can be increased by several times by repeatedly etching the first conductive material using an etching mask. The increase can be easily achieved.

According to a fourth embodiment of the present invention, a storage electrode pattern of a pattern forming material is formed on the first conductive material, and then an etching mask is formed on the pattern side wall. It is made of a process of forming.

The fifth embodiment for achieving the above and other objects of the present invention is to apply the same principle as the third embodiment, after forming the first etching mask on the sidewalls of the first storage electrode pattern of the pattern forming material Forming a second storage electrode pattern of the first conductive material on the first conductive material by etching the first conductive material to a predetermined depth, and forming a second etching mask on the sidewalls of the second storage electrode pattern. The second conductive material may be re-visualized to complete a storage electrode defined for each cell. According to the fifth embodiment, it is possible to easily achieve an increase in cell capacitance.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

FIG. 2 is a schematic layout diagram for manufacturing a capacitor of a highly integrated semiconductor memory device according to the present invention, which is referred to published by Hitachi of Japan.

The region, which is located at the center and is defined by a dashed line in a diagonal line, is a mask pattern (P1) for forming a field oxide film for dividing a semiconductor substrate into an active region and an inactive region. The region defined by the solid line is a mask pattern P2 for forming the gate electrode. The region defined by the solid line is located in the center and crosses diagonal lines. The region defined by the solid line forms contact holes for contacting the bit line with the drain region. And a mask pattern P3 for each of the cells, each of which is formed on the left and right sides of the center part, is a rectangular shape horizontally long, and is defined by each cell and is defined by a long dashed line, and is a mask pattern P4 for forming a storage electrode pattern. A rectangular shape smaller than the pattern P4 and defined by the short dashed line is the first stowage. If the mask pattern (P5) for the electrode pattern is formed.

3A to 3E are cross-sectional views showing a first embodiment of a method of manufacturing a capacitor of a highly integrated semiconductor device patterned using an oxide film etching mask according to the present invention, and the AA line of FIG. 2 is cut out.

First, referring to FIG. 3A, a process of sequentially stacking the planarization layer 40, the etch stop layer 42, and the spacer layer 44 on a semiconductor substrate on which a transistor is formed is shown. The drain region 16 and the bit line 20 in contact with the drain region are shared in the active region of the semiconductor substrate 10 divided into active and inactive regions by 12), and each source region is one. After the transistor having the transistor 14 and the gate electrode 18 is formed, the insulating layer 19 is formed on the entire surface of the semiconductor substrate on which the transistor is formed for the purpose of insulating the transistor. Subsequently, a planarization layer 40 is formed for the purpose of planarizing the surface of the semiconductor substrate having a step difference on the surface thereof by the transistor manufacturing process, and then, as the etching stop layer 42, silicon having a thickness of, for example, about 30 to 300 mW. A spacer layer 44 is formed by applying a material such as nitride (SiN) to the entire surface of the planarization layer, and then applying a material such as oxide to a thickness of, for example, about 500 kPa to about 2,000 kPa.

In this case, the etch stop layer 42 should be made of a material having an etching rate different from that of the spacer layer for wet etching for removing the spacer layer. In general, the etch stop layer has a higher etch rate than the spacer layer. This material should be made of much lower material. In the present invention, as described above, silicon nitride is used as the etch stop layer 42 and an oxide film is used as the spacer layer 44.

Referring to FIG. 3B, a process of forming a contact hole and a process of forming a storage electrode pattern 47 includes a mask pattern for forming a contact hole for contacting a storage electrode with a source region of a transistor. The contact hole by partially removing the insulating layer 19, the planarization layer 40, the etch stop layer 42, and the spacer layer 44 stacked on the source region (not shown in FIG. 2). And a first conductive material 46 such as polycrystalline silicon doped with impurities so as to completely fill the contact hole and have a predetermined thickness, for example, about 6,000 Pa to about 10,000 Pa based on the spacer layer. After depositing the material, a photoresist is applied to the entire surface of the first conductive material, and the first conductive material is formed using the mask pattern P4 of FIG. 2 for forming a storage electrode pattern. After the photoresist pattern 70 is formed on the substrate, the pattern is used as an etching mask, and the first conductive material is etched by a predetermined thickness, for example, a thickness of about 500 to 3,000 mm (first conductive per unit time). The storage electrode pattern 47 is formed on the first conductive material by calculating the amount of the material to be etched, and then removing the material by etching the calculated etching time according to the desired amount of etching. Since the thickness of the first conductive material is an important factor in determining the cell capacitance, it is preferable to adjust the thickness after determining the desired cell capacitance. The height of the sidewall of the storage electrode pattern 47 may be easily formed with a spacer on the sidewall. The height is sufficient, and the profile is preferably formed to have a slight negative or vertical inclination based on a flat surface, which indicates that a sharp fence is formed along the inner wall of the finished storage electrode. To prevent.

Referring to FIG. 3C, a process of forming an etch mask 80 on a sidewall of the storage electrode pattern 47 is performed. The photoresist pattern 70 is removed and the first conductive material is dried. A material having a different etching rate than that of the first conductive material for dry etching, for example, an oxide film such as high temperature oxide film (HTO) or a nitride film such as silicon nitride (SiN) of about 500 kPa to 2,000 After coating to a thickness of about Å, anisotropic etching is performed on the entire surface of the resultant to form an etching mask 80 for etching a spacer of an oxide film or a nitride film on the sidewall of the storage electrode pattern, that is, a polysilicon used as a first conductive material. Form.

Referring to FIG. 3D, a process of completing the storage electrode 100 is illustrated. The surface of the spacer layer 44 is formed by using the etching mask 80 formed on the sidewall of the storage electrode pattern 47. As the end point of etching, the cylindrical storage electrode 100 defined in each cell unit is completed by anisotropically etching the first conductive material. At this time, the profile of the storage electrode is preferably formed to have a vertical or positive inclination based on the spacer layer, which is generated between the storage electrodes when the second conductive material is deposited to form the plate electrode. This is to prevent the formation of voids.

According to FIG. 3D, it is possible to obtain a clean profile in which the collapse or break of the cylinder and the sharpening of the top of the cylinder are not found.

Referring to FIG. 3E, the process of forming the dielectric film 110 and the plate electrode 120 is performed by dipping a semiconductor substrate on which the storage electrode 100 is formed in an etching mask material etchant. The mask is removed and then the spacer layer is removed using an etchant. In this case, when the material constituting the spacer layer and the etching mask material are the same material, it is preferable to proceed with the two processes in one process, and the effective capacitor area for increasing cell capacitance in the space where the spacer layer is removed. Can be used as In the present invention, the two materials were used as the same material. In addition, before or after the etching mask removing process, the semiconductor substrate is exposed to the etchant for removing the first conductive material, thereby removing a fence that may be formed on the sidewall of the etching mask. Subsequently, the dielectric film 110 is formed by applying a high dielectric material such as O / N / O to the entire surface of the result of forming the storage electrode 100 and forming the dielectric film 110 on the entire surface of the resultant product on which the dielectric film is formed. 2, a plate material 120 is formed by depositing polysilicon doped with a conductive material such as impurities.

The above-described method for manufacturing a capacitor (POEM cell; A CAPACITOR IS PATTERNED BY OXIDE ETCH MASK) of a highly integrated semiconductor device patterned by using an oxide film etching mask has a different etching rate from the conductive material constituting the storage electrode for anisotropic etching. By adopting a method of patterning the conductive material by using a material as an etch mask material, it is possible to prevent the leakage current from easily occurring due to the collapse or break of the cylinder constituting the cylindrical capacitor and the sharp top of the cylinder, which have been a problem in the conventional method. In addition, since the storage electrode can be formed of one conductive material, not only can the reliability of the capacitor be further increased, but the process is simple, so that the cost and time required for manufacturing can be reduced, and mass production is easy. Rather than the maximum feature size that can be formed by design rules The large cylindrical storage electrode can be formed, making it easy to achieve increased cell capacitance, making it suitable for DRAM cells of 64Mb or higher.

In another embodiment of the present invention, the same reference numerals as those used in FIGS. 3A to 3E mean the same parts.

4 is a cross-sectional view of a semiconductor device manufactured by a second embodiment of a method of fabricating a capacitor of a highly integrated semiconductor device patterned using an oxide film etching mask according to the present invention, wherein a contact hole for contacting a storage electrode with a source region of a transistor is shown. In this case, the etch stop layer 42 and the spacer 82 are formed on the inner sidewall. The trend toward miniaturization of transistors is that even if the contact holes formed on the transistors are formed with a minimum feature size, the surface of the gate electrode 18 or the bit line 20 may be partially exposed by an etching process for forming the contact holes. Increasing the possibility, it is a serious cause of leakage current in memory cells, especially DRAM cells. The spacer 82 may be formed to surround the gate electrode or the bit line, which may be partially exposed by the etching process for forming the contact hole, thereby eliminating the cause of the leakage current mentioned above. At this time, the etching support layer 42 forms the storage electrode 100 in each cell unit, and then the spacer 82 is damaged by the process of removing the etching mask 80 and the spacer layer 44. Was provided to prevent that.

5 is a cross-sectional view of a semiconductor device manufactured by a third embodiment of a method of manufacturing a capacitor of a highly integrated semiconductor device patterned using an oxide film etching mask according to the present invention, wherein the etch stop layer 42 and the spacer layer 44 are shown in FIG. This is the case when the process is performed without forming.

6 is a cross-sectional view of a semiconductor device manufactured by a fourth embodiment of a method of manufacturing a capacitor of a highly integrated semiconductor device, patterned using an oxide film etching mask, according to an embodiment of the present invention. In this case, the planarization layer 40 is excessively etched in the wet etching process of removing the etch mask 80 to use the effective area for increasing the cell capacitance to the lower surface of the storage electrode 100. According to this method, a cell capacitance slightly larger than that of the semiconductor device of FIG. 5 can be obtained.

FIG. 7 is a cross-sectional view of a semiconductor device manufactured by a fifth embodiment of a method of manufacturing a capacitor of a highly integrated semiconductor device patterned using an etch mask according to the present invention, and the planarization layer 40 described with reference to FIG. This is the case when the process is performed without forming. Although the cell capacitance may be slightly larger than that in the process of forming the planarization layer (FIGS. 3A to 3E), an additional mask for limiting the storage electrode to each cell unit must be added. As a result, the process is complicated.

8A to 8C are cross-sectional views illustrating a sixth embodiment of a method of manufacturing a capacitor of a highly integrated semiconductor device patterned using an oxide film etching mask according to the present invention, taken along line AA of FIG.

First, referring to FIG. 8A, a process of forming the first etching mask 80 on the sidewalls of the first storage electrode pattern 47 is illustrated in FIGS. 3A to 3C (however, forming the storage electrode). The mask pattern P5 is used instead of the mask pattern P4 as a mask pattern for forming the first storage electrode pattern 47 on the first conductive material 46, and a first etching mask on the sidewall thereof. 80 is formed in the same manner as mentioned in FIG. 3C above.

The dotted line shown in FIG. 8A illustrates the second storage electrode pattern obtained after time etching the first conductive material using the first etching mask 80.

Referring to FIG. 8B, a process of forming the second storage electrode pattern 49 and the second etching mask 82 is performed. The time etching is performed on the first conductive material using the first etching mask. As a result, the second storage electrode pattern 49 is formed, and the second etching mask 82 is formed by the same method of forming the first etching mask on the sidewall of the second storage electrode pattern 49. At this time, the minimum height of the sidewall of the second storage electrode pattern should be such that the thickness of the second etching mask can be easily formed, for example, about 500 kPa to 3,000 kPa, and the profile of the side wall is negative based on a flat surface. It is preferable to form so as to have inclination or a vertical inclination. In addition, the thickness of the second etching mask in the lateral direction is preferably about 500 kPa to about 1,500 kPa.

The height of the sidewall and the transverse thickness of the etching mask mentioned above are not limited to the numerical values mentioned in the above embodiments, but may be changed by various variables such as the type of the first conductive material, the type of the etching mask material and the etching method. It will be apparent to those skilled in the art that it can.

Referring to FIG. 8C, a process of forming the storage electrode 100, the dielectric layer 110, and the plate electrode 120 is illustrated. The spacer layer 44 is formed using the second etching mask 82. After the anisotropic etching is performed using the surface of) as the end point, the storage electrode 100, which is limited to each cell unit and formed of a double cylinder, is formed, and then the second etching mask and the spacer layer are removed. Subsequently, after forming the dielectric film 110 on the entire surface of the semiconductor substrate on which the storage electrode is formed, the plate electrode 120 is formed by depositing a second conductive material on the entire surface of the resultant. In this case, the anisotropic etching process is preferably performed so that the sidewall of the storage electrode 100 has a vertical or positive inclination with respect to a flat surface, which may be formed between the storage electrodes in the process of depositing the second conductive material. to prevent (void) creation.

According to the semiconductor device of the sixth embodiment described above, since the cylindrical storage electrode composed of double cylinders can be formed by repeating the process of patterning the first conductive material using an etching mask, an increase in cell capacitance is achieved. It can be achieved easily.

9 is a cross-sectional view of a semiconductor device manufactured by a seventh embodiment of a method of fabricating a capacitor of a highly integrated semiconductor device, patterned using an oxide film etching mask, according to an embodiment of the present invention, wherein the first conductive material is patterned using an etching mask. The process was carried out three times. This shows that by performing the patterning process several times, multiple layers of cylinders can be made, whereby the cell capacitance can be easily increased.

At this time, it should be noted that the deposition thickness of the first conductive material, the lateral thickness of each etching mask, and the height of the sidewall of each storage electrode pattern should be appropriately adjusted.

10A to 10E and 11 are cross-sectional views showing an eighth embodiment of a method of manufacturing a capacitor of a highly integrated semiconductor device patterned using an oxide film etching mask according to the present invention. The AA line of FIG. 2 is cut out, and FIG. 11 is the BB line of FIG. 2 cut out.

First, referring to FIG. 10A, a process of forming the first storage electrode pattern 70 and the first etching mask 84 is illustrated, and is formed on the entire surface of the resultant formed by the method of FIGS. 3A to 3B. The first conductive material 50 is deposited, for example, with a predetermined thickness of a material such as polycrystalline silicon doped with impurities, and then a pattern forming material is coated on the entire surface of the first conductive material. In this case, as the pattern forming material, any material can be formed as long as the pattern is possible and the etching rate is different from that of the etching mask material for the anisotropic etching. However, in the present invention, the bake formed by the multilayer raster method (MLR method) or the like Photoresist, silicon nitride (SiN), or the like was used. Since the baked photoresist and the silicon nitride can be arbitrarily adjusted when the pattern is formed, the fence formation problem mentioned in FIG. 3b can be solved. The sidewall slope is preferably formed to have a negative or vertical slope with respect to the horizontal plane. However, when the baked photoresist is used as the pattern forming material, the process is inconvenient because the material to be applied after the pattern formation, that is, the etching mask material should be limited to a material that can be deposited at low temperature. Subsequently, the pattern forming material is partially etched using the mask pattern P5 of FIG. 2 for forming the first storage electrode pattern to form the first storage electrode pattern 70 made of the pattern forming material. In addition, the etching mask material is applied to the entire surface of the resultant pattern 70 is formed, wherein when using the baked photoresist mentioned by the pattern forming material, a material capable of low temperature deposition, such as PE-TEOS (Plasma Enhanced) -Tetra-Ethyl-Ortho Silicate, PE-Silain (Plasma Enhanced-Silain) and the like are applied, and in the case of silicon nitride, the same materials as mentioned in the previous embodiments are applied. Subsequently, the etching mask material is anisotropically etched to form spacers of the etching mask material, that is, the first etching mask 84, on the sidewalls of the pattern 70.

10B illustrates a process of forming the second storage electrode pattern 52, wherein the second conductive material is anisotropically etched by a predetermined depth using the first food mask 84 to form the second storage electrode pattern 52. The storage electrode pattern 52 is formed. At this time, the anisotropic etching proceeds with a time etch.

Referring to FIG. 10C, a process of forming the second etching mask 86 is shown. The anisotropic etching is performed by applying an etching mask material to the entire surface of the semiconductor substrate on which the second storage electrode pattern 52 is formed. A second etching mask 86 is formed on sidewalls of the second storage electrode pattern.

Referring to FIG. 10D, a process of forming the storage electrode 100 is illustrated. Anisotropic etching is performed using the second etching mask and the surface of the spacer layer 44 as an end point for etching. The storage electrode 100, which is limited to and is composed of a cylinder of migration, is determined. At this time, the profile of the storage electrode is a vertical or positive sidewall slope based on a flat surface in order to prevent the generation of voids that may occur between the storage electrodes when depositing the second conductive material for forming the plate electrode It is desirable to have.

Referring to FIG. 10E, the process of forming the dielectric film 110 and the plate electrode 120 is performed. After removing the second etching mask 86 and the spacer layer 44, the semiconductor substrate may be formed on the entire surface of the semiconductor substrate. For example, the dielectric layer 110 may be formed by applying a high dielectric material such as O / N / O, and then the plate electrode 120 may be formed by depositing a second conductive material such as polycrystalline silicon doped with impurities. Complete

At this time, referring to the cross section taken along the line AA of FIG. 2 (FIGS. 10A to 10E), the double cylinder patterned by the etching mask is not connected to the conductive material filling the contact hole. Although formed. Referring to the cross-sectional view taken along line BB of FIG. 2 (FIG. 11), since it is formed in a connected shape, there is no problem in the overall structure of the storage electrode.

In the above-described embodiment, in order to manufacture a double cylinder, the patterning process using an etching mask was performed twice. However, when the process is performed only once, as shown in FIG. 3E, only one cylinder has a storage electrode formed therein. It will be apparent to those skilled in the art that the present invention can be obtained. In addition, it is possible to solve the problem of the fence problem in the previous embodiment.

12A through 12C are cross-sectional views illustrating a ninth embodiment of a method of manufacturing a capacitor of a highly integrated semiconductor device patterned using an oxide film etching mask according to the present invention. Referring to FIGS. 10A through 10E, In the cross-sectional view taken along the line AA of FIG. 2, the conductive material filling the cylinder and the contact hole is separated from each other.

After forming the first storage electrode pattern 70 and the first etching mask 87 made of the pattern forming material in the same manner as described with reference to FIG. 10a, anisotropic etching is performed on the entire surface of the resultant material, and the first conductive material ( By etching 46, a first storage electrode pattern 47 made of a first conductive material is formed on the first conductive material 46 (FIG. 12A). Subsequently, after removing the first storage electrode pattern formed of the pattern forming material, the second storage electrode pattern 49 is formed by re-etching the first conductive material by a predetermined depth using the first etching mask. The second etching mask 88 is formed on the sidewall of the second storage electrode pattern 49 by applying an etching mask material on the entire surface of the resultant and then performing anisotropic etching process (FIG. 12B), and using the second etching mask. By performing an anisotropic etching process using the spacer layer 44 as the end point of etching, the storage electrode 100 limited to each cell unit is completed. The dielectric film 110 and the plate electrode 120 are formed by a conventional method.

13A and 13B are cross-sectional views showing a tenth embodiment of a method of manufacturing a capacitor of a highly integrated semiconductor device patterned using an oxide film etching mask according to the present invention, in which the AA line of FIG. Another embodiment is for preventing the conductive material filling the contact hole from being separated. After the first storage electrode pattern 70 and the etching mask 89 made of the pattern forming material are formed, anisotropic etching or time etching is performed by using the spacer layer 44 as the end point of etching. After the first conductive material is limited to each cell unit (FIG. 13A), the first storage electrode pattern made of the pattern forming material is removed. Subsequently, the first conductive material is etched to a predetermined depth by using the remaining etching mask 89 to complete the storage electrode 100. The etch mask is then removed (FIG. 13B).

14A to 14E are cross-sectional views showing an eleventh embodiment of a method of manufacturing a capacitor of a highly integrated semiconductor device patterned using an oxide film etching mask according to the present invention, and may be formed on an inner side wall of a cylindrical storage electrode. ) Is to solve the problem. After forming the first conductive material 46 in the same manner as described with reference to FIGS. 3A and 3B, an etch stop layer 91 and a second conductive material 92 are stacked on the entire surface of the first conductive material. . At this time, the etch stop layer should be made of a material different in etching rate from the first and second conductive materials with respect to dry etching, and when the polysilicon is used as the first and third conductive materials, the etching It is preferable to use an oxide film such as HTO or a nitride film such as silicon nitride (SiN) as the material constituting the stop layer 91.

Usually, the thickness is about 100 kPa-300 kPa (FIG. 14A). Subsequently, the storage electrode pattern 70 made of the second conductive material is formed using the mask pattern 14 of FIG. 2 for forming the storage electrode. In this case, the inclination of the sidewall of the pattern 70 may be arbitrarily adjusted by the etch stop layer 91, because the inclination of the sidewall of the pattern 70 may be adjusted by overetching the sidewall of the pattern. The inclination of the side wall is preferably negative or vertical (FIG. 14B). On the entire surface of the resultant, an etch mask 90 is formed on the sidewall of the pattern 70 by applying an anisotropic etch after applying a material having an etch rate different from that of the first and second conductive materials to the anisotropic etch, that is, an etching mask material. To form. At this time, in the present invention, either the oxide film such as HTO or the nitride film such as silicon nitride is used as the etching mask material (FIG. 14C). Subsequently, the storage electrode pattern 47 is formed on the first conductive material by time-etching the first conductive material by a predetermined depth using the storage electrode pattern 70 made of the second conductive material and the etching mask 90. (Fig. 14d). The cylindrical storage electrode 100 removes the storage electrode pattern 70 made of a second conductive material and the etch stop layer 91 on the bottom surface of the pattern, and then uses the etch mask 90 to form the spacer layer 44. This is completed by performing anisotropic etching with the surface of) as the end point (Fig. 14E).

According to the method for manufacturing a capacitor of a highly integrated semiconductor device according to the present invention, since the storage electrode is formed by a process of patterning a conductive material using an oxide film etching mask, the cylinder constituting the cylindrical capacitor, which has been a problem in the conventional method, is collapsed. In addition, since the breakage and the cylindrical profile are roughened, leakage current can be easily prevented, and the storage electrode can be formed of one conductive material, thereby increasing the reliability of the capacitor and simplifying the process. The cost and time required for manufacturing can be reduced, so mass production is easy. In addition, it is possible to form a cylindrical storage electrode larger than the minimum feature size that can be formed by the design line, so that it is easy to achieve an increase in cell capacitance, which is suitable for DRAM cells of 64Mb and above.

It is apparent that the present invention is not limited to the above embodiments, and many modifications are possible by those skilled in the art within the technical spirit of the present invention.

Claims (50)

A first step of forming a conductive material layer on a semiconductor substrate, a second step of forming a groove in an isolation region for defining the conductive material layer for each cell unit, and a third step of forming a first spacer on a sidewall of the groove And a fourth step of forming a first storage electrode pattern by performing an etching process using the first spacer as an etching mask and using the conductive material layer as an etching target. . 2. The method of claim 1, wherein polycrystalline silicon is used as a material constituting the conductive material layer and any one of an oxide film and a nitride film is used as a material constituting the first spacer. . 2. The highly integrated semiconductor device according to claim 1, further comprising, prior to the first step, a step of forming a planarization layer on the entire surface of the semiconductor substrate and a step of forming contact holes for partially exposing the source of the transistor to the surface. Capacitor manufacturing method. The method of claim 1, wherein a material constituting the planarization layer is formed of a material having an etch rate different from that of the conductive material layer with respect to anisotropic etching. The method of claim 4, wherein an oxide film is used as a material of the planarization layer. 4. The semiconductor device according to claim 3, further comprising, after the step of forming the planarization layer, a step of forming an etch stop layer on the entire surface of the resultant and a step of forming a spacer layer on the entire surface of the etch stop layer. Capacitor manufacturing method. The method of claim 6, wherein the material constituting the etch stop layer, an etch rate is different from the material constituting the spacer layer for anisotropic etching, the material constituting the spacer layer, The method of manufacturing a capacitor of a high-density semiconductor device, characterized in that for etching using a material having a different etching rate than the conductive material layer. 8. The method of claim 7, wherein an oxide film is used as a material constituting the planarization layer and a spacer layer, and a nitride film is used as a material constituting the food storage layer. The method of claim 8, wherein the etch stop layer has a thickness of about 30 kPa to about 300 kPa and the spacer layer is about 500 kPa to about 2,000 kPa. 7. The method of claim 6, wherein after the step of forming the contact hole, a step of laminating an etch-stop material consisting of a nitride film and a spacer material consisting of an oxide film on the entire surface of the resultant to have a constant thickness and anisotropically etching the laminated materials. And forming a second spacer on the sidewalls. The method of claim 1, wherein a material constituting the first spacer is formed of a material having an etch rate different from that of the conductive material layer for anisotropic etching. . 2. The method of claim 1, wherein the groove is formed to a depth such that the first spacer is well formed. 13. The method of claim 12, wherein the depth is in the range of about 500 mW to about 3000 mW. The method of claim 1, wherein the edge of the groove is formed at an angle of 90 degrees or less. The method of claim 12, wherein the depth of the groove is adjusted by adjusting an etching time. The method of claim 1, wherein an angle between the sidewall of the first storage electrode pattern and the surface of the planarization layer in the isolation region is greater than or equal to 90 °. 5. The method of claim 4, further comprising a step of partially removing the surface of the planarization layer after the fourth step. 7. The method of claim 6, further comprising, after the fourth step, removing the spacer layer. The method of claim 1, wherein after the fourth process, a photoresist pattern defined for each cell unit is formed on the resultant, and the etching process is performed using the etching mask as an etch mask. Capacitor manufacturing method of a highly integrated semiconductor device, characterized in that the separation. The method of claim 1, further comprising, after the fourth process, removing the first spacer, and before or after removing the first spacer, an etching process using the conductive material layer as an etching target. Thereby eliminating a fence formed of a conductive material layer that may be formed on an inner side wall of the first storage electrode pattern. The second storage electrode pattern of claim 1, wherein the second storage electrode pattern is formed by forming a third spacer on a sidewall of the first storage electrode pattern and an anisotropic etching process using the third spacer as an etch mask after the fourth process. A method for manufacturing a capacitor of a highly integrated semiconductor device, characterized by adding a forming step. 22. The capacitor manufacturing method of claim 21, wherein a material constituting the third spacer is made of a material having an etch rate different from that of the material constituting the conductive material layer for anisotropic etching. Way. 23. The method of claim 22, wherein any one of an oxide film and a nitride film is used as the material constituting the third spacer. 22. The highly integrated semiconductor as claimed in claim 21, wherein the forming of the storage electrode pattern is repeated once by forming a spacer on the sidewall of the second storage electrode pattern and performing an anisotropic etching process using the spacer as an etching mask. Method for manufacturing capacitors in the device. A first step of forming a conductive material layer on a semiconductor substrate, a second step of forming a pattern defined by the conductive material layer for each cell unit, a third step of forming a first spacer on the sidewall of the pattern, and a conductive material layer A fourth step of forming a groove in an isolation region for defining each cell unit by performing an etching process using the formed material layer as an etching mask and using the conductive material layer as an etching target, and a fifth step of removing the pattern And a sixth step of forming a first storage electrode pattern by performing an etching process using the second spacer as an etching mask and the conductive material layer as an etching target. 26. The method of claim 25, wherein the groove is formed on the sidewall of the groove to have a depth sufficient to form the first spacer. 27. The method of claim 26, wherein the depth is in the range of about 500 mW to about 3000 mW. 27. The method of claim 26, wherein the depth of the groove is adjusted by adjusting an etching time. 26. The method of claim 25, wherein an angle between the outer side wall of the first storage electrode pattern and the semiconductor substrate is greater than 90 degrees. 26. The method of claim 25, wherein the material constituting the pattern is used as a material capable of arbitrarily adjusting the sidewall inclination of the groove during the etching process for forming the groove. 31. The method of claim 30, wherein a photoresist baked with the material constituting the pattern is used. 32. The method of claim 31, wherein a material constituting the first spacer is a material capable of low temperature deposition so that the shape of the pattern is not broken. 33. The highly integrated semiconductor device of claim 32, wherein the material capable of low temperature deposition is any one of PE-TEOS (Plasma Enhanced-Tetra-Ethly-Ortho Silicate) and PE-Silain (Plasma Enhanced-Silain). Capacitor manufacturing method. 31. The method of claim 30, wherein silicon nitride is used as a material constituting the pattern. 26. The method of claim 25, wherein a material constituting the first spacer is formed of a material having an etch rate different from that of the conductive material layer for anisotropic etching. 36. The capacitor of claim 35, wherein polycrystalline silicon is used as a material constituting the conductive material layer and any one of an oxide film and a nitride film is used as the material constituting the first spacer. Manufacturing method. 27. The method of claim 25, wherein an angle between the sidewall of the pattern and the surface of the conductive material layer is less than 90 degrees. The method of claim 25, wherein after the sixth step, removing the first spacer, forming a second spacer on a sidewall of the first storage electrode pattern, and forming the second spacer as an etch mask. 1. A method for manufacturing a capacitor of a highly integrated semiconductor device, comprising: forming a second storage electrode pattern by performing an anisotropic etching process using the storage electrode pattern as an etching target. 39. The highly integrated semiconductor device of claim 38, wherein a material constituting the first and second spacers is formed of a material having an etch rate different from that of the conductive material layer for anisotropic etching. Capacitor manufacturing method. 40. The high integration material according to claim 39, wherein polycrystalline silicon is used as a material constituting the conductive material layer and any one of an oxide film and a nitride film is used as a material constituting the first and second spacers. Method for manufacturing capacitor of field conductor device. The method of claim 38, wherein after the forming of the second storage electrode pattern, removing the second spacer, forming a third spacer on sidewalls of the second storage electrode pattern, and etching the third spacer. A method of manufacturing a capacitor in a highly integrated semiconductor device, characterized in that the step of performing anisotropic etching with a mask is repeated one or more times. 26. The method of claim 25, wherein in the fourth step, the depth of the groove is equal to the thickness of the conductive material layer. 27. The method of claim 25, further comprising removing the pattern after the third step. A first process of forming a first conductive material layer on a semiconductor substrate, a second process of forming an etch stop layer on the first conductive material layer, a third process of forming a second conductive material layer on the etch stop layer, Forming a pattern by patterning the second conductive material layer in each cell unit; a fifth process of forming a spacer on the sidewall of the pattern; and etching the first conductive material layer using the pattern and the spacer as an etching mask. An anisotropic etching is performed on the object to form grooves in the isolation region for confining each cell unit, the seventh process of removing the pattern and the etch stop layer under the pattern, and the spacer as an etching mask. And an eighth step of performing an etching step using the first conductive material layer as an etching target. 45. The method of claim 44, wherein polycrystalline silicon is used as the material constituting the second and second conductive material layers. 45. The capacitor of claim 44, wherein a material constituting the etch stop layer is formed of a material having an etch rate different from that of the material constituting the second conductive material layer for dry etching. Manufacturing method. 47. The highly integrated semiconductor device as claimed in claim 46, wherein polycrystalline silicon is used as a material constituting said second conductive material layer and any one of silicon nitride and an oxide film is used as a material constituting said etch stop layer. Capacitor manufacturing method. 45. The highly integrated semiconductor device as claimed in claim 44, wherein a material constituting the spacer is made of a material having an etch rate different from a material constituting the first and second conductive material layers for anisotropic etching. Capacitor manufacturing method. 49. The method of claim 48, wherein one of a nitride film and an oxide film is used as the material constituting the spacer. 45. The method of claim 44, wherein an angle between the sidewall of the pattern and the etch stop layer is less than 90 degrees.