CN112542457B - Capacitor array structure and forming method thereof - Google Patents
Capacitor array structure and forming method thereof Download PDFInfo
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- CN112542457B CN112542457B CN201910898779.6A CN201910898779A CN112542457B CN 112542457 B CN112542457 B CN 112542457B CN 201910898779 A CN201910898779 A CN 201910898779A CN 112542457 B CN112542457 B CN 112542457B
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- 239000003990 capacitor Substances 0.000 title claims abstract description 138
- 238000000034 method Methods 0.000 title claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 238000003475 lamination Methods 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims description 17
- 238000000151 deposition Methods 0.000 claims description 5
- 238000005520 cutting process Methods 0.000 abstract description 9
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 230000009286 beneficial effect Effects 0.000 abstract 1
- 239000000463 material Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000005034 decoration Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to the technical field of semiconductor manufacturing, in particular to a capacitor array structure and a forming method thereof. The forming method of the capacitor array structure comprises the following steps: forming a base, wherein the base comprises a substrate, a lamination layer positioned on the surface of the substrate and capacitor holes which penetrate through the lamination layer and are arranged in an array manner, and the lamination layer comprises sacrificial layers and supporting layers which are alternately arranged; forming a hard mask layer on the surface of the substrate, wherein the hard mask layer is provided with a plurality of openings, each opening is overlapped with a plurality of capacitor holes, and the side lines of the openings for cutting the capacitor holes are equal in length or the overlapped areas of the openings and the capacitor holes are equal; and removing the sacrificial layer along the opening. The invention enlarges the process window, is beneficial to improving the opening precision, thereby realizing the simplification of the forming process of the capacitor array structure and reducing the manufacturing difficulty of the capacitor array structure.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a capacitor array structure and a forming method thereof.
Background
Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in electronic devices such as computers, and is composed of a plurality of Memory cells, each of which typically includes a transistor and a capacitor. The transistor has a gate electrically connected to a word line, a source electrically connected to a bit line, and a drain electrically connected to the capacitor, and a word line voltage on the word line can control the transistor to be turned on and off, so that data information stored in the capacitor can be read or written to the capacitor through the bit line.
In the formation process of the capacitor array structure, after the lower electrode layer is deposited, an opening is usually required to be formed so as to remove the sacrificial layer in the stack through the opening. Along with the continuous reduction of the capacitor size, the size of the opening is also continuously reduced, and the manufacturing difficulty of the capacitor array structure is increased. Therefore, how to simplify the formation process of the capacitor array structure and reduce the process difficulty is a technical problem to be solved at present.
Disclosure of Invention
The invention provides a capacitor array structure and a forming method thereof, which are used for solving the problems of complex forming process and higher difficulty of the conventional capacitor array structure.
In order to solve the above problems, the present invention provides a method for forming a capacitor array structure, comprising the steps of:
forming a base, wherein the base comprises a substrate, a lamination layer positioned on the surface of the substrate and capacitor holes which penetrate through the lamination layer and are arranged in an array manner, and the lamination layer comprises sacrificial layers and supporting layers which are arranged alternately;
forming a hard mask layer on the surface of the substrate, wherein the hard mask layer is provided with a plurality of openings, each opening is overlapped with a plurality of capacitor holes, and the side lines of the openings for cutting the capacitor holes are equal in length or the overlapping areas of the openings and the capacitor holes are equal;
and removing the sacrificial layer along the opening.
Optionally, the number of the capacitor holes overlapping a single opening is four.
Optionally, the specific steps of forming the substrate include:
providing a substrate;
alternately depositing a sacrificial layer and a supporting layer on the surface of the substrate to form a laminated layer;
forming a first capacitor mask layer on the surface of the lamination layer, wherein the first capacitor mask layer is provided with a first etching pattern extending along a first direction;
forming a second capacitance mask layer on the surface of the first capacitance mask layer, wherein the second capacitance mask layer is provided with a second etching pattern extending along a second direction, and the first direction is intersected with the second direction;
and etching the laminated layer by taking the first etching graph and the second etching graph as a capacitor hole graph to form the capacitor hole.
Optionally, the capacitor holes are arranged in a regular hexagonal pattern.
Optionally, the step of forming the hard mask layer on the substrate surface includes:
forming a hard mask layer covering the lamination layer and closing the capacitor hole on the surface of the substrate;
forming a photoresist layer on the surface of the hard mask layer, wherein the photoresist layer is provided with a plurality of initial openings for exposing the hard mask layer;
and etching the hard mask layer along the initial opening to form the opening.
Optionally, the initial opening is a rectangle, and a short side of the rectangle extends along the first direction, and a long side of the rectangle extends along a direction perpendicular to the first direction.
Optionally, the opening is oval, and a long axis direction of the oval opening is perpendicular to the first direction; the boundary in the opening major axis direction of the ellipse passes through the center of the capacitance hole overlapping therewith in a direction perpendicular to the base.
Optionally, the initial opening is a rectangle, and the rectangle is inclined by a preset angle relative to the first direction.
Optionally, the opening is an ellipse, and a long axis direction of the ellipse is inclined by the preset angle with respect to the first direction.
Optionally, the preset angle is 30 degrees.
In order to solve the above problems, the present invention further provides a capacitor array structure formed by any one of the above capacitor array structure forming methods.
According to the capacitor array structure and the forming method thereof, the opening for removing the sacrificial layer is overlapped with the plurality of capacitor holes, and the side line lengths of the opening for cutting the capacitor holes are equal or the overlapping areas of the opening and the capacitor holes are equal, so that a process window is enlarged, the opening precision is improved, the simplification of the forming process of the capacitor array structure is realized, and the manufacturing difficulty of the capacitor array structure is reduced.
Drawings
FIG. 1 is a method of forming a capacitor array structure according to a first embodiment of the present invention;
FIGS. 2A-2D are schematic diagrams of the main process structures of the first embodiment of the present invention in the process of forming the capacitor array structure;
fig. 3A-3F are schematic diagrams illustrating the main process structures of the second embodiment of the present invention in the process of forming the capacitor array structure.
Detailed Description
The following describes a capacitor array structure and a method for forming the same in detail with reference to the accompanying drawings.
First embodiment
Fig. 1 is a method for forming a capacitor array structure according to a first embodiment of the present invention, and fig. 2A to 2D are schematic diagrams of main process structures in a process of forming a capacitor array structure according to the first embodiment of the present invention. As shown in fig. 1 and fig. 2A to fig. 2D, the method for forming a capacitor array structure provided in this embodiment includes the following steps:
step S11, forming a base, wherein the base comprises a substrate, a lamination layer positioned on the surface of the substrate and capacitor holes 20 which penetrate through the lamination layer and are arranged in an array manner, and the lamination layer comprises a sacrificial layer and a supporting layer which are alternately arranged. By way of example, the shape of the capacitor hole 20 is not limited, and may be a circle, a regular polygon, a trapezoid, etc., and the embodiment is described by taking a circle as an example.
Optionally, the specific steps of forming the substrate include:
providing a substrate;
alternately depositing a sacrificial layer and a supporting layer on the surface of the substrate to form a laminated layer;
forming a first capacitor mask layer on the surface of the lamination layer, wherein the first capacitor mask layer is provided with a first etching pattern extending along a first direction;
forming a second capacitance mask layer on the surface of the first capacitance mask layer, wherein the second capacitance mask layer is provided with a second etching pattern extending along a second direction, and the first direction is intersected with the second direction;
and etching the laminated layer by taking the first etching graph and the second etching graph as a capacitor hole graph to form the capacitor hole.
Specifically, in the specific embodiment, the capacitor hole is formed by using a pitch multiplication process, and etching the stack layer by using the first etching pattern and the second etching pattern as the capacitor hole pattern together means etching the stack layer by using a projection overlapping area of the first etching pattern and the second etching pattern as the capacitor hole pattern. The first direction and the second direction may intersect perpendicularly or obliquely, for example: the P1 direction in fig. 2A is the first direction, and the P2 direction is the second direction. The material of the sacrificial layer may be a polysilicon material, a borophosphosilicate Glass (BPSG) material, or silicon dioxide, and the material of the support layer may be a nitride material (e.g., silicon nitride). The number of the sacrificial layers and the support layers stacked alternately can be determined by those skilled in the art according to actual needs.
In order to increase the arrangement density of the capacitance holes, optionally, the capacitance holes are arranged in a regular hexagonal shape, as shown in fig. 2A.
Step S12, forming a hard mask layer on the substrate surface, where the hard mask layer has a plurality of openings 22, each opening 22 overlaps with a plurality of capacitor holes 20, and the edge lengths of the openings 22 cutting the capacitor holes 20 are all equal or the overlapping areas of the openings 22 and the capacitor holes 20 are all equal.
Alternatively, the number of the capacitor holes overlapping the single opening is four, as shown in fig. 2D. As an example, the number of the capacitor holes overlapping a single one of the openings may also be larger than 4, for example, may be 5, 6, 7, 8, 9, etc.
Specifically, the equal lengths of the side lines of the opening 22 cutting the four capacitor holes 20 mean that the equal lengths of the side lines of the projection of the opening 22 and the projection of the four capacitor holes 20 overlapped with the opening 22 in the direction perpendicular to the substrate. The overlapping areas of the opening 22 and the four capacitor holes 20 are equal, which means that the overlapping areas of the projection of the opening 22 and the projection of the four capacitor holes 20 overlapping with the opening are equal in area in the direction perpendicular to the substrate.
Optionally, the step of forming a hard mask layer on the substrate surface includes:
forming a hard mask layer covering the stack and closing the capacitor holes 20 on the substrate surface;
forming a photoresist layer 23 on the surface of the hard mask layer, wherein the photoresist layer 23 has a plurality of initial openings 21 exposing the hard mask layer, as shown in fig. 2C;
the hard mask layer is etched along the initial opening 21 to form the opening 22, as shown in fig. 2D.
Optionally, the initial opening 21 is rectangular, and a short side of the rectangle extends along the first direction, and a long side of the rectangle extends along a direction perpendicular to the first direction.
Optionally, the opening 22 is an ellipse, and a long axis direction of the ellipse is perpendicular to the first direction; the boundary in the opening major axis direction of the ellipse passes through the center of the capacitance hole overlapping therewith in a direction perpendicular to the base.
Specifically, fig. 2A shows a layout of 6 minimum repeating units 21a, and fig. 2B is an enlarged view of 1 minimum repeating unit 21a in fig. 2A. As shown in fig. 2B and 2C, when the initial opening 21 having a rectangular shape is formed on the photoresist layer 23, the initial opening 21 having a rectangular shape covers at least the centers of the four capacitor holes 201, 202, 203, and 204 overlapping with the opening 22 corresponding to the initial opening 21. Thus, the size of the initial opening 21 in the photoresist layer is increased, the photoetching process window is further increased, and meanwhile, the adjustment space is increased for the size of the subsequently formed opening. The long side direction of the rectangular initial opening 21 is perpendicular to the P1 direction, and the short side direction is parallel to the P1 direction, that is, the projections of the two long sides of the rectangular initial opening 21 in the direction perpendicular to the substrate are respectively located on the centers of the capacitor holes 201 and 203 or on the periphery of the central connecting line of the capacitor holes 201 and 203; the projection of the short side of the rectangular initial opening 21 in the direction perpendicular to the substrate passes through the short sides arranged in the direction parallel to the P1 and respectively located at the centers of the capacitor holes 202 and 204 or at the periphery of the connecting line of the centers of the capacitor holes 202 and 204. After the initial opening 21 shown in fig. 2C is formed in the photoresist layer 23, the hard mask layer is etched down along the initial opening 21, so that the opening 22 having an elliptical shape shown in fig. 2D is formed in the hard mask layer, and a boundary in a long axis direction of the opening having an elliptical shape passes through a center of the capacitor hole overlapping therewith in a direction perpendicular to the substrate.
In the present embodiment, as shown in fig. 2B, by controlling the shape of the initial opening 21 in the photoresist layer 23, the overlapping area of the finally formed elliptical opening 22 and four adjacent capacitor holes (i.e. the first overlapping area a of the first capacitor hole 201, the second overlapping area B of the second capacitor hole 202, the third overlapping area C of the third capacitor hole 203, and the fourth overlapping area D of the fourth capacitor hole 204) can be equal, i.e. the area of the opening 22 and four capacitor holes overlapping therewith are equal, which helps to further improve the accuracy of the opening 22 and improve the formation process of the capacitor array structure.
In other embodiments, a person skilled in the art may also adjust the shape and size of the initial opening 21 in the photoresist layer 23, so that the lengths of the side lines of the finally formed elliptical opening 22 that intersect the four capacitor holes (i.e., the lengths of the side lines of the opening 22 that intersect the first capacitor hole 201, the second capacitor hole 202, the third capacitor hole 203, and the fourth capacitor hole 204) are all equal.
Step S13, removing the sacrificial layer along the opening 22.
Specifically, an etching solution is injected from the opening to remove the sacrificial layer. After the removal process of the sacrificial layer is completed, the hard mask layer is removed by ashing to perform a subsequent capacitance manufacturing process, such as deposition of a dielectric layer, an upper electrode layer, and the like.
Furthermore, the present embodiment provides a capacitor array structure formed by any one of the above capacitor array structure forming methods.
The capacitor array structure and the forming method thereof provided by the present specific embodiment enable the opening for removing the sacrificial layer to overlap with the plurality of capacitor holes, and the side line lengths of the opening cutting the capacitor holes are equal or the overlapping areas of the opening and the capacitor holes are equal, thereby increasing the process window, facilitating the improvement of the opening precision, simplifying the forming process of the capacitor array structure, and reducing the manufacturing difficulty of the capacitor array structure.
Second embodiment
The present embodiment provides a method for forming a capacitor array structure, and fig. 3A to 3F are schematic views of main process structures in a process of forming a capacitor array structure according to a second embodiment of the present invention. The same parts as those in the first embodiment will not be described again, and the differences from the first embodiment will be mainly described below.
The method for forming a capacitor array structure provided by the present embodiment includes the following steps:
step S21, forming a base, wherein the base comprises a substrate, a lamination layer positioned on the surface of the substrate and capacitor holes 30 which penetrate through the lamination layer and are arranged in an array manner, and the lamination layer comprises sacrificial layers and supporting layers which are alternately arranged; by way of example, the shape of the capacitor hole 20 is not limited, and may be a circle, a regular polygon, a trapezoid, etc., and the embodiment is described by taking a circle as an example.
Step S22, forming a hard mask layer on the substrate surface, where the hard mask layer has a plurality of openings, each opening 32 overlaps with a plurality of capacitor holes 30, and the lengths of the side lines of the openings 32 cutting the capacitor holes 30 are equal or the overlapping areas of the openings 32 and the capacitor holes 30 are equal, as shown in fig. 3D;
step S23, removing the sacrificial layer along the opening 32.
Optionally, the number of the capacitor holes overlapping with a single opening is four, as shown in fig. 3B and 3D. As an example, the number of the capacitive apertures overlapping a single one of the openings may be greater than 4, for example, 5, 6, 7, 8, 9, etc.
Optionally, the specific steps of forming the substrate include:
providing a substrate;
alternately depositing a sacrificial layer and a supporting layer on the surface of the substrate to form a laminated layer;
forming a first capacitor mask layer on the surface of the laminated layer, wherein the first capacitor mask layer is provided with a first etching pattern extending along a first direction;
forming a second capacitance mask layer on the surface of the first capacitance mask layer, wherein the second capacitance mask layer is provided with a second etching pattern extending along a second direction, and the first direction is intersected with the second direction;
and etching the laminated layer by taking the first etching graph and the second etching graph as a capacitor hole graph to form the capacitor hole.
Optionally, the capacitor holes 30 are arranged in a regular hexagonal pattern.
Optionally, the step of forming a hard mask layer on the substrate surface includes:
forming a hard mask layer covering the stack and closing the capacitor hole 30 on the substrate surface;
forming a photoresist layer 33 on the surface of the hard mask layer, wherein the photoresist layer has a plurality of initial openings 31 exposing the hard mask layer, as shown in fig. 3C;
the hard mask layer is etched along the initial opening 31 to form the opening 32.
Optionally, the initial opening 31 is a rectangle, and the rectangle is inclined by a preset angle with respect to the first direction;
the projection of the rectangle in a direction perpendicular to the substrate covers four of the capacitor holes 30.
Optionally, the opening 32 is an oval shape, and a long axis direction of the oval opening 32 is inclined by the preset angle with respect to the first direction.
In order to adapt to the hexagonal array arrangement of the capacitor holes in the semiconductor memory, the preset angle is optionally 30 degrees.
Specifically, a layout of 5 minimal repeating units 31a is shown in fig. 3A, and fig. 3B is an enlarged view of 1 minimal repeating unit 31a in fig. 3A. As shown in fig. 3C, when the initial opening 31 having a rectangular shape is formed on the photoresist layer 33, a projection of the rectangular initial opening 31 in a direction perpendicular to the substrate at least covers centers of four capacitor holes, for example, a projection of one initial opening 31 in fig. 3B in a direction perpendicular to the substrate at least covers centers of a first capacitor hole 301, a second capacitor hole 302, a third capacitor hole 303 and a fourth capacitor hole 304. The initial opening 31 is inclined by a predetermined angle γ with respect to the P1 direction. After the initial opening 31 shown in fig. 3A and 3B is formed in the photoresist layer 33, the hard mask layer is etched down along the initial opening 31, so that the oval opening 32 shown in fig. 3D is formed in the hard mask layer.
As shown in fig. 3B, by controlling the shape of the initial opening 31 in the photoresist layer 33, the overlapping areas of the finally formed elliptical opening 32 and four adjacent capacitor holes (i.e. the first overlapping area a of the first capacitor hole 301, the second overlapping area B of the second capacitor hole 302, the third overlapping area C of the third capacitor hole 303 and the fourth overlapping area D of the fourth capacitor hole 304) are all equal, i.e. the areas of the four capacitor holes overlapped by the opening 32 are all equal.
In other embodiments, a person skilled in the art may also adjust the shape and size of the initial opening 31 in the photoresist layer 33, so that the side lengths of the finally formed elliptical opening 32 cutting the four capacitor holes overlapped therewith (i.e., the side lengths of the opening 32 cutting the first capacitor hole 301, the second capacitor hole 302, the third capacitor hole 303 and the fourth capacitor hole 304) are all equal.
Fig. 3A to 3D show that the opening 31 is inclined to the left side by a predetermined angle with respect to the P1 direction. In other embodiments, one skilled in the art may also form the opening 31 inclined to the right side with respect to the P1 direction by a predetermined angle as shown in fig. 3E and 3F according to actual needs, and the forming method is similar to the method shown in fig. 3A to 3D.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A method for forming a capacitor array structure is characterized by comprising the following steps:
forming a base, wherein the base comprises a substrate, a lamination layer positioned on the surface of the substrate and capacitor holes which penetrate through the lamination layer and are arranged in an array manner, and the lamination layer comprises sacrificial layers and supporting layers which are arranged alternately; forming a hard mask layer on the surface of the substrate, wherein the hard mask layer is provided with a plurality of openings, each opening is overlapped with more than four capacitor holes, the openings are oval, the boundary of the oval in the long axis direction of the openings passes through the centers of the capacitor holes overlapped with the openings in the direction perpendicular to the substrate, and the overlapped areas of the openings and the capacitor holes are equal;
and removing the sacrificial layer along the opening.
2. The method of claim 1, wherein the step of forming the substrate comprises:
providing a substrate;
alternately depositing a sacrificial layer and a supporting layer on the surface of the substrate to form a laminated layer;
forming a first capacitor mask layer on the surface of the laminated layer, wherein the first capacitor mask layer is provided with a first etching pattern extending along a first direction;
forming a second capacitance mask layer on the surface of the first capacitance mask layer, wherein the second capacitance mask layer is provided with a second etching pattern extending along a second direction, and the first direction is intersected with the second direction; and etching the laminated layer by taking the first etching pattern and the second etching pattern as a capacitor hole pattern together to form the capacitor hole.
3. The method as claimed in claim 2, wherein the capacitor holes are arranged in a regular hexagonal pattern.
4. The method as claimed in claim 3, wherein the step of forming a hard mask layer on the substrate surface comprises:
forming a hard mask layer covering the lamination layer and closing the capacitor hole on the surface of the substrate;
forming a photoresist layer on the surface of the hard mask layer, wherein the photoresist layer is provided with a plurality of initial openings for exposing the hard mask layer;
and etching the hard mask layer along the initial opening to form the opening.
5. The method as claimed in claim 4, wherein the initial opening is a rectangle, and a short side of the rectangle extends along the first direction and a long side of the rectangle extends along a direction perpendicular to the first direction.
6. The method as claimed in claim 5, wherein a major axis direction of the oval is perpendicular to the first direction.
7. The method as claimed in claim 4, wherein the initial opening is a rectangle, and the rectangle is inclined with respect to the first direction by a predetermined angle.
8. The method of claim 7, wherein a major axis direction of the elliptical opening is inclined by the predetermined angle with respect to the first direction.
9. The method as claimed in claim 7, wherein the predetermined angle is 30 degrees.
10. A capacitor array structure formed by the method of any one of claims 1 to 9.
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| KR20140028751A (en) * | 2012-08-30 | 2014-03-10 | 에스케이하이닉스 주식회사 | Method for manufacturing semiconductor device with node array |
| CN107706206A (en) * | 2017-11-02 | 2018-02-16 | 睿力集成电路有限公司 | Array of capacitors and forming method thereof, semiconductor devices |
| CN108010913A (en) * | 2017-12-29 | 2018-05-08 | 睿力集成电路有限公司 | Organization of semiconductor memory and preparation method thereof |
| CN108155185A (en) * | 2016-12-02 | 2018-06-12 | 三星电子株式会社 | Semiconductor devices including supporting pattern |
| CN208637425U (en) * | 2018-06-22 | 2019-03-22 | 长鑫存储技术有限公司 | Preparation laminated structure of semiconductor memory capacitor hole |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR102656866B1 (en) * | 2017-01-24 | 2024-04-11 | 삼성전자주식회사 | Semiconductor device |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140028751A (en) * | 2012-08-30 | 2014-03-10 | 에스케이하이닉스 주식회사 | Method for manufacturing semiconductor device with node array |
| CN108155185A (en) * | 2016-12-02 | 2018-06-12 | 三星电子株式会社 | Semiconductor devices including supporting pattern |
| CN107706206A (en) * | 2017-11-02 | 2018-02-16 | 睿力集成电路有限公司 | Array of capacitors and forming method thereof, semiconductor devices |
| CN108010913A (en) * | 2017-12-29 | 2018-05-08 | 睿力集成电路有限公司 | Organization of semiconductor memory and preparation method thereof |
| CN208637425U (en) * | 2018-06-22 | 2019-03-22 | 长鑫存储技术有限公司 | Preparation laminated structure of semiconductor memory capacitor hole |
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