CN208580747U - The IGBT device of the double clamps of grid - Google Patents
The IGBT device of the double clamps of grid Download PDFInfo
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- CN208580747U CN208580747U CN201821456297.2U CN201821456297U CN208580747U CN 208580747 U CN208580747 U CN 208580747U CN 201821456297 U CN201821456297 U CN 201821456297U CN 208580747 U CN208580747 U CN 208580747U
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Abstract
The utility model relates to a kind of IGBT devices of the double clamps of grid, it includes the grid voltage clamp structure being set in gate electrode area, and the grid voltage clamp structure includes third doped region, the second doped region in the third doped region and the first doped region positioned at second doped region immediately below gate metal layer；First doped region is located in the first conduction type drift region, and the doping type of the first doped region is consistent with the doping type of third doped region, and the doping type of the first doped region is different from the doping type of the second doped region；First doped region and gate metal layer Ohmic contact, third doped region and emitter metal Ohmic contact.The utility model is compact-sized, reduces the gate electrode of IGBT device by the influence of the excessively high spike of positive minus gate voltage, avoid the occurrence of grid voltage it is excessively high when short circuit current increased dramatically and lead to burning for IGBT device, securely and reliably.
Description
Technical field
The utility model relates to a kind of IGBT device, the IGBT device of the double clamps of especially a kind of grid belongs to IGBT device
The technical field of part.
Background technique
Insulated gate bipolar transistor (IGBT) is a kind of MOS field-effect and the compound power electronics device of bipolar junction transistor
Part；It had not only had the advantages that MOSFET was easy to drive, control is simple, switching frequency is high, but also had the conduction voltage drop of power transistor
Ground, on the same stage electric current are beaten, small advantage are lost.In view of these advantages of IGBT, current advanced power electronic equipment is become
It is main to select switching device, it is widely used in the states such as communication, the energy, traffic, industry, medicine, household electrical appliance and space flight and aviation
The every field of people's economy, the application of IGBT play the role of the promotion of system performance vital.
IGBT experienced by development in recent years from punch insulated gate bipolar transistor (PT-IGBT) to non-
Punch insulated gate bipolar transistor (NPT-IGBT), then arrive electric field stop type insulated gate bipolar transistor (FS-IGBT)
Variation, also experienced the development from planar structure to groove structure.Nowadays IGBT structure is more complicated towards structure, finer
Development.Igbt chip is integrated with more more complicated structures, such as is integrated with the IGBT of current measurement function, and current collection may be implemented
Electrode current measurement.Junction temperature measurement may be implemented in the IGBT for being integrated with temperature measurement function.
Nowadays the application surface of IGBT is more and more wider, and application environment is more complicated and changeable, mutual dry between circuit between device
Disturb a significant concern point for becoming device design application.In practical application circuit, IGBT grid can be generated when circuit works
On the one hand the presence of the positive undershoot of grid voltage, spike may make IGBT grid cause irreversible damage, on the other hand such as fruit point
Peak appears in IGBT short-circuit process, will cause increased dramatically for collector short circuit current, eventually leads to device and is burned out.
Summary of the invention
The purpose of the utility model is to overcome the deficiencies in the prior art, provide a kind of IGBT device of double clamps of grid
Part, it is compact-sized, reduce the gate electrode of IGBT device by the influence of the excessively high spike of positive minus gate voltage, avoid the occurrence of grid voltage it is excessively high when
Short circuit current increased dramatically and lead to burning for IGBT device, securely and reliably.
According to technical solution provided by the utility model, the IGBT device of the double clamps of the grid, including semiconductor substrate
And the cellular region positioned at the semiconductor substrate center；The cellular region includes emitter region and gate electrode area；Semiconductor
Substrate includes the first conduction type drift region, and the emitter region includes emitter metal layer, and gate electrode area includes gate metal
Layer；
It further include the grid voltage clamp structure being set in gate electrode area, the grid voltage clamp structure includes being located at
Third doped region immediately below gate metal layer, the second doped region in the third doped region and be located at described second
First doped region of doped region；First doped region is located in the first conduction type drift region, the doping type of the first doped region with
The doping type of third doped region is consistent, and the doping type of the first doped region is different from the doping type of the second doped region；
First doped region and gate metal layer Ohmic contact, third doped region and emitter metal layer Ohmic contact.
The gate metal layer is adulterated by gate insulator dielectric layer and the first doped region, the second doped region and third
Area.
The emitter region further includes the second conduction type base region for being set to the first conduction type drift region internal upper part,
Cellular groove is set in second conduction type base region, the slot bottom of cellular groove is located at the lower section of the second conduction type base region,
Side wall and the bottom wall growth of cellular groove have gate oxide, more filled with grid in the cellular groove that growth has gate oxide
Crystal silicon, the grid polycrystalline silicon by the emitter insulating medium layer of gland cellular groove notch and emitter metal layer insulate every
From the grid polycrystalline silicon and gate metal layer Ohmic contact；
First conduction type source region, the second conduction type source region and cellular ditch are set in the second conduction type base region
The lateral wall on slot top contacts, emitter metal layer and the second conduction type base region, the first conduction type source region Ohmic contact.
Terminal protection area is also set up in the outer ring of cellular region, and the terminal protection area includes terminal metal and is located at institute
State the terminal knot immediately below terminal metal, the terminal metal and terminal knot Ohmic contact.
The terminal protection area further includes terminating insulation dielectric layer, and terminal metal is supported on terminating insulation dielectric layer,
Terminal metal passes through terminal media contact hole and terminal knot Ohmic contact in terminating insulation dielectric layer.
It also sets up the first conduction type field cutoff layer at the back side of the semiconductor substrate and is set to described first and lead
The second conduction type collecting zone on the cutoff layer of electric type field, the first conduction type field cutoff layer are located at the drift of the first conduction type
Between area and the second conduction type collecting zone, and the first conduction type field cutoff layer respectively with the first conduction type drift region,
Two conduction type collecting zones are adjacent；Collector electrode metal layer, the collector electrode metal layer are set on the second conduction type collecting zone
With the second conduction type collecting zone Ohmic contact.
It is conductive for N-type power IGBT device, first in " first conduction type " and " the second conduction type " the two
Type refers to N-type, and the second conduction type is p-type；For p-type power IGBT device, the first conduction type and the second conduction type institute
The type of finger and N-type semiconductor device are exactly the opposite.
The advantages of the utility model: the first doped region, the second doped region and the are set in the underface of gate metal layer
Three doped regions, the first doped region and emitter metal layer Ohmic contact, third doped region and emitter metal layer Ohmic contact, from
And utilize the first doped region, the second doped region and third doped region can be in shape between the emission electrode, gate electrode of IGBT device
It is in pairs that the impact of positive minus gate voltage can be protected from using grid voltage clamp structure to TVS structure, protect the grid of IGBT device
Electrode can also avoid occurring higher short circuit current when grid voltage is excessively high, IGBT device is avoided to lead since short circuit current is excessive
The damage of cause increases the robustness of IGBT device, reduces the dependence to gate driving, effectively improves the integrated level of device, safety
Reliably.
Detailed description of the invention
Fig. 1 is the schematic diagram of the front domain of the utility model.
Fig. 2 is the cross-sectional view of the utility model.
Fig. 3 is the equivalent schematic diagram of the utility model.
Description of symbols: 1- emitter region, the gate electrode area 2-, 3- terminal protection area, 4- emitter metal floor, 5- grid
Metal layer, 6- terminal metal, 7-N type drift region, 8- emitter insulating medium layer, 9-P type base area, 10-N+ source region, 11- grid
Pole polysilicon, 12- gate oxide, 13- third doped region, the second doped region of 14-, the first doped region of 15-, 16- terminating insulation are situated between
Matter layer, 17- terminal knot, 18-N type field cutoff layer, 19-P+ collecting zone, 21-IGBT device, 22- gate electrode, 23- collector, 24-
Emission electrode, 25- grid voltage clamp structure and 26- gate insulator dielectric layer.
Specific embodiment
Below with reference to specific drawings and examples, the utility model is described in further detail.
It is as shown in Figure 1, Figure 2 and Figure 3: in order to reduce the gate electrode 22 of IGBT device 21 by the excessively high spike of positive minus gate voltage
Influence, avoid the occurrence of grid voltage it is excessively high when short circuit current increased dramatically and lead to burning for IGBT device 21, with N-type IGBT device 21
For, the utility model includes semiconductor substrate and the cellular region positioned at the semiconductor substrate center；The cellular region packet
Include emitter region 1 and gate electrode area 2；Semiconductor substrate includes N-type drift region 7, and the emitter region 1 includes emitter metal
Layer 4, gate electrode area 2 include gate metal layer 5；
It further include the grid voltage clamp structure 25 being set in gate electrode area 2, the grid voltage clamp structure 25 wraps
Include the third doped region 13 being located at immediately below gate metal layer 5, in the third doped region 13 the second doped region 14 with
And the first doped region 15 positioned at second doped region 14；First doped region 15 is located in N-type drift region 7, the first doped region
15 doping type is consistent with the doping type of third doped region 13, the doping type and the second doped region of the first doped region 15
14 doping type is different；
First doped region 15 and 5 Ohmic contact of gate metal layer, third doped region 13 connect with 4 ohm of emitter metal layer
Touching.
Specifically, semiconductor substrate can use existing common semiconductor material, such as silicon, silicon carbide, specifically can be with
Selection determination is carried out as needed, details are not described herein again.Cellular region is located at the center of semiconductor substrate, and cellular region includes several members
Born of the same parents, cellular in cellular region simultaneously join together.Cellular region includes emitter region 1 and gate electrode area 2, passes through 2 energy of emitter region
The emission electrode 24 for forming IGBT device 21, can form the gate electrode 22 of IGBT device 21 by gate electrode area 2.Semiconductor substrate
Including N-type drift region 7, emitter metal layer 4, gate metal layer 5 are located at the top of N-type drift region 7.
In the utility model embodiment, grid voltage clamp structure 25 include the first doped region 15, the second doped region 14 with
And third doped region 13, the first doped region 15 are located in N-type drift region 7, the second doped region 14 is located in the first doped region 15, i.e.,
Second doped region 14 is wrapped up by the first doped region 15, and third doped region 13 is located in the second doped region 14, the first doped region 15 with
The doping type having the same of third doped region 13, and the second doped region 14 and the first doped region 15, third doped region 13 are mixed
Miscellany type is opposite.First doped region 15 and 5 Ohmic contact of gate metal layer, third doped region 13 connect with 4 ohm of emitter metal
Touching, certainly, the first doped region 15 can also be with 4 Ohmic contact of emitter metal layer, then third doped region 13 and gate metal layers 5
Ohmic contact, specific connection, which can according to need, to be selected, and details are not described herein again.
When the doping type of the first doped region 15, third doped region 13 is p-type, the doping type of the second doped region 14 is
It is as shown in Figure 3 then to obtain grid voltage clamp structure 25 for N-type.
Further, the gate metal layer 5 passes through gate insulator dielectric layer 26 and the first doped region 15, the second doped region
14 and third doped region 13.In the utility model embodiment, gate insulator dielectric layer 26 is supported on the front of N-type drift region 7,
Gate insulator dielectric layer 26 can use existing common insulating materials, when gate metal layer 5 connects for 15 ohm with the first doped region
It when touching, generally requires and contact hole is set in gate insulator dielectric layer 26, gate metal layer 5 passes through contact hole and the first doped region
15 Ohmic contacts, the mode for implementing gate metal layer 5 and 13 Ohmic contact of the first doped region 15 or third doped region can be with
It is selected as needed, specially known to those skilled in the art, details are not described herein again.
Further, the emitter region 1 further includes the p-type base area 9 for being set to 7 internal upper part of N-type drift region, in the P
Cellular groove is set in type base area 9, and the slot bottom of cellular groove is located at the lower section of p-type base area 9, the side wall and bottom wall of cellular groove
Growth has gate oxide 12, and filled with grid polycrystalline silicon 11 in the cellular groove that growth has gate oxide 12, the grid is more
Crystal silicon 11 is dielectrically separated from by the emitter insulating medium layer 8 of gland cellular groove notch with emitter metal layer 4, the grid
Polysilicon 11 and 5 Ohmic contact of gate metal layer；
N+ source region 10 is set in p-type base area 9, and the N+ source region 10 is contacted with the lateral wall on cellular groove top, is emitted
Pole metal layer 4 and p-type base area 9,10 Ohmic contact of N+ source region.
In the utility model embodiment, p-type base area 9 is located at the top in N-type drift region 7, and the depth of p-type base area 9 is less than N
The thickness of type drift region 7, cellular groove are arranged in p-type base area 9, and the slot bottom of cellular groove is located at the lower section of p-type base area 9, member
Thickness of the depth of born of the same parents' groove again smaller than N-type drift region 7.P-type base area 9 and the first doped region 15, the second doped region 14 and
It is not in contact with each other between three doped regions 13.Gate oxide 12 covers the side wall and bottom wall of cellular groove, and grid polycrystalline silicon 11 is filled
In cellular groove, grid polycrystalline silicon 11 is dielectrically separated from by gate oxide 12 and the side wall and bottom wall of cellular groove.Cellular
The notch of groove is covered by emitter insulating medium layer 8, and emitter metal layer 4 is more by emitter insulating medium layer 8 and grid
Crystal silicon 11 is dielectrically separated from, grid polycrystalline silicon 11 and 5 Ohmic contact of gate metal layer pass through grid polycrystalline silicon 11, cellular groove
Cooperate with gate metal layer 5, trench gate IGBT device 21 can be formed, certainly, IGBT device 21 can also use planarized structure,
It specifically can according to need and selected, details are not described herein again.
N+ source region 10 is located in p-type base area 9, and N+ source region 10 is contacted with the lateral wall of cellular groove, emitter metal layer 4 with
P-type base area 9,10 Ohmic contact of N+ source region, so as to form the emission electrode 24 of IGBT device 21.
Further, terminal protection area 3 is also set up in the outer ring of cellular region, the terminal protection area 3 includes terminal metal
Layer 6 and the terminal knot 17 immediately below the terminal metal 6, the terminal metal 6 and 17 Ohmic contact of terminal knot.
In the utility model embodiment, terminal protection area 3, can be to cellular using terminal protection area 3 around cellular region is surrounded
Area is protected, between cellular region, terminal protection area 3 it is specific effect etc. with it is existing consistent, details are not described herein again.Terminal gold
Belonging to layer 6 and gate metal layer 5, emitter metal layer 4 is same processing step layer, and to N-type IGBT device 21, terminal knot 17 is P
Type doped region.
The terminal protection area 3 further includes terminating insulation dielectric layer 16, and terminal metal 6 is supported on terminating insulation dielectric layer
On 17, terminal metal 6 passes through terminal media contact hole and 17 Ohmic contact of terminal knot in terminating insulation dielectric layer 16.This reality
With in new embodiment, terminating insulation dielectric layer 16 and gate insulator dielectric layer 26, emitter insulating medium layer 8 are same technique
Terminal media contact hole is arranged, in terminating insulation dielectric layer 16 so as to ohm of terminal metal 6 and terminal knot 17 in step layer
Contact.When it is implemented, after terminal metal 6,17 Ohmic contact of terminal knot, mechanism, effect of played terminal protection etc. with
Existing consistent, details are not described herein again.
Further, N-type field cutoff layer 18 is also set up at the back side of the semiconductor substrate and be set to the N-type field
P+ collecting zone 19 on cutoff layer 18, N-type field cutoff layer 18 is between N-type drift region 7 and P+ collecting zone 19, and N-type field is cut
Only layer 18 is adjacent with N-type drift region 7, P+ collecting zone 19 respectively；Collector electrode metal layer 20, the collection are set on P+ collecting zone 19
Electrode metal layer 20 and 19 Ohmic contact of P+ collecting zone.
In the utility model embodiment, the doping concentration of N-type field cutoff layer 18 is greater than the doping concentration of N-type drift region 7, P+
Collecting zone 19 and N-type field cutoff layer 18 are adjacent, using the Ohmic contact of collector electrode metal layer 20 and P+ collecting zone 19, can be formed
The collector 23 of IGBT device 21.
The first doped region 15, the second doped region 14 and third is arranged in the underface of gate metal layer 5 in the utility model
Doped region 13, the first doped region 15 and 5 Ohmic contact of emitter metal layer, third doped region 13 with 4 ohm of emitter metal layer
Contact, thus can be in the transmitting electricity of IGBT device 21 using the first doped region 15, the second doped region 14 and third doped region 15
Two-way TVS structure is formed between pole 24, gate electrode 21, is realized the effect of two-way clamp, that is, is utilized grid voltage clamp structure 25
It can be protected from the impact of positive minus gate voltage, the gate electrode 21 of IGBT device 21 is protected, the appearance when grid voltage is excessively high can also be avoided
Higher short circuit current avoids IGBT device 21 due to the excessive caused damage of short circuit current, increases the robust of IGBT device 21
Property, the dependence to gate driving is reduced, effectively improves the integrated level of device, securely and reliably.
Claims (6)
1. a kind of IGBT device of the double clamps of grid, the cellular including semiconductor substrate and positioned at the semiconductor substrate center
Area；The cellular region includes emitter region and gate electrode area；Semiconductor substrate includes the first conduction type drift region, the hair
Emitter region includes emitter metal layer, and gate electrode area includes gate metal layer；It is characterized in that:
It further include the grid voltage clamp structure being set in gate electrode area, the grid voltage clamp structure includes being located at grid
Third doped region immediately below metal layer, the second doped region in the third doped region and be located at it is described second doping
First doped region in area；First doped region is located in the first conduction type drift region, the doping type and third of the first doped region
The doping type of doped region is consistent, and the doping type of the first doped region is different from the doping type of the second doped region；
First doped region and gate metal layer Ohmic contact, third doped region and emitter metal layer Ohmic contact.
2. the IGBT device of the double clamps of grid according to claim 1, it is characterized in that: the gate metal layer passes through grid
Insulating medium layer and the first doped region, the second doped region and third doped region.
3. the IGBT device of the double clamps of grid according to claim 1, it is characterized in that: the emitter region further includes setting
In the second conduction type base region of the first conduction type drift region internal upper part, cellular is set in second conduction type base region
Groove, the slot bottom of cellular groove are located at the lower section of the second conduction type base region, and side wall and the bottom wall growth of cellular groove have grid
Oxide layer, filled with grid polycrystalline silicon in the cellular groove that growth has gate oxide, the grid polycrystalline silicon passes through gland member
The emitter insulating medium layer of born of the same parents' groove notch is dielectrically separated from emitter metal layer, the grid polycrystalline silicon and gate metal layer
Ohmic contact；
First conduction type source region is set in the second conduction type base region, in the second conduction type source region and cellular groove
The lateral wall in portion contacts, emitter metal layer and the second conduction type base region, the first conduction type source region Ohmic contact.
4. the IGBT device of the double clamps of grid according to claim 1, it is characterized in that: the outer ring in cellular region also sets up end
Protection zone is held, the terminal protection area includes terminal metal and the terminal knot immediately below the terminal metal, institute
State terminal metal and terminal knot Ohmic contact.
5. the IGBT device of the double clamps of grid according to claim 4, it is characterized in that: the terminal protection area further includes end
Insulating medium layer is held, terminal metal is supported on terminating insulation dielectric layer, and terminal metal passes through in terminating insulation dielectric layer
Terminal media contact hole and terminal knot Ohmic contact.
6. the IGBT device of the double clamps of grid according to claim 1, it is characterized in that: at the back side of the semiconductor substrate
The second conduction type for also setting up the first conduction type field cutoff layer and being set on the cutoff layer of first conduction type field
Collecting zone, the first conduction type field cutoff layer between the first conduction type drift region and the second conduction type collecting zone, and
First conduction type field cutoff layer is adjacent with the first conduction type drift region, the second conduction type collecting zone respectively；It is led second
Collector electrode metal layer, the collector electrode metal layer and the second conduction type collecting zone Ohmic contact are set on electric type collecting zone.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201821456297.2U CN208580747U (en) | 2018-09-06 | 2018-09-06 | The IGBT device of the double clamps of grid |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201821456297.2U CN208580747U (en) | 2018-09-06 | 2018-09-06 | The IGBT device of the double clamps of grid |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109192774A (en) * | 2018-09-06 | 2019-01-11 | 江苏中科君芯科技有限公司 | The IGBT device of the double clamps of grid |
| CN111211120A (en) * | 2018-11-21 | 2020-05-29 | 瀚薪科技股份有限公司 | Silicon carbide semiconductor component integrating clamping voltage clamping circuit |
| CN112786683A (en) * | 2020-12-29 | 2021-05-11 | 浙江清华长三角研究院 | Power device |
-
2018
- 2018-09-06 CN CN201821456297.2U patent/CN208580747U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109192774A (en) * | 2018-09-06 | 2019-01-11 | 江苏中科君芯科技有限公司 | The IGBT device of the double clamps of grid |
| CN111211120A (en) * | 2018-11-21 | 2020-05-29 | 瀚薪科技股份有限公司 | Silicon carbide semiconductor component integrating clamping voltage clamping circuit |
| CN112786683A (en) * | 2020-12-29 | 2021-05-11 | 浙江清华长三角研究院 | Power device |
| CN112786683B (en) * | 2020-12-29 | 2022-07-15 | 浙江清华长三角研究院 | Power device |
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