CN208351361U - A kind of band gap reference of high PSRR - Google Patents
A kind of band gap reference of high PSRR Download PDFInfo
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- CN208351361U CN208351361U CN201821015834.XU CN201821015834U CN208351361U CN 208351361 U CN208351361 U CN 208351361U CN 201821015834 U CN201821015834 U CN 201821015834U CN 208351361 U CN208351361 U CN 208351361U
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Abstract
The utility model discloses a kind of band gap references of high PSRR, are related to integrated circuit fields.The a reference source includes sequentially connected start-up circuit, main body circuit and voltage regulator circuit, the start-up circuit is provides biasing when entire circuit start, the main body circuit generates and exports the reference voltage source of high PSRR, and the voltage regulator circuit stablizes the internal power source voltage of the main body circuit；The band gap reference further includes switching tube, and the switching tube is connected to external power supply and the start-up circuit, and the start-up circuit is closed.The circuit structure of technical solutions of the utility model uses Current Feedback Control mode, the internal electric source of the main body circuit of band gap reference and external power supply are separated, and pressure stabilizing and clamper are carried out to the internal electric source of main body circuit, realize the reference voltage source output of high PSRR.
Description
Technical field
The utility model relates to integrated circuit fields, more particularly to a kind of band gap reference of high PSRR.
Background technique
In simulation, numerical model analysis, the high-precision of high PSRR, low-temperature coefficient is even required in totally digital circuit
Voltage-reference.The performance of voltage-reference directly determines the superiority and inferiority of circuit performance to a certain extent.Voltage reference is described
The index of source stability mainly has: power supply rejection ratio, temperature coefficient and noise characteristic etc..It is rapid with large scale integrated circuit
Development, bandgap voltage reference are widely used in various high-precision comparisons due to its Low Drift Temperature coefficient and stability
In the Analogous Integrated Electronic Circuits such as device, A/D and D/A converter, dynamic random access memory.
With the large-scale application and development of portable electronic device, the low-power consumption of chip becomes the key of chip design
The operating voltage of index, chip is also lower and lower.In view of the influence of noise, since power input noise is the weight for influencing output
Noise is wanted, in order to avoid noise coupling is into high-speed figure and analog circuit, it is necessary to propose a kind of to can produce high power supply suppression
The a reference source of ratio processed.
Utility model content
The main purpose of the utility model is to provide a kind of band gap references of high PSRR, it is intended to which output is stablized
, the reference voltage source of low supply voltage, high PSRR.
To achieve the above object, the utility model provides a kind of band gap reference of high PSRR, including successively connects
Start-up circuit, main body circuit and the voltage regulator circuit connect, the start-up circuit is provides biasing, the main body when entire circuit start
Circuit generates and exports the reference voltage source of high PSRR, and the voltage regulator circuit stablizes the internal electric source of the main body circuit
Voltage；The band gap reference further includes switching tube, and the switching tube is connected to external power supply and the start-up circuit, by institute
State start-up circuit closing.
Preferably, the main body circuit includes the first PMOS tube for being connected to the start-up circuit, the second PMOS tube and
Three PMOS tube, first PMOS tube are connected with the first NMOS tube, and first NMOS tube is connected with the first triode；Described
Two PMOS tube are connected with the second NMOS tube, and second NMOS tube is connected to the second triode by first resistor；The third
PMOS tube is connected to second resistance and 3rd resistor parallel with one another, and the second resistance is also connected with third transistor.
Preferably, the source electrode of first PMOS tube, second PMOS tube and the third PMOS tube is connected with each other, and
It is connected to the start-up circuit and the voltage regulator circuit；First PMOS tube, second PMOS tube and the 3rd PMOS
The drain electrode of the grid of pipe and the second PMOS tube is connected with each other, and is connected to the voltage regulator circuit；
The drain electrode of first PMOS tube is connected to the drain and gate and the 2nd NMOS of first NMOS tube
The grid of pipe；The source electrode of first NMOS tube is connected to the emitter of the first triode, the collector of first triode
The base stage of ground connection, the base stage of first triode and second triode is connected with each other and is grounded；
The drain electrode of second PMOS tube is also attached to the drain electrode of second NMOS tube, the source electrode of second NMOS tube
It is connected to one end of the first resistor, the other end of the first resistor is connected to the emitter of second triode, institute
State the grounded collector of the second triode；
The drain electrode of the third PMOS tube is connected to one end of the second resistance and one end of 3rd resistor, and described second
The other end of resistance is connected to the emitter of the third transistor, the other end ground connection of the 3rd resistor；Described 3rd 3
The base stage and grounded collector of pole pipe.
Preferably, the 3rd resistor is two concatenated sub- resistance compositions, is connected to the drain electrode of the third PMOS tube
Sub- resistance be also connected with the first output end of the main body circuit, the main body electricity is also connected between described two sub- resistance
The second output terminal of resistance.
Preferably, the 3rd resistor is variable resistance, and two fixing ends of the 3rd resistor are connected to described
The drain electrode of third PMOS tube and ground connection, and the fixing end for being connected to the drain electrode of the third PMOS tube is also connected with the main body electricity
First output end on road, the convertible tip of the 3rd resistor are connected to the second output terminal of the main body circuit.
Preferably, the voltage regulator circuit includes the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube and the 7th PMOS tube,
Third NMOS tube, the 4th NMOS tube, the 5th NMOS tube and the 6th NMOS tube and first capacitor；
4th PMOS tube be connected to the start-up circuit, the 5th PMOS tube, the 7th PMOS tube and
5th NMOS tube；5th PMOS tube is connected to the start-up circuit, first PMOS tube and the third
NMOS tube, the third NMOS tube are connected to the 4th NMOS tube；6th PMOS tube be connected to external power supply and
6th NMOS tube；7th PMOS tube is connected to the 6th PMOS tube, the start-up circuit and external power supply；Described
Four NMOS tubes, the 5th NMOS tube and the 6th NMOS tube ground connection；
Described first capacitor one end is connected to the start-up circuit, other end ground connection.
Preferably, the grid of the 4th PMOS tube is connected to the first PMOS tube described in the main body circuit,
The drain electrode of the grid and the second PMOS tube of two PMOS tube and third PMOS tube；The source electrode of 4th PMOS tube is connected to
Described 5th PMOS tube source electrode, the drain electrode of the 7th PMOS tube, one end of the first capacitor, the start-up circuit and
The source electrode of first PMOS tube, the second PMOS tube, third PMOS tube；The drain electrode of 4th PMOS tube is connected to the described 5th
The grid of the drain and gate of NMOS tube and the 6th NMOS tube；The source electrode of 5th NMOS tube and the 6th NMOS tube
Ground connection；
The grid of 5th PMOS tube is connected to the drain electrode of first PMOS tube and the drain electrode of first NMOS tube
And grid；The drain electrode of 5th PMOS tube is connected to grid and the drain electrode of the third NMOS tube；The third NMOS tube
Source electrode is connected with the drain and gate of the 4th NMOS tube, the source electrode ground connection of the 4th NMOS tube；
The source electrode of 6th PMOS tube is connected with the source electrode of the 7th PMOS tube and is connected to the external power supply；Institute
The grid for stating the 6th PMOS tube and the 7th PMOS tube is connected with each other and is connected to the drain electrode of the 6th PMOS tube；Described
The drain electrode of six PMOS tube is also respectively connected with drain electrode and the switching tube in the 6th NMOS tube.
Preferably, the start-up circuit includes the 8th PMOS tube and the 9th PMOS tube interconnected, and is connected to two
The 4th resistance of person.
Preferably, the source electrode of the 8th PMOS tube and the 9th PMOS tube is connected with each other and is connected to external power supply；
The grid of 8th PMOS tube and the 9th PMOS tube is connected with each other, and is connected to the leakage of the 8th PMOS tube simultaneously
Pole, switching tube and the 4th resistance one end, the 4th resistance the other end ground connection；The drain electrode of 9th PMOS tube connects
In the main body circuit.
Preferably, the switching tube is PMOS tube, and source electrode is connected to external power supply, and grid is connected to the pressure stabilizing electricity
Road, drain electrode are connected to the start-up circuit.
The circuit structure of technical solutions of the utility model uses Current Feedback Control mode, by the main body electricity of band gap reference
The internal electric source on road and external power supply separate, and carry out pressure stabilizing and clamper to the internal electric source of main body circuit, realize high power supply suppression
The reference voltage source of ratio processed exports.
Detailed description of the invention
Fig. 1 is the circuit diagram of the band gap reference of the utility model high PSRR.
The embodiments will be further described with reference to the accompanying drawings for the realization, functional characteristics and advantage of the utility model aim.
Specific embodiment
It should be appreciated that specific embodiment described herein is only used to explain the utility model, it is not used to limit this
Utility model.
The present invention will be further described with reference to the accompanying drawing.
As described in Figure 1, the utility model provides a kind of band gap reference of high PSRR, including sequentially connected opens
Dynamic circuit, main body circuit and voltage regulator circuit, to provide biasing when entire circuit start, the main body circuit produces the start-up circuit
The reference voltage source of high PSRR is given birth to and exports, the voltage regulator circuit stablizes the internal power source voltage of the main body circuit；
The band gap reference further includes switching tube, and the switching tube is connected to external power supply and the start-up circuit, is opened described
Dynamic circuit is closed.After the completion of entire circuit start, the switching tube P10 turns off start-up circuit, and start-up circuit is made to be detached from master
Body circuit, the internal electric source of main body circuit and external power supply VDD are separated, and realize the bandgap voltage reference of high PSRR
Source.
Preferably, the main body circuit includes the first PMOS tube P1 for being connected to the start-up circuit, the second PMOS tube P2
The first NMOS tube N1, the first NMOS tube N1, which is connected with, with third PMOS tube P3, the first PMOS tube P1 is connected with first
Triode Q1；The second PMOS tube P2 is connected with the second NMOS tube N2, and the second NMOS tube N2 is connected by first resistor R1
It is connected to the second triode Q2；The third PMOS tube P3 is connected to second resistance R2 parallel with one another and 3rd resistor R3, described
Second resistance R2 is also connected with third transistor Q3.
Preferably, the source electrode of the first PMOS tube P1, the second PMOS tube P2 and the third PMOS tube P3 are mutual
Connection, and it is connected to the start-up circuit and the voltage regulator circuit；The first PMOS tube P1, the second PMOS tube P2 and institute
The drain electrode for stating the grid and the second PMOS tube P2 of third PMOS tube P3 is connected with each other, and is connected to the voltage regulator circuit；
The drain electrode of the first PMOS tube P1 is connected to the drain and gate and described second of the first NMOS tube N1
The grid of NMOS tube N2；The source electrode of the first NMOS tube N1 is connected to the emitter of the first triode Q1, the one or three pole
The base stage of the grounded collector of pipe Q1, the base stage of the first triode Q1 and the second triode Q2 are connected with each other and are grounded
GND；
The drain electrode of the second PMOS tube P2 is also attached to the drain electrode of the second NMOS tube N2, the second NMOS tube N2
Source electrode be connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to the second triode Q2
Emitter, the grounded collector GND of the second triode Q2；
The drain electrode of the third PMOS tube P3 is connected to one end of the second resistance R2 and one end of 3rd resistor R3, institute
The other end for stating second resistance R2 is connected to the emitter of the third transistor Q3, the other end ground connection of the 3rd resistor R3
GND；The base stage and grounded collector GND of the third transistor Q3.
Preferably, the 3rd resistor R3 is two concatenated sub- resistance compositions, is connected to the third PMOS tube P3's
The sub- resistance of drain electrode is also connected with the first output end V of the main body circuitout1, it is also connected between described two sub- resistance
State the second output terminal V of body resistanceout2.In this embodiment, the reference voltage of output is fixed, by electric resistance partial pressure,
It can obtain any zero-temperature coefficient reference voltage lower than 1.25V.
Preferably, the 3rd resistor R3 is variable resistance, and two fixing ends of the 3rd resistor R3 are connected to
The drain electrode of the third PMOS tube P3 and ground connection GND, and the fixing end for being connected to the drain electrode of the third PMOS tube P3 is also connected with
There is the first output end V of the main body circuitout1, the convertible tip of the 3rd resistor R3 is connected to the second of the main body circuit
Output end Vout2.In this embodiment, the reference voltage of output can be adjusted by variable resistance, by adjusting resistance point
Pressure can obtain any zero-temperature coefficient reference voltage lower than 1.25V.
Preferably, the voltage regulator circuit includes the 4th PMOS tube P4, the 5th PMOS tube P5, the 6th PMOS tube P6 and the 7th
PMOS tube P7, third NMOS tube N3, the 4th NMOS tube N4, the 5th NMOS tube N5 and the 6th NMOS tube N6 and first capacitor C1；
The 4th PMOS tube P4 is connected to the start-up circuit, the 5th PMOS tube P5, the 7th PMOS
Pipe P7 and the 5th NMOS tube N5；The 5th PMOS tube P5 is connected to the start-up circuit, first PMOS tube
The P1 and third NMOS tube N3, the third NMOS tube N3 are connected to the 4th NMOS tube N4；The 6th PMOS tube P6
It is connected to external power supply VDD and the 6th NMOS tube N6；The 7th PMOS tube P7 is connected to the 6th PMOS tube P6, institute
State start-up circuit and external power supply VDD；The 4th NMOS tube N4, the 5th NMOS tube N5 and the 6th NMOS tube
N6 is grounded GND；
The one end the first capacitor C1 is connected to the start-up circuit, and the other end is grounded GND.
Preferably, the grid of the 4th PMOS tube P4 is connected to the first PMOS tube described in the main body circuit
The drain electrode of P1, the grid of the second PMOS tube P2 and third PMOS tube P3 and the second PMOS tube P2；The 4th PMOS tube P4's
Source electrode be connected to the drain electrode of the described 5th PMOS tube source electrode, the 7th PMOS tube P7, the first capacitor C1 one
The source electrode at end, the start-up circuit and the first PMOS tube P1, the second PMOS tube P2, third PMOS tube P3；Described 4th
The drain electrode of PMOS tube P4 is connected to the drain and gate of the 5th NMOS tube N5 and the grid of the 6th NMOS tube N6；It is described
The source electrode of 5th NMOS tube N5 and the 6th NMOS tube N6 are grounded GND；
The grid of the 5th PMOS tube P5 be connected to the first PMOS tube P1 drain electrode and the first NMOS tube N1
Drain and gate；The drain electrode of the 5th PMOS tube P5 is connected to grid and the drain electrode of the third NMOS tube N3；Described
The source electrode of three NMOS tube N3 is connected with the drain and gate of the 4th NMOS tube N4, the source electrode ground connection of the 4th NMOS tube N4
GND, and the Substrate ground GND of the two；
The source electrode of the 6th PMOS tube P6 is connected with the source electrode of the 7th PMOS tube P7 and is connected to the external electrical
Source VDD；The grid of the 6th PMOS tube P6 and the 7th PMOS tube P7 is connected with each other and is connected to the 6th PMOS tube
The drain electrode of P6；The drain electrode of the 6th PMOS tube P6 is also respectively connected with drain electrode and the switching tube in the 6th NMOS tube N6
P10。
Preferably, the start-up circuit includes the 8th PMOS tube P8 and the 9th PMOS tube P9 interconnected, and connection
In the 4th resistance R4 of the two.
Preferably, the source electrode of the 8th PMOS tube P8 and the 9th PMOS tube P9 is connected with each other and is connected to external electrical
Source VDD；The grid of the 8th PMOS tube P8 and the 9th PMOS tube P9 is connected with each other, and is connected to the described 8th simultaneously
The drain electrode of PMOS tube P8, switching tube P10 and the 4th resistance R4 one end, the other end of the 4th resistance R4 is grounded GND；Institute
The drain electrode for stating the 9th PMOS tube P9 is connected to the main body circuit.
Preferably, the switching tube P10 is PMOS tube, and source electrode is connected to external power supply VDD, and grid is connected to described
Voltage regulator circuit, drain electrode are connected to the start-up circuit.
As shown in Figure 1, the course of work and working principle of the utility model are as described below:
External power supply VDD is connected, after external power supply reaches the conduction threshold of the 8th PMOS tube P8, the 8th PMOS tube P8 is led
It is logical, current limliting is realized by the 4th resistance R4, electric current is electrically charged by current mirror mirror to the 9th PMOS tube P9, first capacitor C1, main
The internal power cord net01 voltage of body circuit increases.
After the voltage of internal power cord net01, which reaches the main body circuit, opens threshold value, the main body circuit starting；?
In the present embodiment, the ratio of the first NMOS tube N1 and the second NMOS tube N2 are set as 1:1；By the first triode Q1, the two or three pole
Pipe Q2, third transistor Q3 ratio be set as 1:m:1；The ratio of first PMOS tube P1, the second PMOS tube P2 and third PMOS tube P3
Example is set as 1:1:n；
Each branch current size for determining main body circuit is calculated by following equatioies:
Wherein, k is that bohr hereby overflows constant, and T is temperature, and q is the unit quantity of electric charge, and m is PNP pipe the first triode Q1 and second
The quantity ratio of triode Q2；Vbe1For the emitter voltage drop of the first triode Q1, Vbe2For the emitter voltage drop of the second triode Q2；
I2+I3=n*I0
Wherein, Vbe3For the emitting stage pressure drop of third transistor Q3, n is the mirror of the first PMOS tube P1 and third PMOS tube P3
As ratio；R3AFor the first output end Vout1To second output terminal Vout2Between resistance value, R3BFor second output terminal Vout2With third
Resistance R3 is grounded the resistance value between the end GND；
By the above-mentioned equation of simultaneous, available following equatioies, to calculate the first output end Vout1Output voltage:
Pass through the equation: by adjusting the ratio of second resistance R2 and 3rd resistor R3, available zero-temperature coefficient
First output voltageVout1。
In the first output voltage V for obtaining zero-temperature coefficientout1After, by adjusting R3AAnd R3BRatio, it is available
Second output voltage V of zero-temperature coefficientout2。
By the 4th PMOS tube P4, electric current I is obtained4, then by mirror image twice, respectively obtain electric current I5And I6, electric current ratio
Example relationship is set as: I4: I5: I6=1:1:X；
Internal power cord net01 whole electric currents of consumption are provided by the 7th PMOS tube P7, it may be assumed that I6≥I0+I1+I2+I3+I4；
In order to retain certain surplus, by I6Value suitably increase (i.e. proportionality coefficient X increase), extra electric current is exactly I7, pass through
Five PMOS tube P5, third NMOS tube N3 and the 4th NMOS tube N4 flow into GND current potential, available current relationship:
I6=I0+I1+I2+I3+I4+I7；
Voltage regulator circuit is stablized internal power cord net01 current potential: (V by negative-feedbackgs_P5+Vgs_N1+Vbe1), the electricity
Pressure does not change with the variation of external power supply VDD, so that output voltage Vout1And Vout2Also not with the variation of external power supply VDD and
Variation；
Wherein, Vgs_P5For the gate source voltage of the 5th PMOS tube P5, Vgs_N1For the gate source voltage of the first NMOS tube N1.
When external disturbance increases net01 voltage, the gate source voltage of third PMOS tube P3 increases, so that drain-source current
Increase, so that output voltage Vout1And Vout2Increase.But the meanwhile gate source voltage V of the 5th PMOS tube P5gs_P5Also can increase simultaneously
Greatly, discharge current I7Increase, the discharge current I of first capacitor C17Greater than charging current (I6-I0-I1-I2-I3-I4), net01 electricity
Pressure falls back to normal value, output voltage Vout1And Vout2It keeps stablizing；
Similarly, when external disturbance reduces net01 voltage, the gate source voltage of third PMOS tube P3 reduces, drain-source electricity
Stream will reduce, so that output voltage Vout1And Vout2It reduces.But the gate source voltage V of the 5th PMOS tube P5gs_P5It also can be simultaneously
Reduce, discharge current I7Reduce, the discharge current I of first capacitor C17Less than charging current (I6-I0-I1-I2-I3-I4), net01
Voltage is increased to normal value, output voltage Vout1And Vout2It keeps stablizing.
The electric current of the 6th PMOS tube P6 of switching tube P10 mirror image, which flows through the 4th resistance R4 and generates pressure drop, so that the 4th
Pressure drop on resistance R4 is equal with external power supply VDD, at this point, the 8th PMOS tube P8 and the 9th PMOS tube P9 cut-off, so that starting
Circuit is detached from main body circuit.
When entire reference source circuit works normally, since start-up circuit has been switched off, the variation of outer power voltage is not
The voltage that net01 can be influenced by start-up circuit, to not influence output voltage Vout1And Vout2；
On the other hand, the electric current of the 7th PMOS tube P7 is obtained by the 6th PMOS tube P6 mirror image, and the electricity of the 6th PMOS tube P6
Stream is determined by the 4th PMOS tube P4, the 5th NMOS tube N5 and the 6th NMOS tube N6, unrelated with external power supply VDD, therefore,
The voltage of net01 and external power supply VDD are almost unrelated, thus output voltage Vout1And Vout2Also with external power supply VDD almost without
It closes, so that the band gap reference has very high power supply rejection ratio.
In further embodiments, main body circuit introduces profound and negative feedbck by increasing amplifier structure, further increases electricity
Source inhibits ratio, specifically, exporting control the first PMOS tube P1, the second PMOS tube P2, third PMOS tube P3 and the 4th by amplifier
The grid voltage of PMOS tube P4 reduces output voltage V by negative-feedbackout1And Vout2It is influenced by net01 voltage, is further mentioned
High output voltage Vout1And Vout2Inhibition to external power vd D.
It should be understood that cannot therefore limit the utility model the above is only the preferred embodiment of the utility model
The scope of the patents, equivalent structure or equivalent flow shift made by using the description of the utility model and the drawings, or it is straight
It connects or is used in other related technical areas indirectly, be also included in the patent protection scope of the utility model.
Claims (10)
1. a kind of band gap reference of high PSRR, which is characterized in that including sequentially connected start-up circuit, main body circuit
And voltage regulator circuit, to provide biasing when entire circuit start, the main body circuit generates and exports high power supply the start-up circuit
Inhibit the reference voltage source of ratio, the voltage regulator circuit stablizes the internal power source voltage of the main body circuit；The band gap reference
It further include switching tube, the switching tube is connected to external power supply and the start-up circuit, and the start-up circuit is closed.
2. the band gap reference of high PSRR according to claim 1, which is characterized in that the main body circuit includes
It is connected to the first PMOS tube, the second PMOS tube and third PMOS tube of the start-up circuit, first PMOS tube is connected with
One NMOS tube, first NMOS tube are connected with the first triode；Second PMOS tube is connected with the second NMOS tube, and described
Two NMOS tubes are connected to the second triode by first resistor；The third PMOS tube be connected to second resistance parallel with one another and
3rd resistor, the second resistance are also connected with third transistor.
3. the band gap reference of high PSRR according to claim 2, which is characterized in that first PMOS tube,
The source electrode of second PMOS tube and the third PMOS tube is connected with each other, and is connected to the start-up circuit and pressure stabilizing electricity
Road；First PMOS tube, second PMOS tube and the grid of the third PMOS tube and the leakage of second PMOS tube
Pole is connected with each other, and is connected to the voltage regulator circuit；
The drain electrode of first PMOS tube be connected to first NMOS tube drain and gate and second NMOS tube
Grid；The source electrode of first NMOS tube is connected to the emitter of the first triode, the grounded collector of first triode,
The base stage of first triode and the base stage of second triode are connected with each other and are grounded；
The drain electrode of second PMOS tube is also attached to the drain electrode of second NMOS tube, the source electrode connection of second NMOS tube
In one end of the first resistor, the other end of the first resistor is connected to the emitter of second triode, and described
The grounded collector of two triodes；
The drain electrode of the third PMOS tube is connected to one end of the second resistance and one end of 3rd resistor, the second resistance
The other end be connected to the emitter of the third transistor, the other end ground connection of the 3rd resistor；The third transistor
Base stage and grounded collector.
4. the band gap reference of high PSRR according to claim 3, which is characterized in that the 3rd resistor is two
A concatenated sub- resistance composition, the sub- resistance for being connected to the drain electrode of the third PMOS tube are also connected with the of the main body circuit
One output end is also connected with the second output terminal of the body resistance between described two sub- resistance.
5. the band gap reference of high PSRR according to claim 2, which is characterized in that the 3rd resistor is can
Power transformation resistance, two fixing ends of the 3rd resistor are connected to drain electrode and the ground connection of the third PMOS tube, and are connected to
The fixing end of the drain electrode of the third PMOS tube is also connected with the first output end of the main body circuit, the 3rd resistor can
Become the second output terminal that end is connected to the main body circuit.
6. the band gap reference of high PSRR according to claim 2, which is characterized in that the voltage regulator circuit includes
4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube and the 7th PMOS tube, third NMOS tube, the 4th NMOS tube, the 5th NMOS tube
With the 6th NMOS tube and first capacitor；
4th PMOS tube is connected to the start-up circuit, the 5th PMOS tube, the 7th PMOS tube and described
5th NMOS tube；5th PMOS tube is connected to the start-up circuit, first PMOS tube and the 3rd NMOS
Pipe, the third NMOS tube are connected to the 4th NMOS tube；6th PMOS tube is connected to external power supply and the 6th
NMOS tube；7th PMOS tube is connected to the 6th PMOS tube, the start-up circuit and external power supply；Described 4th
NMOS tube, the 5th NMOS tube and the 6th NMOS tube ground connection；
Described first capacitor one end is connected to the start-up circuit, other end ground connection.
7. the band gap reference of high PSRR according to claim 6, which is characterized in that the 4th PMOS tube
Grid is connected to the first PMOS tube described in the main body circuit, the grid of the second PMOS tube and third PMOS tube and
The drain electrode of two PMOS tube；The source electrode of 4th PMOS tube be connected to the described 5th PMOS tube source electrode, the described 7th
The drain electrode of PMOS tube, one end of the first capacitor, the start-up circuit and first PMOS tube, the second PMOS tube,
The source electrode of three PMOS tube；The drain electrode of 4th PMOS tube is connected to the drain and gate and the described 6th of the 5th NMOS tube
The grid of NMOS tube；The source electrode of 5th NMOS tube and the 6th NMOS tube ground connection；
The grid of 5th PMOS tube is connected to the drain electrode of first PMOS tube and drain electrode and the grid of first NMOS tube
Pole；The drain electrode of 5th PMOS tube is connected to grid and the drain electrode of the third NMOS tube；The source electrode of the third NMOS tube
It is connected with the drain and gate of the 4th NMOS tube, the source electrode ground connection of the 4th NMOS tube；
The source electrode of 6th PMOS tube is connected with the source electrode of the 7th PMOS tube and is connected to the external power supply；Described
The grid of six PMOS tube and the 7th PMOS tube is connected with each other and is connected to the drain electrode of the 6th PMOS tube；Described 6th
The drain electrode of PMOS tube is also respectively connected with drain electrode and the switching tube in the 6th NMOS tube.
8. the band gap reference of high PSRR according to claim 2, which is characterized in that the start-up circuit includes
8th PMOS tube and the 9th PMOS tube interconnected, and it is connected to the 4th resistance of the two.
9. the band gap reference of high PSRR according to claim 8, which is characterized in that the 8th PMOS tube and
The source electrode of 9th PMOS tube is connected with each other and is connected to external power supply；8th PMOS tube and the 9th PMOS tube
Grid is connected with each other, and is connected to one end of the drain electrode of the 8th PMOS tube, switching tube and the 4th resistance simultaneously, and described the
The other end of four resistance is grounded；The drain electrode of 9th PMOS tube is connected to the main body circuit.
10. the band gap reference of high PSRR according to claim 1, which is characterized in that the switching tube is
PMOS tube, source electrode are connected to external power supply, and grid is connected to the voltage regulator circuit, and drain electrode is connected to the starting electricity
Road.
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| CN108829169A (en) * | 2018-06-29 | 2018-11-16 | 成都锐成芯微科技股份有限公司 | A kind of band gap reference of high PSRR |
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