CN207800043U - 驱动芯片及显示装置 - Google Patents

驱动芯片及显示装置 Download PDF

Info

Publication number
CN207800043U
CN207800043U CN201820304616.1U CN201820304616U CN207800043U CN 207800043 U CN207800043 U CN 207800043U CN 201820304616 U CN201820304616 U CN 201820304616U CN 207800043 U CN207800043 U CN 207800043U
Authority
CN
China
Prior art keywords
convex block
driving chip
height
buffering
face
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201820304616.1U
Other languages
English (en)
Inventor
刘练彬
梁恒镇
兰传艳
吴国强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201820304616.1U priority Critical patent/CN207800043U/zh
Application granted granted Critical
Publication of CN207800043U publication Critical patent/CN207800043U/zh
Priority to US16/756,976 priority patent/US11217549B2/en
Priority to PCT/CN2018/112564 priority patent/WO2019169879A1/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1405—Shape
    • H01L2224/14051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1415—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/14151—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1415—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/14154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/14177—Combinations of arrays with different layouts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
    • H01L2224/81903—Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

本文公布了一种驱动芯片及显示装置，驱动芯片包括衬底和设置在衬底上的多个连接凸块，还设置有多个缓冲凸块，所述缓冲凸块具有高度为a的第一端面，所述连接凸块具有高度为b的端面，a＜b，所述高度为端面到衬底表面之间的距离；显示装置包括所述驱动芯片。本实用新型可应用于显示技术领域，应用本实用新型能够有效克服现有技术中存在的缺陷，通过增加优选设置的凸块，实现应力的缓冲目的，进而提高驱动集成电路的绑定效果。

Description

驱动芯片及显示装置
技术领域
本申请涉及显示技术领域，具体涉及一种驱动芯片及显示装置。
背景技术
柔性基板因其轻薄且抗冲击性能好等特点而越来越广泛的应用在显示装置中。此类显示装置在制作时一般先将柔性基板固定在玻璃基板上，再进行之后的柔性显示面板制作工艺。过程中，需要将驱动集成电路(Driver Integrated Circuit,Driver IC)绑定在显示面板(Panel)，通过驱动集成电路对显示面板驱动，以使显示面板显示出预设的画面。
在驱动集成电路的绑定过程中，需要将驱动集成电路背面设置的连接凸块(Bump)接触显示面板上裸露设置的金属引线，以实现相应的电连接功能；其中，上述驱动集成电路背面设置的连接凸块的高度均相同。在上述驱动集成电路的绑定过程中，驱动集成电路的多个区域承受的应力不同，易出现绑定效果欠佳的缺陷；同时，显示面板易出现显示异常的情况，甚至产生破裂。
实用新型内容
本申请解决的技术问题是提供一种驱动芯片及显示装置，能够有效克服现有技术中存在的缺陷，通过增加优选设置的凸块，以实现应力的缓冲目的，进而提高驱动集成电路的绑定效果。
为解决上述技术问题，本申请提供了一种驱动芯片，包括衬底和设置在衬底上的多个连接凸块，还设置有多个缓冲凸块；
所述缓冲凸块具有高度为a的第一端面，所述连接凸块具有高度为b的端面，a＜b，所述高度为端面到衬底表面之间的距离。
上述驱动芯片，还可具有如下特点：
所述缓冲凸块还具有高度为b的第二端面。
上述驱动芯片，还可具有如下特点：
所述缓冲凸块包括高度为a的第一子凸块和高度为b的第二子凸块，所述第一子凸块和第二子凸块相互独立设置。
上述驱动芯片，还可具有如下特点：
所述缓冲凸块包括阶梯凸块，所述阶梯凸块具有高度为a、b的阶梯面。
上述驱动芯片，还可具有如下特点：
所述缓冲凸块设置在所述连接凸块之间，和/或设置在所述衬底上的空白区域。
上述驱动芯片，还可具有如下特点：
所述缓冲凸块的高度a与连接凸块的高度b之间的关系：b/3≤a＜2b/3。
上述驱动芯片，还可具有如下特点：
所述缓冲凸块均布设置在所述衬底上。
上述驱动芯片，还可具有如下特点：
所述多个连接凸块包括沿第一方向排列的至少一组连接凸块，所述多个缓冲凸块包括沿所述第一方向排列的至少一组缓冲凸块。
上述驱动芯片，还可具有如下特点：
缓冲凸块之间的距离等于相邻连接凸块距离的最小值。
为了解决上述技术问题，本实用新型还提供了一种显示装置，包括所述的驱动芯片。
本申请上述技术方案具有如下有益效果：
相比于现有技术，本申请通过增加不同高度的凸块，以实现应力的缓冲目的，进而提高驱动集成电路的绑定效果。
本申请的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本实用新型实施例而了解。本申请的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本申请技术方案的进一步理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1为现有技术中的驱动芯片示意图；
图2为本实用新型实施例一的驱动芯片示意图；
图3为本实用新型实施例二的驱动芯片示意图；
图4为本实用新型实施例三的驱动芯片示意图；
图5为本实用新型实施例四的驱动芯片示意图；
图示说明：
1-衬底，2-连接凸块，3-空白区域，41-缓冲凸块的第一端面，42-缓冲凸块的第二端面。
具体实施方式
下文中将结合附图对本申请的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
如图1所示，现有技术中的驱动芯片包括衬底1和设置在衬底1上的多个连接凸块2，连接凸块2之间具有较大的空白区域3，连接凸块2的高度均为b。在上述驱动集成电路的绑定过程中，驱动集成电路的多个区域承受的应力不同，如设置有同等高度的连接凸块2的区域和空白区域3的承受应力不同，易出现绑定效果欠佳的缺陷；同时，显示面板易出现显示异常的情况，甚至产生破裂。
为了能够有效解决上述技术问题，本实用新型提供有如下多个实施例：
实施例一：
如图2所示，本实用新型实施例一提供了一种驱动芯片，包括衬底1和设置在衬底1上的多个连接凸块2，还设置有多个缓冲凸块；缓冲凸块具有高度为a的第一端面41，连接凸块2具有高度为b的端面，a＜b；其中，上述高度具体为端面到衬底1表面之间的距离。
具体操作中，通过上述缓冲凸块第一端面41的优选设置，能够实现应力的缓冲作用；绑定过程中，驱动集成电路可先接触连接凸块2的端面，随着压力增加，在后期即可接触到缓冲凸块的第一端面41，能够通过增加不同高度的接触面，实现应力缓冲的技术效果，最终能够有效提高绑定效果。
本实施例中的缓冲凸块，优选设置在衬底1上的空白区域3。
具体操作中，通过上述优选区域的设置，能够有效减小驱动集成电路的多个区域的应力差异，尤其是设置有同等高度的连接凸块2的区域和空白区域3的应力差异，最终能够进一步的提高绑定效果。
本实施例中，缓冲凸块第一端面41的高度a与连接凸块2的高度b之间的关系：b/3≤a＜2b/3。
具体操作中，上述缓冲凸块第一端面41的高度a优选为连接凸块2的高度的一半，即a＝b/2；上述优选高度尺寸的设置，能够有效避免因缓冲凸块与连接凸块2的端面高度差过大或过小所造成的缓冲效果欠佳的缺陷。
本实施例中的驱动集成电路通过热压各向异性导电胶膜(AnisotropicConductive Film，ACF)工艺绑定在显示面板上。
实施例二：
本实用新型实施例二提供了一种驱动芯片，主体结构与实施例一类似，也包括衬底1、连接凸块2和缓冲凸块；关于主体结构的具体设置，请参见实施例一中的详细记载，此处旨在阐述两者之间的区别。
如图3所示，本实施例中的缓冲凸块，还具有高度为b的第二端面42。
具体操作中，通过高度等同于连接凸块2端面高度的第二端面42的优选设置，能够使得驱动集成电路在接触初期所受到的应力更均匀，能够有效克服现有技术中的空白区域3因未设凸块所带来的应力差异缺陷，能够进一步的提高驱动集成电路的绑定效果。
本实施例中的缓冲凸块包括阶梯凸块，阶梯凸块具有高度为a、b的阶梯面，即上述缓冲凸块为设置有第一端面41的第二端面42的一体结构。
具体操作中，上述阶梯凸块的设置，能够实现相应的逐步缓冲的有益技术效果；同时，上述一体结构的缓冲凸块，具有便捷制造、便捷组装等诸多优点。
本实施例中，多个连接凸块2包括沿第一方向排列的至少一组连接凸块2，多个缓冲凸块包括沿第一方向排列的至少一组缓冲凸块。
具体操作中，上述衬底1上设置有沿第一方向排列的5个连接凸块2，第4个凸块和第5个凸块的之间具有较大的空白区域3；空白区域3内设置有两个缓冲凸块；缓冲凸块的排列方向与连接凸块2的排列方向相同，均沿第一方向排列；上述具有相同排列方向的缓冲凸块和连接凸块2，能够进一步的保证驱动集成电路的所受应力的均匀分布特性。
本实施例中，缓冲凸块之间的距离等于相邻连接凸块2距离的最小值。
具体操作中，通过上述缓冲凸块的优选间距的设置，能够进一步的提高驱动集成电路所受应力的均匀分布特性。
实施例三：
本实用新型实施例三提供了一种驱动芯片，主体结构与实施例二类似，也包括衬底1、连接凸块2和缓冲凸块；关于主体结构的具体设置，请参见实施例二中的详细记载，此处旨在阐述两者之间的区别。
如图4所示，本实施例中的缓冲凸块包括高度为a的第一子凸块和高度为b的第二子凸块，第一子凸块和第二子凸块相互独立设置；即第一子凸块具有高度为a的第一端面41，第二子凸块具有高度为b的第二端面42。
具体操作中，上述包括两个独立设置的子凸块的缓冲凸块，能够有效克服一体设置缓冲凸块的阶梯处的应力集中缺陷，即能够有效克服一体设置缓冲凸块的第一端面和第二端面的连接处的应力集中缺陷；上述独立设置的子凸块，应用更为灵活，能够进一步的提高驱动集成电路的绑定效果。
本实施例中的缓冲凸块均布设置在衬底1上。
具体操作中，上述均布设置的缓冲凸块，能够有效保证驱动集成电路所受应力的均匀分布特性，进而能够有效提高驱动集成电路的绑定效果。
实施例四：
本实用新型实施例四提供了一种驱动芯片，主体结构与实施例三类似，也包括衬底1、连接凸块2和缓冲凸块；关于主体结构的具体设置，请参见实施例三中的详细记载，此处旨在阐述两者之间的区别。
本实施例中的缓冲凸块可以设置在连接凸块2之间，以实现连接凸块2之间区域的应力缓冲技术效果，当相邻连接凸块2的间距过大时，在相邻连接凸块2的之间区域设有缓冲凸块，能够实现良好的应力缓冲技术效果；上述缓冲凸块也可以设置在衬底1上的空白区域3，与实施例一、二、三的设置位置类似，能够有效提高驱动集成电路在空白区域3处的应力缓冲技术效果。
如图5所示，本实施例中的缓冲凸块包括设置在所述连接凸块2之间的部分缓冲凸块，和设置在所述衬底1上的空白区域3的部分缓冲凸块。
具体操作中，上述优选设置的缓冲凸块，能够实现连接凸块2之间的应力缓冲，也能够实现驱动集成电路在空白区域3处的应力缓冲技术效果，能够有效提高驱动集成电路的绑定效果。
实施例五：
本实用新型实施例五提供了一种显示装置，包括实施例一或实施例二或实施例三或实施例四中记载的驱动芯片。
在本申请的描述中，术语“设置”、“相连”、“连接”、“固定”等均应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是直接相连，也可以通过中间媒介间接相连。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本说明书的描述中，术语“一个实施例”、“一些实施例”、“具体实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或特点包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或实例。而且，描述的具体特征、结构、材料或特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
本领域的技术人员应该明白，虽然本实用新型实施例所揭露的实施方式如上，但所述的内容仅为便于理解本实用新型实施例而采用的实施方式，并非用以限定本实用新型实施例。任何本实用新型实施例所属领域内的技术人员，在不脱离本实用新型实施例所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本实用新型实施例的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (10)

1.一种驱动芯片，包括衬底和设置在衬底上的多个连接凸块，其特征在于，还设置有多个缓冲凸块；
所述缓冲凸块具有高度为a的第一端面，所述连接凸块具有高度为b的端面，a＜b，所述高度为端面到衬底表面之间的距离。
2.根据权利要求1所述的驱动芯片，其特征在于，
所述缓冲凸块还具有高度为b的第二端面。
3.根据权利要求2所述的驱动芯片，其特征在于，
所述缓冲凸块包括高度为a的第一子凸块和高度为b的第二子凸块，所述第一子凸块和第二子凸块相互独立设置。
4.根据权利要求2所述的驱动芯片，其特征在于，
所述缓冲凸块包括阶梯凸块，所述阶梯凸块具有高度为a、b的阶梯面。
5.根据权利要求1-4中任一所述的驱动芯片，其特征在于，
所述缓冲凸块设置在所述连接凸块之间，和/或设置在所述衬底上的空白区域。
6.根据权利要求1-4中任一所述的驱动芯片，其特征在于，
所述缓冲凸块的高度a与连接凸块的高度b之间的关系：b/3≤a＜2b/3。
7.根据权利要求1-4中任一所述的驱动芯片，其特征在于，
所述缓冲凸块均布设置在所述衬底上。
8.根据权利要求7所述的驱动芯片，其特征在于，
所述多个连接凸块包括沿第一方向排列的至少一组连接凸块，所述多个缓冲凸块包括沿所述第一方向排列的至少一组缓冲凸块。
9.根据权利要求8所述的驱动芯片，其特征在于，
缓冲凸块之间的距离等于相邻连接凸块距离的最小值。
10.一种显示装置，其特征在于，包括权利要求1-9中任一所述的驱动芯片。
CN201820304616.1U 2018-03-05 2018-03-05 驱动芯片及显示装置 Expired - Fee Related CN207800043U (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201820304616.1U CN207800043U (zh) 2018-03-05 2018-03-05 驱动芯片及显示装置
US16/756,976 US11217549B2 (en) 2018-03-05 2018-10-30 Driving chip and display device
PCT/CN2018/112564 WO2019169879A1 (zh) 2018-03-05 2018-10-30 驱动芯片及显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201820304616.1U CN207800043U (zh) 2018-03-05 2018-03-05 驱动芯片及显示装置

Publications (1)

Publication Number Publication Date
CN207800043U true CN207800043U (zh) 2018-08-31

Family

ID=63275537

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201820304616.1U Expired - Fee Related CN207800043U (zh) 2018-03-05 2018-03-05 驱动芯片及显示装置

Country Status (3)

Country Link
US (1) US11217549B2 (zh)
CN (1) CN207800043U (zh)
WO (1) WO2019169879A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019169879A1 (zh) * 2018-03-05 2019-09-12 京东方科技集团股份有限公司 驱动芯片及显示装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW506103B (en) 2001-08-06 2002-10-11 Au Optronics Corp Bump layout on a chip
KR100672650B1 (ko) * 2004-02-25 2007-01-24 엘지.필립스 엘시디 주식회사 액정 표시 장치 및 이의 제조 방법
CN101414583A (zh) 2007-10-15 2009-04-22 奇美电子股份有限公司 具有倒装片结构的显示装置
KR101519844B1 (ko) * 2008-01-07 2015-05-13 삼성디스플레이 주식회사 터치스크린패널용 상부기판, 그 제조방법 및 이를 갖는표시장치
CN101533816B (zh) 2009-05-06 2011-02-09 友达光电股份有限公司 导电凸块结构及显示面板的芯片焊接结构
JP5972041B2 (ja) * 2012-05-15 2016-08-17 三菱電機株式会社 液晶表示装置
KR20150038842A (ko) * 2013-10-01 2015-04-09 삼성디스플레이 주식회사 구동 칩, 이를 구비한 표시 장치 및 구동 칩 제조 방법
CN107621710A (zh) 2017-11-10 2018-01-23 京东方科技集团股份有限公司 驱动芯片、显示基板、显示装置及显示装置的制作方法
CN207800043U (zh) 2018-03-05 2018-08-31 京东方科技集团股份有限公司 驱动芯片及显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019169879A1 (zh) * 2018-03-05 2019-09-12 京东方科技集团股份有限公司 驱动芯片及显示装置
US11217549B2 (en) 2018-03-05 2022-01-04 Chengdu Boe Optoelectronics Technology Co., Ltd. Driving chip and display device

Also Published As

Publication number Publication date
WO2019169879A1 (zh) 2019-09-12
US11217549B2 (en) 2022-01-04
US20200273831A1 (en) 2020-08-27

Similar Documents

Publication Publication Date Title
CN103217845B (zh) 下基板及其制造方法、液晶显示面板和液晶显示器
CN100516995C (zh) 用于基板的夹具及其制造方法
JP2005026682A (ja) Ｃｏｇ実装方式の構造
JP4504795B2 (ja) 駆動チップ及びこれを有する表示装置
CN103269563B (zh) 覆晶薄膜柔性电路板及显示装置
CN110570772A (zh) 柔性显示装置及其制备方法
CN102650776A (zh) 一种液晶显示面板及液晶显示器
US20190148327A1 (en) Driving chip, display substrate, display device and method for manufacturing display device
CN107632475A (zh) 显示面板及显示装置
CN104373914B (zh) 一种灯条散热结构、背光模组及显示装置
JP2012227480A (ja) 表示装置及び半導体集積回路装置
CN207800043U (zh) 驱动芯片及显示装置
TW200523610A (en) Driver chip and display apparatus including the same
CN107749240A (zh) 一种显示面板以及显示器
CN108776407A (zh) 一种显示模组及终端
WO2020019468A1 (zh) Tft阵列基板及其制造方法与柔性液晶显示面板
CN209343102U (zh) 一种覆晶薄膜和显示面板
US20210091027A1 (en) Array substrate and chip bonding method
CN111312090A (zh) 显示面板及其制作方法、显示装置
CN114924443A (zh) Lcos显示器及其制作方法
CN108469703A (zh) 液晶显示器
CN207689788U (zh) 一种液晶显示模组
CN201622408U (zh) 液晶显示面板
CN205643959U (zh) 一种背光模组及显示设备
CN207424443U (zh) 一种显示装置

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20180831