CN207671684U - A kind of total silicon three-dimension packaging structure based on silicon pinboard - Google Patents
A kind of total silicon three-dimension packaging structure based on silicon pinboard Download PDFInfo
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Abstract
The utility model provides a kind of total silicon three-dimension packaging structure based on silicon pinboard comprising silicon package substrate, silicon sealing cap and several microelectronic chips；The silicon package substrate is provided with several free columns, free top end is detached by surrounding gap with substrate, free column bottom end fixed and insulation is realized by insulating materials and silicon package substrate, the upper surface and lower face of the silicon package substrate are covered each by insulating layer, and the surface of free column top free end and the surface of bottom fixing end have the Ohmic contact being made of metal layer and silicon base；The silicon sealing cap is with certain thickness shell, which is provided with pit；The silicon sealing cap bonds the upper surface or lower face for being laminated in silicon package substrate by metal bonding or organic matter；The upper surface of the silicon package substrate, silicon sealing cap shell pit are interior including at least a microelectronic chip, and the microelectronic chip is placed in the upper surface of silicon package substrate in the form of upside-down mounting or formal dress.
Description
Technical field
The total silicon three-dimension packaging structure based on silicon pinboard that the utility model is related to a kind of belonging to microelectronic packaging technology neck
Domain.
Background technology
Microelectronics Packaging can be divided into air-tight packaging and non-tight dress, and air-tight packaging refers to being fully able to prevent dirt
Contaminate the encapsulation of the intrusion and corrosion of object (liquid and solid etc.).The level Hermetic Package of high performance integrated circuit IC and discrete device is adopted more
With Can, ceramics, glass-encapsulated etc., package interior is cavity structure, filled with high pure nitrogen or other inert gases.Work
Industry grade and business level device generally use plastic package process, without cavity, chip is entirely wrapped by polymeric material, belongs to non-more
Level Hermetic Package.The non-hermetically sealed packaging heat dissipation of plastic packaging is poor, is divided into business level and technical grade, quotient according to application field is unusual
Industry grade nominal operation environment temperature is 0-70 DEG C, and technical grade nominal operation environment temperature is -40-85 DEG C.
Can encapsulates the packing forms for belonging to semitight, and electromagnetism letter can be isolated in metal shell to a certain extent
Number, avoid electromagnetic interference, electromagnetism interference performance good；Ceramic cartridge packaging air tightness is good, stable chemical performance, thermal conductivity and heat
The coefficient of expansion is higher and close with chip, but the disadvantage is that ceramic cartridge substrate manufacture process is complicated, ceramic package substrates are special
Line width and microelectronic feature line width are levied there are still larger gap, production efficiency is low etc..
TSV silicon switching plate technique (Through Silicon Via, TSV) is by MEMS technology and Integrated circuit IC system
It makes technique and realizes the technology having with the high-density silicon package substrate of Integrated circuit IC characteristic line breadth routing capabilities, there is size
It is small, wiring density is high, is suitable for the advantages that structure 2.5D/3D encapsulation, can effectively reduce package dimension, improve packaging density,
It encapsulates integrated level, reduce transmission delay, improve electric property, the substrate being prepared is a kind of novel high-density packages lining
Bottom.George Xereas(Xereas,George,Chodavarapu,Vamsy P.Wafer-Level Vacuum-
Encapsulated LaméMode Resonator With f-Q Product of 2.23×10(13),Hz[J]
.Electron Device Letters,IEEE,2015,36(10):1079-1081.) silicon substrate air-tight packaging is used, it utilizes
Silicon cavity store MEMS chip, silicon substrate then be using ISPD fill Si-TSV, recycle Si-TSV draw transmission port to
Reach air-tight packaging.Joseph E.E.Zekry(Zekry J E E,Tezcan D S,Cherman V,et
al.Design,fabrication and testing of wafer-level thin film vacuum packages
for MEMS based on nanoporous alumina membranes[J].Sensors&Actuators
APhysical,2013,189(2):218-232.) etc. using copper TSV pinboards and the glass substrate of MEMS chip is disposed to pass through
BCB bondings, which stack, reaches air-tight packaging.
For TSV is interconnected and realized technological approaches, mainly have using W-TSV, Cu-TSV, Au-TSV, Cu-TSV etc. into
Row interconnection, there are coefficient of thermal expansion mismatch between TSV and silicon substrate, this can introduce thermal stress issues, and then to performance and reliably
Property causes risk.In order to solve thermal stress and subsidiary integrity problem, it has been disclosed that document mainly by TSV structure design with
The modes such as dimensional parameters optimization, material selection reduce TSV be electrically interconnected thermal stress, as Marella (Marella, Sravan K.,
S.V.Kumar,and S.S.Sapatnekar."Aholistic ana lysis of circuit timing
variations in 3D-ICs with thermal and TSV-induced stress co nsiderations."
IEEE/ACM International Conference on Computer-Aided Design,Diges t of
Technical Papers2012:317-324.),Jung,Moongon(Jung,Moongon,D.Z.Pan,and
S.K.Lim."Chip/package co-analysis of thermo-mechanical stress and reliabilit
y in TSV-based 3D ICs."Design Automation Conference(DAC),2012 49th ACM/EDAC/
IEEEIEEE,2012:317-326.),QW Chen(QW Chen,YY Yan,YT Ding,et al.“Fabrication and
electrical characteristics of a novel interposer with polymer line r and
silicon pillars with ultra-low-resistivity as through-silicon-vias(TSVs)for
2.5D/3D applications.”[J].Microsystem Technologies,2015,21(10):2207-2214.),
Chen(C hen,Qianwen,C.Huang,and Z.Wang."Development of ultra-low capacitance
thro ugh-silicon-vias(TSVs)with air-gap liner."Proceedings-Electronic
Components an d Technology Conference2013:1433-1438.),Steller,W(Steller W,
Meinecke C,Gottfried,K,Woldt G,W,Wolf M.J,Lang K.D.,"SIMEIT-project:
High pr ecision inertial sensor integration on a modular 3D-Interposer
platform."Electronic Components and Technology Conference(ECTC),2014IEEE 64th,
Pages:1218-1225) etc., wherein QW Chen disclose a kind of annular TSV interconnection techniques scheme of internal filling organic matter,
C hen and Steller, W etc. propose a kind of Cu TSV interconnection design technical solutions of air insulated, these methods are in certain journey
Thermal stress and integrity problem caused by can alleviating coefficient of thermal expansion mismatch on degree.But the even Cu of air insulated
TSV design, Cu TSV interconnection and substrate and surrounding dielectric material still have coefficient of thermal expansion mismatch, and cannot meet airtight
Property require, and its manufacture craft is complex.
It is therefore proposed that one kind can solve traditional air-tight packaging technology in substrate layout density, packaging density and integrate
The deficiency and defect of degree, thermal stress mismatch etc., and then realize small size, high density, the total silicon three-dimension packaging of high integration
Structure has become the technical issues of this field urgent need to resolve.
Utility model content
In order to solve above-mentioned disadvantage and deficiency, the purpose of this utility model is to provide a kind of based on the complete of silicon pinboard
Silicon 3 D encapsulating structure.
In order to achieve the above objectives, the utility model provides a kind of total silicon three-dimension packaging structure based on silicon pinboard, packet
Include silicon package substrate 100, silicon sealing cap 306 and several microelectronic chips；Wherein,
The silicon package substrate 100 is provided with several free columns 101, and 101 top of free column passes through surrounding gap and base
Plate 100 detaches, and 101 bottom end of free column realizes that fixed and insulation, the silicon encapsulate base by insulating materials and silicon package substrate 100
The upper surface 106 and lower face 108 of plate are covered each by insulating layer 103, and the surface 105 and bottom of free column top free end are fixed
There is the Ohmic contact being made of metal layer and silicon base in the surface 107 at end；
The silicon sealing cap 306 is with certain thickness shell, which is provided with pit；The silicon sealing cap 306
Upper surface 106 or the lower face 108 for being laminated in silicon package substrate are bonded by metal bonding or organic matter；
A microelectronic chip is included at least in the upper surface of the silicon package substrate 100,306 shell pit of silicon sealing cap,
The microelectronic chip is placed in the upper surface of silicon package substrate 100 in the form of upside-down mounting or formal dress.
In the total silicon three-dimension packaging structure based on silicon pinboard, it is preferable that upside-down mounting microelectronic chip passes through microbonding
Ball or microbonding point are bonded on the weld pad on the ohmic contact regions of free column top free end surface 105, are electrically connected with realizing
It connects.
In the total silicon three-dimension packaging structure based on silicon pinboard, it is preferable that formal dress microelectronic chip passes through eutectic
Bonding or conductive adhesive are assembled on the lower face 108 of silicon package substrate, and microelectronic chip is realized by wire bonding mode
With the electrical connection of 107 ohmic contact regions of surface of bottom fixing end.
In the total silicon three-dimension packaging structure based on silicon pinboard, it is preferable that the upper surface of the silicon package substrate
106 and lower face 108 be provided with metal interconnecting layer.
In the total silicon three-dimension packaging structure based on silicon pinboard, it is preferable that the metal interconnecting layer includes at least
One layer insulating and at least one layer of metallic circuit layer, ohm which fixes end surfaces 107 with free column bottom connect
There is electrical connection between touching.
In the total silicon three-dimension packaging structure based on silicon pinboard, it is preferable that the lower face of the silicon package substrate
108 are at least arranged a microelectronic chip, and the surface input/output end port of the microelectronic chip passes through microbonding ball or microbonding solid point
It is scheduled on the metal interconnecting layer of silicon package substrate lower face 108.
Total silicon three-dimension packaging structure described in the utility model based on silicon pinboard can pass through a variety of different methods
Making obtains, and in order to further be illustrated to the structure of the utility model, the utility model additionally provides described based on silicon
The production method of the total silicon three-dimension packaging structure of pinboard comprising following steps：
Step (1) is used including one or more of flip chip bonding, positive welding equipment and wire bonding method method with chip
Microelectronic chip is assembled in the upper surface of silicon package substrate to silicon package substrate disk or chip-chip form；
Step (2), with silicon sealing cap disk to silicon package substrate disk, chip-disk or chip-chip form by silicon sealing cap
It is aligned, bonds with silicon package substrate；
Step (3), using including flip chip bonding, one or more of positive welding equipment and wire bonding method method are sealed in silicon
The lower face for filling substrate assembles microelectronic chip.
In one embodiment, which further includes that the silicon sealing cap is divided into the operation of silicon sealing cap chip,
After silicon sealing cap is divided into silicon sealing cap chip, the production method of the total silicon three-dimension packaging based on silicon pinboard specifically includes
Following steps：
Step (1), using including flip chip bonding, one or more of positive welding equipment and wire bonding method method are with chip
Microelectronic chip is assembled in the upper surface of silicon package substrate to silicon package substrate disk mode (or chip-chip form)；
Step (2), in such a way that silicon sealing cap chip is to silicon package substrate disk (or chip-disk, chip-chip form)
Silicon sealing cap chip is aligned with silicon package substrate, is bonded；
Step (3), using including flip chip bonding, one or more of positive welding equipment and wire bonding method method are sealed in silicon
The lower face for filling substrate assembles microelectronic chip.
In one embodiment, which further includes that the silicon sealing cap, silicon package substrate are divided into silicon sealing cap respectively
The operation of chip and silicon package substrate chip,
After silicon sealing cap, silicon package substrate are divided into silicon sealing cap chip and silicon package substrate chip respectively, it is based on silicon pinboard
The production method of total silicon three-dimension packaging specifically include following steps：
Step (1), using including flip chip bonding, one or more of positive welding equipment and wire bonding method method are with chip
Microelectronic chip is assembled in the upper surface of silicon package substrate to the mode (or chip-chip form) of silicon package substrate chip；
Step (2), in such a way that silicon sealing cap chip is to silicon package substrate chip (or chip-disk, chip-chip form)
Silicon sealing cap is aligned with silicon package substrate, is bonded；
Step (3), using including flip chip bonding, one or more of positive welding equipment and wire bonding method method are sealed in silicon
The bottom face for filling substrate chip assembles microelectronic chip.
In one embodiment, partitioning scheme used in the production method is laser cutting or emery wheel cuts.
In one embodiment, the making of the silicon package substrate includes the following steps：
1), in the multiple annular slotted holes of the upper surface of low-resistance silicon wafer making, (those skilled in the art can be according to operation need
The hole and depth of slot are rationally set)；
2), megohmite insulant is packed into step 1) annular slotted hole cavity；
3), to the processing of the bottom face of silicon wafer progress attenuated polishing, (those skilled in the art can need to close according to operation
The thickness of silicon wafer after reason setting is thinned) after, then in side making respective annular slot until contact procedure 2) intermediate annular groove hole
The megohmite insulant filled in cavity completes the making of the free column of silicon；
4), the upper surface of silicon wafer and bottom face obtained by step 3) are covered each by insulating layer, then in silicon freedom
Insulating layer uplifting window mouth corresponding to the both ends end face of column, to expose the silicon face at the free column both ends of silicon；
5) it is free in the free column of silicon after, the upper surface of silicon wafer and bottom face obtained by step 4) prepare metal layer respectively
End face and the free column of silicon fix on end face the Ohmic contact formed between silicon and metal；
6), the upper surface of the silicon wafer obtained by step 5) makes Bonded Ring and the free column of silicon is made to be respectively positioned on the bonding
In ring, the making of silicon package substrate is completed.
In the manufacturing process of the silicon package substrate, the bottom face of the silicon wafer refers to without ring described in step 1)
The face of shape slot；It is respectively towards silicon wafer upper surface and bottom end that the free column free end face of the silicon and the free column of silicon, which fix end face,
The free styletable face of silicon in face.
Wherein, the utility model does not do specific requirement to low-resistance silicon wafer, and those skilled in the art can make according to scene
Industry needs to select suitable low-resistance silicon wafer, and in specific embodiment of the present invention, silicon wafer used is resistivity≤0.1
The silicon wafer of Ω cm.
According to the utility model specific embodiment, in the manufacturing process step 1), step 3) of the silicon package substrate,
Using deep reaction ion etching method (Deep Reactive Ion Etching, DRIE), laser boring method in low-resistance silicon wafer
Upper making annular slotted hole.Wherein, the deep reaction ion etching method and laser boring method are the routine side that this field uses
Method.
In the manufacturing process step 2) of the silicon package substrate, using including plasma enhanced chemical vapor deposition method
(PECVD), megohmite insulant is packed into step 1) by least one of chemical vapour deposition technique (CVD) and vacuum glue pouring method method
In annular slotted hole cavity.Wherein, plasma enhanced chemical vapor deposition method, chemical vapour deposition technique and vacuum glue pouring method are
The conventional method that this field uses.
In the manufacturing process step 2) of the silicon package substrate, the megohmite insulant includes silica, silicon nitride, oxygen
Change aluminium, benzocyclobutene (BCB), polyimides (PI), glass paste, polypropylene (polypropylene) or Parylene
(Poly-p-xylene)。
In the manufacturing process step 3) of the silicon package substrate, the attenuated polishing processing is using mechanical reduction method, machine
Tool chemical polishing (CMP) is realized.Wherein, mechanical reduction method, chemical mechanical polishing method are the conventional method that this field uses.
In the manufacturing process step 4) of the silicon package substrate, the covering insulating layer using include oxidizing process, etc. from
Daughter enhances at least one of chemical vapour deposition technique, chemical vapour deposition technique, spin-coating method and spray coating method method and realizes.Its
In, the oxidizing process, plasma enhanced chemical vapor deposition method, chemical vapour deposition technique, spin-coating method and spray coating method are this
The conventional method that field uses.
It is described exhausted corresponding to the both ends end face of the free column of silicon in the manufacturing process step 4) of the silicon package substrate
Edge layer uplifting window mouth using include reactive ion etching method, plasma etching method (sense coupling method) and
At least one of wet etching method method is realized.Wherein, the reactive ion etching method, sense coupling
Method, plasma etching method and wet etching method are the conventional method that this field uses.
In the manufacturing process step 5) of the silicon package substrate, the metal layer includes TiW layers, aluminium layer, layers of copper and gold
Layer in one or more layers；
Further, the preparation of the metal layer is realized using at least one of sputtering, evaporation, plating method.Wherein,
Sputtering, evaporation, plating are conventional method that this field uses.
In the manufacturing process step 5) of the silicon package substrate, pass through the works such as wet chemical etching technique, dry etching, stripping
At least one of skill realizes that ohm between the silicon-metal that the free column free end face of silicon and the free column of silicon are fixed on end face connects
It touches.Wherein, the techniques such as wet chemical etching technique, dry etching, stripping are the conventional method that this field uses.
In the manufacturing process step (6) of the silicon package substrate, it includes gold, copper and tin to make binding material used in Bonded Ring
Any one of alloy, gold-tin alloy, silver-tin alloy, benzocyclobutene, polyimides or epoxy resin.
In one embodiment, the making of the silicon sealing cap includes the following steps：
1, silicon wafer is provided, pit is made on the substrate of the silicon wafer；
2, Bonded Ring corresponding with the Bonded Ring of silicon package substrate is made in the dimpled side of silicon wafer band, completes silicon
The making of sealing cap.
In the manufacturing process of the silicon package substrate, according to the size of silicon package substrate and the number of the free column of silicon, position
Making pit is set, to ensure that the pit can be by the free column cladding of the silicon wherein.
According to the utility model specific embodiment, in the manufacturing process step 1 of the silicon sealing cap, the pit uses
Any one of wet etching, dry etching or laser boring method is formed.Wherein, the wet etching, dry etching or sharp
Light punching is the conventional method that this field uses.
In the manufacturing process step 2 of the silicon sealing cap, make Bonded Ring used in binding material include gold, copper-tin alloy,
Any one of gold-tin alloy, silver-tin alloy, benzocyclobutene, polyimides or epoxy resin.
In the total silicon three-dimension packaging structure, the silicon package substrate is the substrate made of low-resistance silicon materials, wherein
The Ω cm of the resistivity of the low-resistance silicon materials≤0.1.
Technical solution provided by the utility model can solve traditional air-tight packaging technology in substrate layout density, envelope
Insufficient and defect existing in terms of dress density, integrated level, thermal stress mismatch, meanwhile, what the utility model was proposed should be based on newly
The total silicon three-dimensional packaging technology of type silicon pinboard can realize small size, high density, high integration, the total silicon three-dimensional of low stress envelope
Dress.
It is provided by the utility model based on the total silicon three-dimension packaging method of silicon pinboard by using air insulated low-resistance
As conductive channel coefficient of thermal expansion mismatch is not present, and then fundamentally avoid tradition in silicon column between silicon column and silicon substrate
TSV transfer plate technique in as between Cu, Au, W and silicon substrate there are coefficient of thermal expansion mismatch and caused by thermal stress issues.
Further, the free column of the silicon of air insulated can provide stress buffer for the microelectronic chip being disposed thereon and release
Mechanism is put, the free column of air insulated silicon can deform upon when packaging body undergoes temperature change, and then make microelectronics core thereon
Piece is influenced from thermal stress, realizes low stress three-dimension packaging.
Further, total silicon encapsulates compatible various chips, the electronic chip of flexible Application different model, MEMS chip
Deng and manufacture craft simple possible.
Description of the drawings
Fig. 1 is the vertical view of silicon package substrate provided by the utility model (carrying silicon sealing cap)；
Fig. 2 is the vertical view of silicon package substrate provided by the utility model；
Fig. 3 is the Section A-A structural schematic diagram of silicon package substrate provided by the utility model (carrying silicon sealing cap)；
Fig. 4 a are the close-up schematic view of B1 in Fig. 3；
Fig. 4 b are the close-up schematic view of B2 in Fig. 3；
Fig. 5 is the upward view of silicon package substrate provided by the utility model；
Fig. 6 is the structural schematic diagram of the total silicon three-dimension packaging provided by the utility model based on silicon pinboard；
Fig. 7 is the structural schematic diagram of the total silicon three-dimension packaging provided by the utility model based on silicon pinboard；
Fig. 8 is the process flow chart of the total silicon three-dimension packaging method provided by the utility model based on silicon pinboard；
Fig. 9 is the process flow chart of the total silicon three-dimension packaging method provided by the utility model based on silicon pinboard；
Figure 10 is the process flow chart of the total silicon three-dimension packaging method provided by the utility model based on silicon pinboard；
Figure 11 is the process flow chart of the total silicon three-dimension packaging method provided by the utility model based on silicon pinboard；
Figure 12 is the process flow chart of the total silicon three-dimension packaging method provided by the utility model based on silicon pinboard；
Figure 13 is the process flow chart of the total silicon three-dimension packaging method provided by the utility model based on silicon pinboard；
Figure 14 is the process flow chart of the total silicon three-dimension packaging method provided by the utility model based on silicon pinboard；
Figure 15 is the process flow chart of the total silicon three-dimension packaging method provided by the utility model based on silicon pinboard.
Main Reference label：
100 substrates, 101 free columns, 102 insulating materials, 103 insulating layers, 104 metal layers, 105 free column free ends table
Face, 106 silicon package substrate upper surfaces, the surface of 107 free column fixing ends, 108 silicon package substrate lower faces, 109 free columns are certainly
By end, 110 free column fixing ends, 111 Bonded Rings；
201 soldered balls, 202 lower layer's microelectronic chips；
300M metal-silicons Ohmic contact, 301 weld pads, solder joint etc., 302 upper layer microelectronic chips, 303 metal interconnecting layers,
306 silicon sealing caps.
Specific implementation mode
In order to which the technical characteristics of the utility model, purpose and advantageous effect are more clearly understood, in conjunction with following
Specific embodiment the technical solution of the utility model is carried out it is described further below, but should not be understood as to the utility model can
The restriction of practical range.
Embodiment 1
Present embodiments provide a kind of total silicon three-dimension packaging method based on silicon pinboard, process flow chart such as Fig. 8-figure
Shown in 15, this approach includes the following steps：
(A) making of silicon package substrate 100：
1) a low-resistance silicon wafer is provided, thickness is about 400 microns, passes through deep reaction ion etching (Deep
Reactive Ion Etching, DRIE), the technologies such as laser the silicon wafer is performed etching, obtain annular blind hole, hole is about
20 microns, depth is 60 microns, is prepared to form free column 101, as shown in Figure 8.
2) by physical vacuum encapsulating by insulating materials silica (SiO2, SiOx) and it 102 is filled in annular slotted hole cavity,
As shown in Figure 9.
3) reduction processing is carried out to the wafer described in step 2 by mechanical reduction, chemical mechanical polishing (CMP) technology,
The low-resistance silicon wafer of 250 micron thickness is obtained, then respective rings are made in substrate annular groove opposite side by DRIE, processing technology
Shape slot, depth are about 190 microns, and the free column of silicon 101 completes, as shown in Figure 10.
4) one layer of 1.5 microns of insulating layer 103 are covered on the wafer by chemical method PECVD described in step 3；Pass through
Chemical method wet etching cylinder both ends end face insulating layer uplifting window mouth on a wafer, exposes cylinder both ends silicon face, institute
Both ends as free column free end 109 and free column fixing end 110 are stated, as shown in figure 11.
5) metal layer 104 is prepared by sputtering method, metal layer is layers of copper, and thickness is 5 microns, then passes through wet chemistry corruption
The Ohmic contact on the surface 105 of the free column free end of silicon and the surface 107 of fixing end is realized in erosion, stripping technology, and base is encapsulated in silicon
Plate upper surface 106 makes Bonded Ring 111, which is 200 nanometers, and 111 material of Bonded Ring is golden tin solder layer, is such as schemed
Shown in 12；
Wherein, the vertical view for the silicon package substrate that the present embodiment is prepared is as shown in Fig. 2, upward view is as shown in Figure 5.
(B) making of silicon sealing cap 306：
1) silicon wafer is provided, thickness is more than 400 microns, by one kind of wet etch techniques on silicon wafer substrate
Pit is made, depth is 400 microns；
The silicon sealing cap 306 is aligned with silicon package substrate 100, is bonded, vertical view is as shown in Figure 1, Section A-A structure is shown
Be intended to as shown in figure 3, the close-up schematic view of B1, B2 in Fig. 3 as shown in Figs. 4 a-b.
2) Bonded Ring 111 corresponding with silicon package substrate 100 is made on surface where silicon wafer pit, thickness is about 200
Nanometer, 111 material of Bonded Ring are golden tin solder layer.
(C) making of the total silicon three-dimension packaging based on silicon package substrate：
1) after silicon sealing cap disk completes, which is divided into silicon sealing cap chip, partitioning scheme is cut for grinding wheel
It cuts；By face-down bonding technique by chip to disposing the micro- electricity in upper layer in silicon package substrate upper surface 106 in a manner of silicon package substrate disk
Sub- chip 302, chip thickness are less than 390 microns；As shown in figure 13.
2) in such a way that silicon sealing cap chip is to silicon package substrate disk that 306 chip of silicon sealing cap and silicon package substrate 100 is right
Standard bonds, wherein welding temperature is 300 DEG C, pressure 20kg, as shown in figure 14.
3) lower layer's microelectronic chip 202 is disposed in the lower face of silicon package substrate 108 with face-down bonding technique, such as Figure 15, Fig. 6
It is shown.
Embodiment 2
A kind of total silicon three-dimension packaging based on silicon pinboard is present embodiments provided, is prepared by the method for embodiment 1
It obtains, the structural schematic diagram of the total silicon three-dimension packaging is as shown in fig. 6, from fig. 6 it can be seen that it includes
Silicon package substrate, silicon sealing cap and three microelectronic chips；Wherein,
The silicon package substrate setting is there are six free column, and free top end is detached by surrounding gap with substrate, freely
Column bottom end fixed and insulation, the upper surface and lower face point of the silicon package substrate are realized by insulating materials and silicon package substrate
A layer insulating is not covered, and the surface presence of free column top free end and bottom fixing end is made of metal layer and silicon base
Ohmic contact；
The silicon sealing cap is with certain thickness shell, which is provided with pit；The silicon sealing cap passes through gold
Belong to the upper surface that bonding is laminated in silicon package substrate；
The upper surface of the silicon package substrate, interior silicon sealing cap shell pit include two microelectronic chips, the microelectronics
Chip is placed in the upper surface of silicon package substrate with flip-chip fashion.
Upside-down mounting microelectronic chip is bonded to by microbonding point 301 on the weld pad on the ohmic contact regions of free column free end
Realize electrical connection；
The characteristics of microelectronic chip is connected by soldered ball 201, is also had and is attached by pad, and soldered ball connects is that he needs
Soldered ball is used, and soldered ball is much larger relative to pad volume, pad only needs golden on microelectronic chip or on pinboard
Belonging to layer, locally thickening is bonded to obtain.
Embodiment 3
Present embodiments provide a kind of total silicon three-dimension packaging method based on silicon pinboard, process flow chart such as Fig. 8-figure
Shown in 15, this approach includes the following steps：
(A) making of silicon package substrate 100：
1) a low-resistance silicon wafer is provided, thickness is about 400 microns, passes through deep reaction ion etching (Deep
Reactive Ion Etching, DRIE), the technologies such as laser the silicon wafer is performed etching, obtain annular blind hole, hole is about
20 microns, depth is 60 microns, is prepared to form free column 101, as shown in Figure 8.
2) by physical vacuum encapsulating by silica (SiO2, SiOx) and it is filled in annular slotted hole cavity, as shown in Figure 9.
3) reduction processing is carried out to the wafer described in step 2 by mechanical reduction, chemical mechanical polishing (CMP) technology,
The low-resistance silicon wafer of 250 micron thickness is obtained, then respective rings are made in substrate annular groove opposite side by DRIE, processing technology
Shape slot, depth are about 190 microns, and the free column of silicon 101 completes, as shown in Figure 10.
4) one layer of 1.5 microns of insulating layer 102 are covered on the wafer by chemical method PECVD described in step 3；Pass through
Chemical method wet etching cylinder both ends end face insulating layer uplifting window mouth on a wafer, exposes cylinder both ends silicon face, such as
Shown in Figure 11.
5) metal layer 104 is prepared by sputtering method, metal layer is layers of copper, and thickness is 5 microns, then passes through wet chemistry corruption
The Ohmic contact of the free column free end face 109 of silicon and fixed end face 110 is realized in erosion, stripping technology, in silicon package substrate upper surface
106 make Bonded Ring 111, which is 200 nanometers, and 111 material of Bonded Ring is golden tin solder layer, as shown in figure 12.
(B) making of silicon sealing cap 306：
1) silicon wafer is provided, thickness is more than 400 microns, by one kind of wet etch techniques on silicon wafer substrate
Pit is made, depth is 400 microns；
2) Bonded Ring 111 corresponding with silicon package substrate 100 is made on surface where silicon wafer pit, thickness is about 200
Nanometer, 111 material of Bonded Ring are golden tin solder layer.
(C) making of the total silicon three-dimension packaging based on silicon package substrate：
1) after silicon sealing cap disk completes, which is divided into silicon sealing cap chip, partitioning scheme is cut for grinding wheel
It cuts；By soldered ball 304 by chip to disposing upper layer microelectronics core in silicon package substrate upper surface 10 in a manner of silicon package substrate disk
Piece 302, chip thickness are less than 390 microns；As shown in figure 13.
2) in such a way that silicon sealing cap chip is to silicon package substrate disk that 306 chip of silicon sealing cap and silicon package substrate 100 is right
Standard bonds, wherein welding temperature is 300 DEG C, pressure 20kg, as shown in figure 14.
3) lower layer's microelectronic chip 202 is disposed in the lower face of silicon package substrate 108 with face-down bonding technique, as shown in Figure 7.
Embodiment 4
A kind of total silicon three-dimension packaging based on silicon pinboard is present embodiments provided, is prepared by the method for embodiment 3
It obtains, the structural schematic diagram of the total silicon three-dimension packaging is as shown in fig. 7, it can be seen from figure 7 that it includes
Silicon package substrate, silicon sealing cap and three microelectronic chips；Wherein,
The silicon package substrate setting is there are six free column, and free top end is detached by surrounding gap with substrate, freely
Column bottom end fixed and insulation, the upper surface and lower face point of the silicon package substrate are realized by insulating materials and silicon package substrate
Do not cover a layer insulating, the surface of free column top free end and bottom fixing end exists by metal interconnecting layer 303 and silicon
The Ohmic contact 300 that substrate is constituted；
The silicon sealing cap is with certain thickness shell, which is provided with pit；The silicon sealing cap passes through gold
Belong to the upper surface that bonding is laminated in silicon package substrate；
The upper surface of the silicon package substrate, interior silicon sealing cap shell pit include two microelectronic chips, the microelectronics
Chip is placed in the upper surface of silicon package substrate in the form of upside-down mounting or formal dress；
Upside-down mounting microelectronic chip is bonded to by microbonding ball or microbonding point on the ohmic contact regions of free column free end
Electrical connection is realized on weld pad；Formal dress microelectronic chip is assembled in silicon package substrate substrate by eutectic bonding or conductive adhesive
On, the electrical connection of microelectronic chip and free styletable face ohmic contact regions is realized by wire bonding mode；
Flip-chip fashion is used in sealing cap, that is, needs two faces to be aligned, is bonded, and bottom can pass through formal dress shape
Formula, wire bonding, while can also be attached with flip-chip fashion.
Claims (6)
1. a kind of total silicon three-dimension packaging structure based on silicon pinboard comprising silicon package substrate (100), silicon sealing cap (306) and
Several microelectronic chips；It is characterized in that,
The silicon package substrate (100) is provided with several free columns (101), free column (101) top by surrounding gap with
Silicon package substrate (100) separation, free column (101) bottom end are realized fixed and exhausted by insulating materials and silicon package substrate (100)
Edge, the upper surface (106) and lower face (108) of the silicon package substrate are covered each by insulating layer (103), and free column top is free
There is the Ohmic contact being made of metal layer and silicon base in the surface (105) at end and the surface (107) of bottom fixing end；
The silicon sealing cap (306) is with certain thickness shell, which is provided with pit；The silicon sealing cap (306)
Upper surface (106) or lower face (108) for being laminated in silicon package substrate are bonded by metal bonding or organic matter；
A microelectronic chip is included at least in the upper surface of the silicon package substrate (100), silicon sealing cap (306) shell pit,
The microelectronic chip is placed in the upper surface of silicon package substrate (100) in the form of upside-down mounting or formal dress.
2. the total silicon three-dimension packaging structure according to claim 1 based on silicon pinboard, which is characterized in that upside-down mounting microelectronics
Chip is bonded to the weld pad on the ohmic contact regions on the surface (105) of free column top free end by microbonding ball or microbonding point
On, to realize electrical connection.
3. the total silicon three-dimension packaging structure according to claim 1 based on silicon pinboard, which is characterized in that formal dress microelectronics
Chip is assembled in by eutectic bonding or conductive adhesive on the lower face (108) of silicon package substrate, and wire bonding mode is passed through
Realize the electrical connection of microelectronic chip and surface (107) ohmic contact regions of bottom fixing end.
4. the total silicon three-dimension packaging structure according to claim 1 based on silicon pinboard, which is characterized in that the silicon encapsulation
The upper surface (106) and lower face (108) of substrate are provided with metal interconnecting layer.
5. the total silicon three-dimension packaging structure according to claim 4 based on silicon pinboard, which is characterized in that the metal is mutual
Even layer includes at least one layer of insulating layer and at least one layer of metallic circuit layer, the table of the metallic circuit layer and free column bottom fixing end
There is electrical connection between the Ohmic contact in face (107).
6. the total silicon three-dimension packaging structure according to claim 4 or 5 based on silicon pinboard, which is characterized in that the silicon
A microelectronic chip is at least arranged in the lower face (108) of package substrate, and the surface input/output end port of the microelectronic chip is logical
It crosses microbonding ball or microbonding point is fixed on the metal interconnecting layer of lower face (108) of silicon package substrate.
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| CN201721745006.7U CN207671684U (en) | 2017-12-14 | 2017-12-14 | A kind of total silicon three-dimension packaging structure based on silicon pinboard |
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