CN110010481A - A kind of hermetic type system-level photoelectric module packaged type and technique - Google Patents
A kind of hermetic type system-level photoelectric module packaged type and technique Download PDFInfo
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- CN110010481A CN110010481A CN201811176859.2A CN201811176859A CN110010481A CN 110010481 A CN110010481 A CN 110010481A CN 201811176859 A CN201811176859 A CN 201811176859A CN 110010481 A CN110010481 A CN 110010481A
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- 238000000034 method Methods 0.000 title claims abstract description 75
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims abstract description 46
- 238000005538 encapsulation Methods 0.000 claims abstract description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 51
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 51
- 229910052802 copper Inorganic materials 0.000 claims description 51
- 239000010949 copper Substances 0.000 claims description 51
- 229910052710 silicon Inorganic materials 0.000 claims description 51
- 239000010703 silicon Substances 0.000 claims description 51
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 48
- 238000001259 photo etching Methods 0.000 claims description 40
- 230000008569 process Effects 0.000 claims description 36
- 239000000463 material Substances 0.000 claims description 35
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 28
- 229910052751 metal Inorganic materials 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 28
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 24
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 24
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 24
- 239000004411 aluminium Substances 0.000 claims description 24
- 229910052782 aluminium Inorganic materials 0.000 claims description 24
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 24
- 229910052759 nickel Inorganic materials 0.000 claims description 24
- 229910052709 silver Inorganic materials 0.000 claims description 24
- 239000004332 silver Substances 0.000 claims description 24
- 229910052718 tin Inorganic materials 0.000 claims description 24
- 239000011135 tin Substances 0.000 claims description 24
- 238000009713 electroplating Methods 0.000 claims description 21
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 19
- 229910052737 gold Inorganic materials 0.000 claims description 19
- 239000010931 gold Substances 0.000 claims description 19
- 238000005516 engineering process Methods 0.000 claims description 18
- 239000013307 optical fiber Substances 0.000 claims description 14
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 12
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 12
- 229910052763 palladium Inorganic materials 0.000 claims description 12
- 229910052716 thallium Inorganic materials 0.000 claims description 12
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 claims description 12
- 239000010936 titanium Substances 0.000 claims description 12
- 229910052719 titanium Inorganic materials 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- 239000011521 glass Substances 0.000 claims description 9
- 239000007769 metal material Substances 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 238000003466 welding Methods 0.000 claims description 7
- 238000005520 cutting process Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 230000005496 eutectics Effects 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 5
- 229920005989 resin Polymers 0.000 claims description 5
- 239000011347 resin Substances 0.000 claims description 5
- 238000004544 sputter deposition Methods 0.000 claims description 5
- 238000000280 densification Methods 0.000 claims description 4
- 239000003822 epoxy resin Substances 0.000 claims description 4
- 230000008020 evaporation Effects 0.000 claims description 4
- 238000001704 evaporation Methods 0.000 claims description 4
- 229920000647 polyepoxide Polymers 0.000 claims description 4
- 239000010453 quartz Substances 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000007797 corrosion Effects 0.000 claims description 3
- 238000005260 corrosion Methods 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 239000004814 polyurethane Substances 0.000 claims description 3
- 229920002635 polyurethane Polymers 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 2
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 238000003698 laser cutting Methods 0.000 claims description 2
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 31
- 239000013078 crystal Substances 0.000 description 8
- 230000003287 optical effect Effects 0.000 description 5
- 230000005855 radiation Effects 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 238000012163 sequencing technique Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- JOYRKODLDBILNP-UHFFFAOYSA-N Ethyl urethane Chemical compound CCOC(N)=O JOYRKODLDBILNP-UHFFFAOYSA-N 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 230000002528 anti-freeze Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4817—Conductive parts for containers, e.g. caps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/8121—Applying energy for connecting using a reflow oven
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a kind of hermetic type system-level photoelectric module packaged type and technique, include the following steps: 101) pedestal processing step, 102) cover board processing step, 103) encapsulation step；The present invention provides batch making, cost relatively before a kind of hermetic type system-level photoelectric module packaged type that substantially reduces of packaged type and technique.
Description
Technical field
The present invention relates to technical field of semiconductors, more specifically, it is related to a kind of hermetic type system-level photoelectric module envelope
Dress mode and technique.
Background technique
The load of usual Seeds of First Post-flight has phased-array radar, high definition camera, inertial navigation and various kinds of sensors, with load
Performance is gradually increased, and the rate requirement of data transmission is gradually increased, and fiber count is passed due to light-weight, electromagnetic shielding
Characteristic is good, message capacity is big, is easy to be multiplexed the advantages that integrated, becomes the favorable substitutes of data transmission medium-high frequency cable.
But in certain specific environments, harsh overheat or excessively cool condition and unknown radiation can be seriously affected
Induction and transmission of the optical chip to photon in optical fiber, or even fatal harm is brought to the optical chip of high speed operation.For such
Optical module can generally make of radiation-resistant optical fiber, but for optical chip, then need to carry out it by sealing technology
Protection, makes it have the functions such as heat-insulated antifreeze and radiation protection.
To guarantee that air-tightness, traditional method are to use ceramic substrate, pcb board etc. is beaten the functional chip of module by pasting
The mode of line is welded, and is then sealed with glue, reach isolation external environment purpose, but at present for, symbol
Can the glue that the requirement be closed be less, and cannot be completely secured and also play a role under more harsh environment.
Summary of the invention
The present invention overcomes the deficiencies in the prior art, provide batch making, cost relatively before packaged type substantially reduce
A kind of hermetic type system-level photoelectric module packaged type and technique.
Technical scheme is as follows:
A kind of hermetic type system-level photoelectric module packaged type and technique, specific processing include the following steps:
101) pedestal processing step: silicon hole is made by photoetching and dry etch process in susceptor surface, silicon hole depth is in 10nm
To 800um, silicon hole shape be it is rectangular, trapezoidal or cylindrical, side length or diameter range between 10um to 40000um,
The pedestal surface deposits translucent material, and so that deposition translucent material is only left at silicon hole by CMP process, and translucent material is oxidation
Silicon, organic resin or organic glass；
Pad is made by photoetching and electroplating technique on another surface of pedestal, pad thickness range is in 1nm to 100um, pad
This body structure is one or more layers, and the metal material of pad uses one of titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel or more
Kind；Groove is made by photoetching and dry etch process on the pedestal surface, depth is between 10nm to 800um, groove
Shape be it is rectangular, trapezoidal, cylindrical, side length or diameter range are between 10um to 40000um；
102) cover board processing step: cover board makes the hole TSV in lid surface by photoetching, etching technics, and TSV bore dia range exists
1um to 1000um, depth is in 10um to 1000um；Square cvd silicon oxide or silicon nitride or directly thermal oxidation shape on the cover board
At insulating layer, thickness of insulating layer range is existed between 10nm to 100um by physical sputtering, magnetron sputtering or evaporation process
Seed layer is made above insulating layer, for seed layer thickness range in 1nm to 100um, this body structure of seed layer is one or more layers, is planted
The metal material of sublayer uses one or more of titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel；By electro-coppering, make copper
Metal is full of the hole TSV, and densification copper at a temperature of 200 to 500 degree, makes silicon chip surface only be left to fill out copper formation copper with CMP process
Column；
RDL is made on the surface of cover board, process includes production respective insulation layers, and thickness of insulating layer range is arrived in 10nm
1000um, material are silica or silicon nitride, are opened a window by photoetching, dry etch process, RDL is enable to connect with copper post one end
It connects, then RDL is made in lid surface by photoetching, electroplating technology, RDL includes cabling and bonding；
Bond wire is made in lid surface and is formed by photoetching, electroplating technology, and pad height range is in 10nm to 1000um, key
Alloy, which belongs to, uses copper, and aluminium, nickel, silver, gold, one of tin or a variety of, this body structure of bond wire is one or more layers；It welds herein
Disk and RDL are located at the same face of copper post exposing；
The another side of cover board is carried out it is thinned, pass through photoetching, electroplating technology make metal pad；Thickness range is arrived in 1nm
100um, this body structure of metal pad are one or more layers, and the material of metal pad is titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel
One of or it is a variety of；
103) encapsulation step: pass through the technique welding function chip of eutectic bonding on cover board pad, function is made by routing technique
The PAD of energy chip is interconnected with the pad of cover board wafer, is bonded in the one side of pedestal and cover board in such a way that wafer scale is bonded
Together, other function chip is placed in the another side of pedestal surface mount process；Bonded wafer is cut into single Encapsulation Moulds
Group, and single encapsulation module is inserted into optical fiber, it is passed through optical fiber and completes light-path.
Further, cover board, pedestal use unified size, use one of 4,6,8,12 cun sizes, thickness model
It encloses for 200um to 2000um, material uses silicon wafer, glass, quartz, silicon carbide, aluminium oxide, epoxy resin or polyurethane.
Further, the surface insulation layer dry etching of cover board or wet corrosion technique removal.
Further, insulating layer is covered on the surface RDL, open a window exposed pad on the insulating layer；The metal of RDL uses herein
One or more of copper, aluminium, nickel, silver, gold, tin, this body structure of RDL use one or more layers, and the thickness range of RDL is
10nm to 1000um；Pad opens a window diameter as 10um to 10000um.
Further, cutting mode is located at pit and is filled out copper position using laser cutting or cutter cutting, cutting position
It is intermediate.
Further, step 103) bonding temperature is between 200 to 500 degree.
Advantage is the present invention compared with prior art: the present invention makes capping and the support plate of sealing of silicon pinboard,
Chip is fixed on support plate by welding, is then packaged by the technique of metal bonding, while being passed with light
The insulating layer for leading effect blocks the hole of module transfer light, and the chip in module is made to achieve the effect that be fully sealed.This technique is not
The problem of being easy with worry organic gel by intense radiation accelerated ageing, and can be with batch making, packaged type of the cost compared with before is big
It is big to reduce.
Detailed description of the invention
Fig. 1 is the cross-sectional view of the structure that pedestal of the invention makes silicon hole；
Fig. 2 is the cross-sectional view of the structure of pedestal of the invention；
Fig. 3 is the cross-sectional view of the structure of cover board of the invention；
Fig. 4 is the cross-sectional view of the structure of pedestal and cover board of the invention；
Fig. 5 is cross-sectional view of the structure of the invention；
Fig. 6 is the cross-sectional view of the structure that second of pedestal of the invention makes silicon hole；
Fig. 7 is the cross-sectional view of the structure that chip is arranged on the pedestal of Fig. 6 of the invention；
Fig. 8 is the cross-sectional view of the structure of second of cover board of the invention；
Fig. 9 is the cross-sectional view of the structure that Fig. 7 of the invention and Fig. 8 is combined；
Figure 10 is second of cross-sectional view of the structure of the invention.
It is identified in figure: pedestal 101, silicon hole 102, groove 103, cover board 201, functional chip 202, metal layer 203, cavity
204, other function chip 301, optical fiber 401.
Specific embodiment
Embodiments of the present invention are described below in detail, in which the same or similar labels are throughly indicated identical or classes
As element or the element of similar functions.It is exemplary below with reference to the embodiment of attached drawing description, is only used for explaining
The present invention and cannot function as limitation of the present invention.
Those skilled in the art can understand that unless otherwise defined, all terms used herein (including skill
Art term and scientific and technical terminology) there is meaning identical with the general understanding of those of ordinary skill in fields of the present invention.Also
It should be understood that those terms such as defined in the general dictionary should be understood that have in the context of the prior art
The consistent meaning of meaning, and unless definition as here, will not be explained in an idealized or overly formal meaning.
The label about step mentioned in each embodiment, it is only for the convenience of description, without substantial
The connection of sequencing.Different step in each specific embodiment can carry out the combination of different sequencings, realize this hair
Bright goal of the invention.
The present invention is further described with reference to the accompanying drawings and detailed description.
Embodiment 1:
As shown in Figures 1 to 5, a kind of hermetic type system-level photoelectric module packaged type and technique, specific processing include following step
It is rapid:
101) silicon hole 102, silicon hole 101 processing step of pedestal: are made by photoetching and dry etch process on 101 surface of pedestal
102 depth in 10nm to 800um, 102 shape of silicon hole be it is rectangular, trapezoidal or cylindrical, side length or diameter range are in 10um
To between 40000um, translucent material is deposited on the surface of pedestal 101, and so that deposition translucent material is only left at silicon by CMP process
Hole 102, translucent material are silica, organic resin or organic glass.
Pad is made by photoetching and electroplating technique on another surface of pedestal 101, pad thickness range is arrived in 1nm
100um, this body structure of pad are one or more layers, and the metal material of pad is using in titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel
It is one or more.Groove 103 is made by photoetching and dry etch process on the surface of pedestal 101, depth is in 10nm
To between 800um, 103 shape of groove be it is rectangular, trapezoidal, cylindrical, side length or diameter range 10um to 40000um it
Between.
It is i.e. specific as shown in Figure 1, the crystal column surface in pedestal 101 makes silicon hole 102 by photoetching and dry etch process,
For 102 depth of silicon hole in 10nm to 800um, 102 shape of silicon hole can be rectangular, trapezoidal, cylinder etc., side length or diameter model
It is trapped among 10um to 40000um.
The pedestal 101 of this step includes 4,6,8,12 cun of wafers, and thickness range is 200um to 2000um, generally uses silicon
Piece is also possible to other materials, including glass, and quartz, silicon carbide, the inorganic material such as aluminium oxide are also possible to epoxy resin, gathers
The organic materials such as urethane, major function are to provide supporting role.
On 101 surface of pedestal by deposition translucent material, silica, organic resin can be, organic glass etc. passes through
CMP removes excess surface material, leaves behind substance in silicon hole 102.
As shown in Fig. 2, the crystal column surface in pedestal 101 makes pad, pad thickness model by photoetching and electroplating technique
Be trapped among 1nm to 100um, can be one layer and be also possible to multilayer, metal material can be titanium, copper, aluminium, silver, palladium, gold, thallium,
Tin, nickel etc..
Groove 103 is made by photoetching and dry etch process in the crystal column surface of pedestal 101, depth is arrived in 10nm
800um, 103 shape of groove can be rectangular, and trapezoidal, cylinder etc., side length or diameter range are in 10um to 40000um.
102) 201 processing step of cover board: cover board 201 makes the hole TSV on 201 surface of cover board by photoetching, etching technics,
TSV bore dia range is in 1um to 1000um, and depth is in 10um to 1000um.In 201 disposed thereon silica of cover board or nitridation
Silicon or directly thermal oxidation form insulating layer, and thickness of insulating layer range passes through physical sputtering, magnetic control between 10nm to 100um
Sputtering or evaporation process just make seed layer on the insulating layer, and seed layer thickness range is in 1nm to 100um, seed layer itself
Structure is one or more layers, and the metal material of seed layer uses one of titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel or more
Kind.By electro-coppering, make copper metal full of the hole TSV, and densification copper at a temperature of 200 to 500 degree, makes silicon wafer table with CMP process
Only it is left to fill out copper formation copper post in face.
RDL is made on the surface of cover board 201, process includes production respective insulation layers, and thickness of insulating layer range is in 10nm
To 1000um, material is silica or silicon nitride, is opened a window by photoetching, dry etch process, enables RDL and copper post one end
Connection, then RDL is made on 201 surface of cover board by photoetching, electroplating technology, RDL includes cabling and bonding.
Bond wire is made on 201 surface of cover board and is formed by photoetching, electroplating technology, and pad height range is arrived in 10nm
1000um, bond wire use copper, and aluminium, nickel, silver, gold, one of tin or a variety of, this body structure of bond wire is one layer or more
Layer.Pad and RDL are located at the same face of copper post exposing herein.
The another side of cover board 201 is carried out it is thinned, pass through photoetching, electroplating technology make metal pad.Thickness range is in 1nm
To 100um, this body structure of metal pad is one or more layers, the material of metal pad be titanium, copper, aluminium, silver, palladium, gold, thallium, tin,
One of nickel is a variety of.
It is i.e. specific that as shown in figure 3, the wafer in cover board 201 passes through photoetching, etching technics makes the hole TSV in silicon chip surface,
TSV bore dia range is in 1um to 1000um, and depth is in 10um to 1000um.In 201 disposed thereon silica of cover board or nitridation
The insulating layers such as silicon or directly thermal oxidation, thickness of insulating layer range is between 10nm to 100um.By physical sputtering, magnetic control splashes
It penetrates or evaporation process just makes seed layer on the insulating layer, seed layer thickness range can be one layer in 1nm to 100um
It is also possible to multilayer, metal material can be titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel etc..
By electro-coppering, make copper metal full of the hole TSV, densification keeps copper finer and close at a temperature of 200 to 500 degree.Copper CMP work
Skill removes silicon chip surface copper, and silicon chip surface is made only to be left to fill out copper to form copper post.Silicon chip surface insulating layer can use dry method
Etching or wet corrosion technique removal.Silicon chip surface insulating layer can also retain.
RDL is made on the surface of cover board 201, process includes production insulating layer, and thickness of insulating layer range is arrived in 10nm
1000um, material can be silica or silicon nitride.By photoetching, dry etch process windowing makes RDL and copper post one end
Connection.By photoetching, electroplating technology makes RDL in silicon chip surface.RDL includes cabling and key function.
Insulating layer can also be covered again on the surface RDL, open a window exposed pad on the insulating layer.RDL metal can be herein
Copper, aluminium, nickel, silver, gold, the materials such as tin, this body structure of insulating layer can be one layer and be also possible to multilayer, thickness range 10nm
To 1000um.The windowing diameter of exposed pad is 10um to 10000um.
By photoetching, electroplating technology forms pad in 201 surface of cover board production bond wire, and pad height range is in 10nm
To 1000um, metal can be copper, and aluminium, nickel, silver is golden, and the materials such as tin can be one layer and be also possible to multilayer, thickness range
For 10nm to 1000um.Pad and RDL are one sides herein, positioned at one end that copper post is exposed.
To 201 silicon wafer of cover board do not make smithcraft carry out on one side it is thinned, pass through photoetching, electroplating technology make metal
Pad.In 1nm to 100um, this body structure of metal pad can be one layer and is also possible to multilayer thickness range, and metal material can be with
It is titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel etc..
103) encapsulation step: welding photoelectric functional chip 202 by the technique of eutectic bonding on 201 pad of cover board, leads to
Crossing routing technique interconnects the PAD of functional chip 202 with the pad of 201 wafer of cover board, the bottom of by such a way that wafer scale is bonded
The one side and cover board 201 of seat 101 are bonded together, and place other function core in the another side surface mount process of pedestal 101
Piece 301.Bonded wafer is cut into single encapsulation module, and single encapsulation module is inserted into optical fiber 401, is passed through optical fiber 401
Complete light-path.
It is i.e. specific as shown in figure 3, pass through the technique welding function chip 202 of eutectic bonding on 201 wafer pad of cover board,
The PAD of functional chip 202 is interconnected with the pad of 201 wafer of cover board by routing technique.101 wafer of pedestal and cover board 201 are brilliant
Round key closes, and cutting obtains single module, is passed through optical fiber 401 and completes optical path connection.I.e. as shown in figure 4, passing through wafer scale bonding
Mode is by 101 wafer of pedestal together with 201 wafer bonding of cover board, and bonding temperature is between 200 to 500 degree.It is brilliant in pedestal 101
Round another side places other function chip 301 with surface mount process.Bonded wafer is cut into single encapsulation module.I.e. such as
Shown in Fig. 5, single package mould group is inserted into optical fiber 401, optical fiber 401 is passed through and completes light-path.
Embodiment 2:
As shown in Fig. 6 to Figure 10,201) 101 crystal column surface of pedestal makes silicon hole 102, fills translucent material in silicon hole 102.
As shown in fig. 6, making silicon hole 102, silicon hole 102 by photoetching and dry etch process in 101 crystal column surface of pedestal
Depth is in 10nm to 800um, and 102 shape of silicon hole can be rectangular, and trapezoidal, cylinder etc., side length or diameter range exist
10um to 40000um.
101 wafer of pedestal of this step includes 4,6,8,12 cun of wafers, and thickness range is 200um to 2000um, general
Using silicon wafer, it is also possible to other materials, including glass, quartz, silicon carbide, the inorganic material such as aluminium oxide are also possible to epoxy
Resin, the organic materials such as polyurethane, major function are to provide supporting role.
Silicon hole 102 is filled out by deposition translucent material in crystal column surface, translucent material can be silica, organic resin,
Organic glass etc. removes excess surface material by CMP, leaves behind substance in silicon hole 102.
202) RDL and pad are made in 101 crystal column surface of pedestal, thinned wafer exposes 102 other end of silicon hole.I.e. in silicon
The surface of piece makes RDL, and process includes production insulating layer, and for thickness of insulating layer range in 10nm to 1000um, material can be with
It is silica or silicon nitride.By photoetching, dry etch process windowing allows to connect at windowing with RDL.By photoetching,
Electroplating technology makes RDL in silicon chip surface.RDL includes cabling and key function.Insulating layer can also be covered again on the surface RDL,
Open a window exposed pad on the insulating layer.RDL metal can be copper herein, and aluminium, nickel, silver is golden, and the materials such as tin can be one layer
It can be multilayer, thickness range is 10nm to 1000um.Pad windowing 10um to 10000um diameter.
Bond wire is made on 101 surface of pedestal by photoetching, electroplating technology, pad height range is arrived in 10nm
1000um, metal can be copper, and aluminium, nickel, silver is golden, and the materials such as tin can be one layer and be also possible to multilayer, and thickness range is
10nm to 1000um.
To pedestal 101 do not make smithcraft carry out on one side be thinned and CMP, make 102 other end of silicon hole expose.
203) 202 paster technique of functional chip is welded on 101 wafer of pedestal.As shown in fig. 7, photoelectric functional chip
202 are directly welded on 101 wafer of pedestal by paster technique.
RDL, pad, pit are made in 201 crystal column surface of cover board, and covers metal layer 203 in pit surface.
As shown in figure 8, making RDL on the surface of cover board 201, process includes production insulating layer, thickness of insulating layer range
In 10nm to 1000um, material can be silica or silicon nitride.By photoetching, dry etch process windowing makes to open a window
Place can be connect with RDL.By photoetching, electroplating technology makes RDL in silicon chip surface.RDL includes cabling and key function.
Insulating layer can also be covered again on the surface RDL, open a window exposed pad on the insulating layer.RDL metal can be herein
Copper, aluminium, nickel, silver, gold, the materials such as tin can be one layer and are also possible to multilayer, and thickness range is 10nm to 1000um.Pad
Open a window 10um to 10000um diameter.
By photoetching, electroplating technology forms pad in silicon chip surface production bond wire, and pad height range is arrived in 10nm
1000um, metal can be copper, and aluminium, nickel, silver is golden, and the materials such as tin can be one layer and be also possible to multilayer, and thickness range is
10nm to 1000um.By grinding, the technique of wet etching and dry etching makes cavity 204.
Metal layer 203 is made on 204 surface of cavity by photoetching, electroplating technology, metal can be copper, and aluminium, nickel, silver is golden,
The materials such as tin can be one layer and be also possible to multilayer, and thickness range is 10nm to 1000um.
204) the welding function chip 202 on 101 wafer pad of pedestal, attachment process interconnection.
As shown in figure 9, passing through the technique welding function chip 202 of eutectic bonding on 101 wafer pad of pedestal, pass through patch
Dress technique interconnects the PAD of functional chip 202 with the pad of 201 wafer of cover board.By pedestal 101 in such a way that wafer scale is bonded
Wafer is together with 201 wafer bonding of cover board, and bonding temperature is between 200 to 500 degree.Bonded wafer is cut into single encapsulation
Mould group.As shown in Figure 10, single package mould group is inserted into optical fiber 401, is passed through optical fiber 401 and completes light-path.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, without departing from the inventive concept of the premise, can also make several improvements and modifications, these improvements and modifications also should be regarded as
In the scope of the present invention.
Claims (6)
1. a kind of hermetic type system-level photoelectric module packaged type and technique, which is characterized in that specific processing includes the following steps:
101) pedestal processing step: silicon hole is made by photoetching and dry etch process in susceptor surface, silicon hole depth is in 10nm
To 800um, silicon hole shape be it is rectangular, trapezoidal or cylindrical, side length or diameter range between 10um to 40000um,
The pedestal surface deposits translucent material, and so that deposition translucent material is only left at silicon hole by CMP process, and translucent material is oxidation
Silicon, organic resin or organic glass；
Pad is made by photoetching and electroplating technique on another surface of pedestal, pad thickness range is in 1nm to 100um, pad
This body structure is one or more layers, and the metal material of pad uses one of titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel or more
Kind；Groove is made by photoetching and dry etch process on the pedestal surface, depth is between 10nm to 800um, groove
Shape be it is rectangular, trapezoidal, cylindrical, side length or diameter range are between 10um to 40000um；
102) cover board processing step: cover board makes the hole TSV in lid surface by photoetching, etching technics, and TSV bore dia range exists
1um to 1000um, depth is in 10um to 1000um；Square cvd silicon oxide or silicon nitride or directly thermal oxidation shape on the cover board
At insulating layer, thickness of insulating layer range is existed between 10nm to 100um by physical sputtering, magnetron sputtering or evaporation process
Seed layer is made above insulating layer, for seed layer thickness range in 1nm to 100um, this body structure of seed layer is one or more layers, is planted
The metal material of sublayer uses one or more of titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel；By electro-coppering, make copper
Metal is full of the hole TSV, and densification copper at a temperature of 200 to 500 degree, makes silicon chip surface only be left to fill out copper formation copper with CMP process
Column；
RDL is made on the surface of cover board, process includes production respective insulation layers, and thickness of insulating layer range is arrived in 10nm
1000um, material are silica or silicon nitride, are opened a window by photoetching, dry etch process, RDL is enable to connect with copper post one end
It connects, then RDL is made in lid surface by photoetching, electroplating technology, RDL includes cabling and bonding；
Bond wire is made in lid surface and is formed by photoetching, electroplating technology, and pad height range is in 10nm to 1000um, key
Alloy, which belongs to, uses copper, and aluminium, nickel, silver, gold, one of tin or a variety of, this body structure of bond wire is one or more layers；It welds herein
Disk and RDL are located at the same face of copper post exposing；
The another side of cover board is carried out it is thinned, pass through photoetching, electroplating technology make metal pad；Thickness range is arrived in 1nm
100um, this body structure of metal pad are one or more layers, and the material of metal pad is titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel
One of or it is a variety of；
103) encapsulation step: pass through the technique welding function chip of eutectic bonding on cover board pad, function is made by routing technique
The PAD of energy chip is interconnected with the pad of upper cover plate wafer, is bonded the one side of pedestal and cover board in such a way that wafer scale is bonded
Together, other function chip is placed in the another side of pedestal surface mount process；Bonded wafer is cut into single encapsulation
Mould group, and single encapsulation module is inserted into optical fiber, it is passed through optical fiber and completes light-path.
2. a kind of hermetic type system-level photoelectric module packaged type according to claim 1 and technique, it is characterised in that: lid
Plate, pedestal use unified size, use one of 4,6,8,12 cun sizes, and thickness range is 200um to 2000um,
Material uses silicon wafer, glass, quartz, silicon carbide, aluminium oxide, epoxy resin or polyurethane.
3. a kind of hermetic type system-level photoelectric module packaged type according to claim 1 and technique, it is characterised in that:,
The surface insulation layer dry etching or wet corrosion technique of cover board remove.
4. a kind of hermetic type system-level photoelectric module packaged type according to claim 1 and technique, it is characterised in that:
The surface RDL covers insulating layer, and open a window exposed pad on the insulating layer；The metal of RDL is using in copper, aluminium, nickel, silver, gold, tin herein
One or more, this body structure of RDL uses one or more layers, and the thickness range of RDL is 10nm to 1000um；Pad windowing
Diameter is 10um to 10000um.
5. a kind of hermetic type system-level photoelectric module packaged type according to claim 1 and technique, it is characterised in that: cut
It cuts mode and the centre that pit fills out copper position is located at using laser cutting or cutter cutting, cutting position.
6. a kind of hermetic type system-level photoelectric module packaged type according to claim 1 and technique, it is characterised in that: step
Rapid 103) bonding temperature is between 200 to 500 degree.
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