CN207425850U - The semiconductor packaging frame of SOP 8L - Google Patents
The semiconductor packaging frame of SOP 8L Download PDFInfo
- Publication number
- CN207425850U CN207425850U CN201721318928.XU CN201721318928U CN207425850U CN 207425850 U CN207425850 U CN 207425850U CN 201721318928 U CN201721318928 U CN 201721318928U CN 207425850 U CN207425850 U CN 207425850U
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- Prior art keywords
- foot
- pad
- interior
- semiconductor packaging
- packaging frame
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Abstract
The utility model discloses a kind of semiconductor packaging frame of SOP 8L, it is characterized by comprising interior foot, outer foot and pads, foot is drawn respectively from two pieces of pads wherein in the overwhelming majority, match on the outer foot quantity and position with interior foot, and interior foot is connected by muscle with outer foot, and pad is connected by connection strap with outer foot.The utility model semiconductor packaging frame is applied, by the connection structure for changing chip and pad and pin so that product can be electrically conducted and radiated by outer foot after packaging, ensure product function quality；The producing line of optimization reduces the time that board replaces product simultaneously, improves one times or more of unit production capacity and efficiency；Plating area is changed, corresponding product can be selected according to demand.
Description
Technical field
The utility model is related to a kind of frame structures, and in particular to lead used in a kind of encapsulation semiconductor function chip
Frame.
Background technology
Semiconductor packages refers to the independent core that will be processed by the wafer of test according to product type and functional requirement
The process that piece is packaged.Encapsulation process is：Wafer from chip factory is by being cut into small chip after cutting technique
（Die）, then the chip of well cutting silver paste is mounted to corresponding substrate（Lead frame）Little Ji islands on, recycle it is ultra-fine
Metal（Gold, silver, copper）Conducting wire is by the bond pad of chip（Bond Pad）It is connected to the respective pins of substrate（Lead）, and structure
Into required circuit；Then packaging protection is subject to the mode of injection or epoxy resin to independent chip again, after plastic packaging
Rib cutting is also carried out, tin plating, packaging.Finished product test is carried out after the completion of encapsulation（Test）And packaging（Packing）Etc. processes, finally
Be put in storage shipment.
There is a variety of classification, SOP as semiconductor packaging frame（That is Small Outline Package）And QSOP
（Quarter Small Outline Package）It is the fraction mainstream product of surface mount packages frame, it is extensive
It uses.Wherein SOP is more routinely divided into 7L, 8L by number of pin, and QSOP refers generally to the more product of number of pins, such as 24L.
In the prior art, small one and large one two pads are mainly contained in the semiconductor packaging frame of 8L specifications, meet two
A separate wafer forms functional form device products, and usually using gold thread or copper wire by crystalline substance in the connection of chip and lead frame
Piece is connected with interior foot, is then packaged.In encapsulation process, due to carrying out dispensing and the curing of chip, product can all be sealed
The influence of certain reliability is generated after dress, layering can be led to the problem of when the large percentage of chip and pad, cause product
Functional and the service life reduction, therefore the specification for padding with chip has certain limitation, if reaching certain ratio, accordingly
Chip can not use the lead frame of this specification, and lead frame can not popularization application.
The content of the invention
In view of the problems of the above-mentioned prior art, the purpose of this utility model is to propose a kind of semiconductor package of SOP 8L
Frame up frame.
The above-mentioned purpose of the utility model, the technical solution being achieved：The semiconductor packaging frame of SOP 8L,
It is characterized by comprising interior foot, outer foot and pad, wherein foot is drawn respectively from two pieces of pads, the outer foot quantity in the overwhelming majority
Match on position with interior foot, interior foot is connected by muscle with outer foot, and pad is connected by connection strap with outer foot..
Further, the pad is divided into relatively small first pad of area and relatively large second pad of area,
And foot distribution association is to the second pad in six of which, an interior foot is associated to the first pad, and remaining next interior foot is free on two
Block pads and independence.
Further, the interior foot uses base material for secondary silver-plated semiconductor packages, and the outer foot of adjacent package frame leads to
Cross muscle interconnection and support.
Further, the point plating type product that the semiconductor packaging frame is electroplated for only interior foot pressure-sizing position.
Further, the semiconductor packaging frame is the full plating type product electroplated at interior foot pressure-sizing position and pad.
The protrusion effect that the utility model semiconductor packaging frame is able to apply is：By changing chip with padding and drawing
The connection structure of foot so that product can be electrically conducted and radiated by outer foot after packaging, ensure product function quality；
The producing line of optimization reduces the time that board replaces product simultaneously, improves one times or more of unit production capacity and efficiency；Change electricity
Region is plated, corresponding product can be selected according to demand.
Description of the drawings
Fig. 1 is the structure diagram of the packaging frame of the semiconductor of the utility model SOP 8L.
Specific embodiment
The purpose of this utility model, advantage and feature will carry out figure by the non-limitative illustration of preferred embodiment below
Show and explain.
What the chip specification that the utility model creator is unsuitable for continuing to develop for conventional package frame was packaged will
It asks, innovation proposes a kind of semiconductor packaging frame of SOP 8L, can be with the chip of generally applicable plurality of specifications size, and finished product
Electrical property and heat dissipation are expected to be substantially improved.
As shown in Figure 1, the semiconductor packaging frame of the SOP 8L includes interior foot 2, outer foot 3 and pad 1.Here interior 2 He of foot
Outer foot 3 is referred to as in the industry lead, and pads and be referred to as pad, and such as no special explanation, each technical characteristic described below corresponds to the industry
It is interior to be referred to as understanding.The overwhelming majority is drawn respectively from two pieces of cushion regions in eight interior foot 2a ~ 2h in diagram, and the quantity of outer foot 3
Match on position with interior foot one-to-one corresponding, and interior foot 2 is connected by muscle 4 with outer foot 3, pad 1 by connection strap 5 and
Outer foot 3 is connected.
From diagram as it can be seen that the pad is divided into relatively small first pad 11 of area and relatively large second pad of area
12, and foot 2a, 2b, 2c, 2d, 2g, 2h distribution association are to the second pad 12 in six of which, an interior foot 2f distribution association to the
One pad 11, remaining next interior foot 2e are free on two pieces and pad and independence.This kind of wire bond structure is conducive to pad suitable for a variety of
Chip specification can be multiplexed by the different biplate chip of size, can also the larger single-chip use of area.
In addition, it is illustrated that it is visible to be formed with outer foot in interior outside of foot one-to-one corresponding, and to be that a plate multimode joins altogether secondary for outer foot
Metal lining item, the outer foot of adjacent package frame are interconnected by being coupled bar item.Pass through packed integrated circuit between inside and outside foot
Bar item connects unicom, is achieved in product and can penetrate outer foot after wafer package carrying out electrical conducting and heat dissipation, so as to ensure
The quality of product.
Further to increase more applicabilities of the shell frame products, the semiconductor packaging frame design of the utility model includes gold
Belong to full plating and point plating two types, wherein so-called full plating refers to electroplating at interior foot pressure-sizing position 21 and pad 1；So-called point plating
Refer to only interior foot pressure-sizing position plating.Different demands of the different user in semiconductor packages can be met with this, provided
Polynary alternative.
In conclusion the utility model semiconductor packaging frame is applied, there is more significant technique effect：It is logical
Cross the connection structure for changing chip and pad and pin so that product can be electrically conducted and dissipated by outer foot after packaging
Heat has ensured product function quality；The producing line of optimization reduces the time that board replaces product simultaneously, improves one times or more
Unit production capacity and efficiency.
Still there are many embodiment, all technologies formed using equivalents or equivalent transformation for the utility model
Scheme is all fallen within the scope of protection of the utility model.
Claims (4)
- The semiconductor packaging frame of 1.SOP 8L, it is characterised in that including interior foot, outer foot and pad, wherein the pad is divided into face Long-pending relatively small first pads the second pad relatively large with area, and six interior feet distribution are associated to second and padded, and one To the first pad, remaining next interior foot is free on two pieces and pads and independent, the outer foot quantity and position for a interior foot distribution association It is upper to match with interior foot, and interior foot is connected by muscle with outer foot, and pad is connected by connection strap with outer foot.
- 2. the semiconductor packaging frame of SOP 8L according to claim 1, it is characterised in that：The interior foot is secondary silver-plated Semiconductor packages uses base material, and the outer foot of adjacent package frame is interconnected and supported by muscle.
- 3. the semiconductor packaging frame of SOP 8L according to claim 1, it is characterised in that：The semiconductor packaging frame is The point plating type product of only interior foot pressure-sizing position plating.
- 4. the semiconductor packaging frame of SOP 8L according to claim 1, it is characterised in that：The semiconductor packaging frame is The full plating type product electroplated at interior foot pressure-sizing position and pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721318928.XU CN207425850U (en) | 2017-10-13 | 2017-10-13 | The semiconductor packaging frame of SOP 8L |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721318928.XU CN207425850U (en) | 2017-10-13 | 2017-10-13 | The semiconductor packaging frame of SOP 8L |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207425850U true CN207425850U (en) | 2018-05-29 |
Family
ID=62311090
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721318928.XU Active CN207425850U (en) | 2017-10-13 | 2017-10-13 | The semiconductor packaging frame of SOP 8L |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207425850U (en) |
-
2017
- 2017-10-13 CN CN201721318928.XU patent/CN207425850U/en active Active
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220706 Address after: 221000 building a11, electronic information industrial park, Xuzhou Economic and Technological Development Zone, Jiangsu Province Patentee after: Saiken Electronics (Xuzhou) Co.,Ltd. Address before: 215416 Building 5, No. 3, Huangqiao Road, Shuangfeng town, Taicang City, Suzhou City, Jiangsu Province Patentee before: SAIKEN ELECTRON (SUZHOU) CO.,LTD. |