CN207320101U - The semiconductor packaging frame of QSOP 24L - Google Patents
The semiconductor packaging frame of QSOP 24L Download PDFInfo
- Publication number
- CN207320101U CN207320101U CN201721318929.4U CN201721318929U CN207320101U CN 207320101 U CN207320101 U CN 207320101U CN 201721318929 U CN201721318929 U CN 201721318929U CN 207320101 U CN207320101 U CN 207320101U
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- China
- Prior art keywords
- foot
- pad
- interior
- chip
- semiconductor packaging
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
The utility model discloses a kind of semiconductor packaging frame of QSOP 24L, it is characterized by comprising interior foot, outer foot and pad, wherein 24 interior feet are drawn around pad and the opposite both sides that pad are bent into symmetrical two rows, and match on outer foot quantity and position with interior foot, pad is connected by the bonding of conducting resinl or the bonding of wire with chip, chip is connected by the bonding of wire with interior foot, so as to fulfill the connection of pad and foot outside interior foot.The utility model semiconductor packaging frame is applied, by varying the connection structure of chip and pad and pin so that product can be electrically conducted and radiated by outer foot after packaging, ensure product function quality；The producing line of optimization reduces the time that board replaces product at the same time, improves more than one times of unit production capacity and efficiency.
Description
Technical field
It the utility model is related to a kind of frame structure, and in particular to lead used in one kind encapsulation semiconductor function chip
Frame.
Background technology
Semiconductor packages refers to the independent core that will be processed by the wafer of test according to product type and functional requirement
The process that piece is packaged.Encapsulation process is：Wafer from chip factory is by being cut into small chip after cutting technique
（Die）, then the chip of well cutting silver paste is mounted to corresponding substrate（Lead frame）Little Ji islands on, recycle it is ultra-fine
Metal（Gold, silver, copper）Conducting wire is by the bond pad of chip（Bond Pad）It is connected to the respective pins of substrate（Lead）, and structure
Into required circuit；Then packaging protection is subject to the mode of injection or epoxy resin to independent chip again, after plastic packaging
Rib cutting is also carried out, tin plating, packaging.Finished product test is carried out after the completion of encapsulation（Test）And packaging（Packing）Etc. process, finally
Be put in storage shipment.
There is a variety of classification, SOP as semiconductor packaging frame（That is Small Outline Package）And QSOP
（Quarter Small Outline Package）It is the fraction mainstream product of surface mount packages frame, it is extensive
Use.Wherein SOP is more routinely divided into 7L, 8L by number of pin, and QSOP refers generally to the more product of number of pins, such as 24L.
In the prior art, meet that single-chip forms function containing a pad in the semiconductor packaging frame of 24L specifications
Type device products, and be connected chip with interior foot usually using gold thread or copper wire in the connection of chip and lead frame, then
It is packaged.In encapsulation process, due to carrying out dispensing and the curing of chip, produced after all being encapsulated to product certain reliable
Property influence, when chip with pad large percentage when can produce layering the problem of, cause the reduction in product functionality and service life,
Therefore the specification for padding with chip has certain limitation, if reaching certain ratio row, corresponding chip can not use this specification
Lead frame, lead frame can not popularization application.
The content of the invention
In view of the problems of the above-mentioned prior art, the purpose of this utility model is to propose a kind of semiconductor of QSOP 24L
Packaging frame.
The above-mentioned purpose of the utility model, its technical solution being achieved：The semiconductor package of QSOP 24L frames up
Frame, it is characterised in that including interior foot, outer foot and pad, wherein 24 interior feet draw around pad and pad two lateral bendings relatively
Symmetrical two rows are converted into, are matched on the outer foot quantity and position with interior foot, the bonding or metal that pad passes through conducting resinl
The bonding of silk is connected with chip, and chip is connected by the bonding of wire with interior foot, so as to fulfill pad and foot outside interior foot
Connection；Interior foot is connected by muscle 4 with outer foot 3, and pad 1 is connected by connection strap 5 with outer foot 3.
Further, the interior foot uses base material for secondary silver-plated semiconductor packages, and the outer foot of adjacent package frame leads to
Cross muscle interconnection and support.
Further, the point plating type product that the semiconductor packaging frame is electroplated for only interior foot pressure-sizing position.
Further, institute's art semiconductor packaging frame for only interior foot pressure-sizing position plating and pads the full plating production electroplated
Product
The protrusion effect that the utility model semiconductor packaging frame is able to apply is：By varying chip with padding and drawing
The connection structure of foot so that product can be electrically conducted and radiated by outer foot after packaging, ensure product function quality；
The producing line of optimization reduces the time that board replaces product at the same time, improves more than one times of unit production capacity and efficiency.
Brief description of the drawings
Fig. 1 is the structure diagram of the packaging frame of the semiconductor of the utility model QSOP 24L.
Embodiment
The purpose of this utility model, advantage and feature, will carry out figure by the non-limitative illustration of preferred embodiment below
Show and explain.
What the chip specification that the utility model creator is unsuitable for continuing to develop for conventional package frame was packaged will
Ask, innovation proposes a kind of semiconductor packaging frame of QSOP 24L, and electrical property and heat dissipation are expected to be substantially improved.
As shown in Figure 1, the semiconductor packaging frame of the QSOP 24L includes interior foot 2, outer foot 3 and pad 1.Here interior foot 2
Lead is referred to as in the industry with outer foot 3, and pads and is referred to as pad, and such as no special explanation, each technical characteristic described below is corresponding should
It is referred to as in the industry and understands.24 interior feet are drawn around pad in diagram and the opposite both sides that pad are bent into symmetrical two rows, often
Row has 12 interior feet.And match on outer 3 quantity of foot and position with interior foot, and pad the bonding or metal by conducting resinl
The bonding of silk is connected with chip, and chip is connected by the bonding of wire with interior foot；Interior foot is connected by muscle 4 with outer foot 3
Connect, pad 1 is connected by connection strap 5 with outer foot 3, so as to fulfill the connection of pad and foot outside interior foot.This kind of structure is conducive to
Pad is used suitable for the single-chip of a variety of chip specifications.
In addition, it is illustrated that visible to be corresponded in interior outside of foot formed with outer foot, interior foot is secondary silver-plated semiconductor packages
Using base material, the outer foot of adjacent package frame is interconnected and supported by muscle.Connected unicom by muscle between inside and outside foot, it is thus real
Existing product can pass through outer foot after wafer package and carry out electrical conducting and heat dissipation, so as to ensure the quality of product.
Further to increase more applicabilities of the shell frame products, the semiconductor packaging frame design of the utility model includes gold
Belong to full plating and point plating two types, wherein so-called full plating refers to electroplating at interior foot pressure-sizing position 21 and pad 1；So-called point plating
Refer to only interior foot pressure-sizing position plating.Different demands of the different user in semiconductor packages can be met with this, there is provided
Polynary alternative.
In conclusion the utility model semiconductor packaging frame is applied, there is more significant technique effect：It is logical
Cross the connection structure for changing chip and pad and pin so that product can be electrically conducted and dissipated by outer foot after packaging
Heat, has ensured product function quality；The producing line of optimization reduces the time that board replaces product at the same time, improves more than one times
Unit production capacity and efficiency.
The utility model still has numerous embodiments, all technologies formed using equivalents or equivalent transformation
Scheme, all falls within the scope of protection of the utility model.
Claims (4)
- The semiconductor packaging frame of 1.QSOP 24L, it is characterised in that including interior foot, outer foot and pad, wherein 24 interior feet Drawn around pad and the opposite both sides that pad be bent into symmetrical two rows, matched on the outer foot quantity and position with interior foot, Pad is connected by the bonding of conducting resinl or the bonding of wire with chip, bonding and interior foot phase of the chip by wire Connection；Interior foot is connected by muscle 4 with outer foot 3, and pad 1 is connected by connection strap 5 with outer foot 3.
- 2. the semiconductor packaging frame of QSOP 24L according to claim 1, it is characterised in that：The interior foot is secondary silver-plated Semiconductor packages use base material, the outer foot of adjacent package frame passes through muscle interconnection and support.
- 3. the semiconductor packaging frame of QSOP 24L according to claim 1, it is characterised in that：The semiconductor packaging frame For the point plated product of only interior foot pressure-sizing position plating.
- 4. the semiconductor packaging frame of QSOP 24L according to claim 1, it is characterised in that：Institute's art semiconductor packaging frame The full plated product electroplated for only interior foot pressure-sizing position plating and pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721318929.4U CN207320101U (en) | 2017-10-13 | 2017-10-13 | The semiconductor packaging frame of QSOP 24L |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721318929.4U CN207320101U (en) | 2017-10-13 | 2017-10-13 | The semiconductor packaging frame of QSOP 24L |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207320101U true CN207320101U (en) | 2018-05-04 |
Family
ID=62381144
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721318929.4U Active CN207320101U (en) | 2017-10-13 | 2017-10-13 | The semiconductor packaging frame of QSOP 24L |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207320101U (en) |
-
2017
- 2017-10-13 CN CN201721318929.4U patent/CN207320101U/en active Active
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220804 Address after: 221000 building a11, electronic information industrial park, Xuzhou Economic and Technological Development Zone, Jiangsu Province Patentee after: Saiken Electronics (Xuzhou) Co.,Ltd. Address before: 215416 Building 5, No. 3, Huangqiao Road, Shuangfeng town, Taicang City, Suzhou City, Jiangsu Province Patentee before: SAIKEN ELECTRON (SUZHOU) CO.,LTD. |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220826 Address after: 221000 building a11, electronic information industrial park, Xuzhou Economic and Technological Development Zone, Jiangsu Province Patentee after: Saiken Electronics (Xuzhou) Co.,Ltd. Address before: 215416 Building 5, No. 3, Huangqiao Road, Shuangfeng town, Taicang City, Suzhou City, Jiangsu Province Patentee before: SAIKEN ELECTRON (SUZHOU) CO.,LTD. |