CN207399413U - The non-standard video agreement Transmission system of Camera Link interfaces based on FPGA - Google Patents
The non-standard video agreement Transmission system of Camera Link interfaces based on FPGA Download PDFInfo
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- CN207399413U CN207399413U CN201721541762.8U CN201721541762U CN207399413U CN 207399413 U CN207399413 U CN 207399413U CN 201721541762 U CN201721541762 U CN 201721541762U CN 207399413 U CN207399413 U CN 207399413U
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Abstract
The utility model discloses a kind of non-standard video agreement Transmission system of the Camera Link interfaces based on FPGA, which includes power module, analog video camera, A/D modular converters, the first FPGA module, the second FPGA module, Camera Link interface modules and video compressing module；Power module is connected respectively with analog video camera, the first FPGA module and the second FPGA module；Analog video camera is also connected with A/D modular converters；First FPGA module is also connected with A/D modular converters, Camera Link interface modules respectively；Second FPGA module is also connected with video compressing module, Camera Link interface modules respectively.This system improves the traffic rates of transmission of video, ensure that the real-time of transmission of video, and the internal memory module carried reduces the cost of Video transmission system.Military project is can be widely applied to, space flight communicates, monitoring, the multiple fields of traffic.
Description
Technical field
The utility model is related to video protocols transmission technique fields, are specifically that a kind of Camera Link based on FPGA connect
The non-standard video agreement Transmission system of mouth.
Background technology
With the fast development of video communication technology, transmission of video becomes more and more important, however, in video transmitting procedure
In, transmit the premise that data reliability and real-time height are video high-speed transfers.
Investigation display, the video transmission technologies used both at home and abroad generally using 3 NS DS90CR series chip by 28
Position CMOS/TTL level switchs to 4 pairs of LVDS signals, is then transmitted according to the BT.656 video interfaces agreement of standard, on the one hand, this
Sample generate entire Video transmission system rate is low, and expense is larger, the bit error rate is high and the shortcomings that high expensive.On the other hand,
Whole system rear end is compressed video processing using MJPEG and MJPEG -2 grade conventional video compressions methods, so makes whole
With substantial amounts of external memory in a Video transmission system, the shortcomings of system bulk is big, and load power consumption is higher is finally generated.
Utility model content
The purpose of the utility model is to overcome the deficiencies in the prior art, and provide a kind of Camera based on FPGA
The non-standard video agreement Transmission system of Link interfaces, the system transfer rate are high, power consumption and at low cost.
Realizing the technical solution of the utility model aim is：
A kind of non-standard video agreement Transmission system of the Camera Link interfaces based on FPGA, including power module, mould
Intend video camera, A/D modular converters, the first FPGA module, the second FPGA module, Camera Link interface modules and video compress
Module；Power module respectively with analog video camera, the first FPGA module, the second FPGA module and Camera Link interface modules
Connection；Analog video camera is also connected with A/D modular converters；First FPGA module also respectively with A/D modular converters, Camera
Link interface modules connect；Second FPGA module is also connected with video compressing module, Camera Link interface modules respectively.
Second FPGA module, is the FPGA module based on ZYNQ7020 chips, is internally provided with FIFO memory.
First FPGA module is the FPGA module based on EP4CE6E22C8 chips, is turned by IIC interfaces and A/D
Change the mold block connection.
The video compressing module is the video compressing module based on DM368 and ADV212 chips.
The power module is the power module based on MP2315 chips.
The power module, including the first capacitance, the second capacitance, the 3rd capacitance, the 4th capacitance, the 5th capacitance, first
Resistance, second resistance, 3rd resistor, the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance, the 8th resistance, inductance and
MP2315 chips；One end of first capacitance, one end of second resistance, No. 2 pins of MP2315 chips connect+12V voltages；First electricity
The other end ground connection of appearance；The one end of No. 6 pins of MP2315 chips respectively with the other end of second resistance, first resistor is connected；
The other end ground connection of first resistor；One end ground connection of second capacitance, the other end are connected with No. 7 pins of MP2315 chips；3rd
One end ground connection of resistance, the other end are connected with No. 1 pin of MP2315 chips；No. 5 pins of MP2315 chips and the 4th resistance
One end connection, the other end of the 4th resistance is connected with one end of the 3rd capacitance；No. 3 pins of MP2315 chips are respectively with the 3rd
One end connection of the other end, inductance of capacitance；The other end of inductance respectively with one end of the 6th resistance, the 4th capacitance one end,
One end of 5th capacitance, one end connection of the 8th resistance；The other end of 4th capacitance, the other end ground connection of the 5th capacitance；8th
Another termination+3.3V of resistance；No. 8 pins of MP2315 chips are connected with one end of the 5th resistance；The other end of 5th resistance
One end with the other end of the 6th resistance, the 7th resistance is connected respectively；The other end ground connection of 7th resistance；The 4 of MP2315 chips
Number pin ground connection.
A kind of transmission method of the non-standard video agreement Transmission system of the Camera Link interfaces based on FPGA, specifically
Include the following steps：
1）Power module is opened, electric power source pair of module whole system is made to power, ensures each module normal work；
2）Register parameters inside first FPGA module configuration A/D modular converters comply with standard video camera output and regard
The data flow of frequency agreement；
3）The normal video protocol data-flow of first FPGA module acquisition module video camera output；
4）First FPGA module amendment step 3）In the normal video protocol data-flow that collects, and self-defined non-standard regard
Frequency transmission format protocol, for transmitting amended video data stream；
5）By step 4）In amended video data stream, the 2nd FPGA is transferred to by Camera Link interface modules
In module；
6）The video data that the modification of second FPGA module receives, recovers the video protocol data stream of standard, and transmits
It is handled to video compressing module；
By above-mentioned steps, the transmission of video protocol data stream is completed.
Advantageous effect：A kind of non-standard video association of Camera Link interfaces based on FPGA provided by the utility model
Transmission system is discussed, only the valid data in video format are extracted in transmission process, Elided data and data are originated
Signal is temporarily retained, and so considerably reduces expense and load power consumption, is improved the transmission rate of data, is enhanced
Real-time in video transmitting procedure.And reduce signal cross-talk present in transmission process using Camera Link interfaces
The problems such as, be conducive to the stability and reliability of whole system, finally using the memory carried inside FPGA, solve tradition
External memory chip present in Video transmission system is more, and volume is big, it is of high cost the shortcomings of.It can be widely applied to military project, space flight,
Communication, monitoring, the multiple fields of traffic.
Description of the drawings
Fig. 1 is a kind of non-standard video agreement transmission system of Camera Link interfaces based on FPGA of the utility model
The structure diagram of system；
Fig. 2 is the circuit diagram of the power module of the utility model；
Fig. 3 is that the IIC interfaces of the utility model write sequence diagram；
Fig. 4 is the schematic diagram of BT.656 standard Protocol Data forms；
Fig. 5 is the schematic diagram of non-standard video protocol data form；
Fig. 6 is the sequence diagram of MAX9247；
Fig. 7 is the caching design process chart of the second FPGA module.
Specific embodiment
The utility model is further elaborated with reference to the accompanying drawings and examples, but is not the limit to the utility model
It is fixed.
Embodiment：
As shown in Figure 1, a kind of non-standard video agreement Transmission system of the Camera Link interfaces based on FPGA, including
Power module 4, analog video camera 3, A/D modular converters 5, the first FPGA module 6, the second FPGA module 2, Camera Link connect
Mouth mold block 7 and video compressing module 1；Power module 4 respectively with analog video camera 3, the first FPGA module 6, the second FPGA module 2
It is connected with Camera Link interface modules 7；Analog video camera 3 is also connected with A/D modular converters 5；First FPGA module 6 is also divided
It is not connected with A/D modular converters 5, Camera Link interface modules 7；Second FPGA module 2 also respectively with video compressing module 1,
Camera Link interface modules 7 connect.
Second FPGA module 2, is the FPGA module 2 based on ZYNQ7020 chips, is internally provided with FIFO memory.
First FPGA module 6, is the FPGA module 6 based on EP4CE6E22C8 chips, passes through IIC interfaces and A/D
Modular converter connects, and the sequence diagram of configuration parameter is write to A/D modular converters internal register；As shown in figure 3, first, when
Sequence figure most starts, and when SCL signal is between high period, SDA data bus signals is dragged down, then it represents that entire configuration flow
Belong to the START stages；Secondly, after START, and then SDA data/address bus is posted according to sequential sending device write address, response
The data such as data, response, stop position in storage byte address, response, write-in register.It should be noted that because starting
The change of position and stop position is all happened between the high period of SCL, so occurring the mistake of sequential in order to prevent, SDA data are total
The change of data on line can only be between the low period of each SCL.According to this standard agreement, it is possible to A/D cores will be configured
In the register of the data write-in A/D chip internals of piece, video camera output is made to comply with standard the data flow of video protocols.
The video compressing module 1 is the video compressing module 2 based on DM368 and ADV212 chips.
The power module 4 is the power module 4 based on MP2315 chips,
As shown in Fig. 2, the power module 4, including the first capacitance C1, the second capacitance C2, the 3rd capacitance C3, the 4th electricity
Hold C4, the 5th capacitance C5, first resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4, the 5th resistance R5, the 6th electricity
Hinder R6, the 7th resistance R7, the 8th resistance R8, inductance L324 and MP2315 chip U1；One end of first capacitance C1, second resistance R2
One end, No. 2 pin IN of MP2315 chips connect+12V voltages；The other end ground connection of first capacitance C1；The 6 of MP2315 chips U1
Number one end of pin EN/SYNC respectively with the other end of second resistance R2, first resistor R1 is connected；The other end of first resistor R1
Ground connection；One end ground connection of second capacitance C2, the other end are connected with No. 7 pin VCC of MP2315 chips U1；The one of 3rd resistor R3
End ground connection, the other end are connected with No. 1 pin AAM of MP2315 chips U1；The electricity of No. 5 pin BST of MP2315 chips U1 and the 4th
One end connection of R4 is hindered, the other end of the 4th resistance R4 is connected with one end of the 3rd capacitance C3；No. 3 pins of MP2315 chips U1
The one end of SW respectively with the other end of the 3rd capacitance C3, inductance L324 is connected；The other end of inductance L324 respectively with the 6th resistance
One end of R6, one end connection of one end of the 4th capacitance C4, one end of the 5th capacitance C5, the 8th resistance R8；4th capacitance C4's
The other end ground connection of the other end, the 5th capacitance C5；Another termination+3.3V of 8th resistance R8；No. 8 pins of MP2315 chips U1
FB is connected with one end of the 5th resistance R5；The other end of 5th resistance R5 respectively with the other end of the 6th resistance R6, the 7th resistance
One end connection of R7；The other end ground connection of 7th resistance R7；No. 4 pin GND ground connection of MP2315 core U1 pieces.
A kind of transmission method of the non-standard video agreement Transmission system of the Camera Link interfaces based on FPGA, specifically
Include the following steps：
1）Power module 4 is opened, electric power source pair of module whole system is made to power, ensures each module normal work；
2）Register parameters inside first FPGA module 6 configuration A/D modular converters 5, meet the output of analog video camera 3
The data flow of normal video agreement；
3）The normal video protocol data-flow of first FPGA module, 6 acquisition module video camera 3 output；
4）First FPGA module, 3 amendment step 3）In the normal video protocol data-flow that collects, it is and self-defined non-standard
Transmission of video protocol format, for transmitting amended video data stream；
5）By step 4）In amended video data stream, the 2nd FPGA is transferred to by Camera Link interface modules 7
In module 2；
6）The video data that the modification of second FPGA module 2 receives, recovers the video protocol data stream of standard, and transmits
It is handled to video compressing module 1；
By above-mentioned steps, the transmission of video protocol data stream is completed.
As shown in figure 4, after to have configured the register in A/D modular converters 5, standard that analog video camera 3 exports first
Video protocol data stream（That is the data of BT.656 video formats）, can therefrom draw every a line of standard video data stream by
Each byte composition such as EAV, Blank Video, SAV, Active Video, wherein EAV, SAV are represented respectively by 4BYte, and
Blank Video are represented that last Active Video are represented by 1440BYte, then pass through first by 280 invalid datas
FPGA module 6 gets off data acquisition；First, master of first FPGA module 6 by the use of external crystal oscillator clock as data acquisition
Then clock, is detecting the EAV of each row standard video data stream, SAV, just will be it considers that be complete a line when signals
Starting and ending, and it is preserved.The normal video protocol data that such first FPGA module 6 just exports analog video camera
It collects.
As shown in figure 5, in order to improve the rate of communication and reduce expense, in the base of 656 video data protocols of standard BT.
On plinth, a kind of off-gauge video data protocols form is had devised.First, it is each when detecting in the first FPGA module 6
During capable wardrobe start bit SAV, just the slack byte of EAV, SAV and 280BYte are deleted, only extract having in video data
Imitate data（Active Video）, and the top for adding the start of line FCFE and 4BYte of 2BYte again is gone with bottom and is counted,
Because of the pal mode according to standard, using the resolution ratio of 720*576, so there are 288 rows in bottom field, there are 288 rows in top field, common group
Into 576 rows, counted using this row, the later stage can detect whether each frame malfunction by it, to reach the function of error correction, make be
System is more stablized.So by deleting invalid data and only extracting effective video data, and after being with the addition of customized 6Byte,
It is formed customized video data transmission protocol format.
As shown in fig. 6, the sequence diagram of data is transmitted for Camera Link interface modules 7.First, rise in PCLK_IN
Edge, and DE_IN is in high point and puts down period, RGB_IN samplings are effective video data, and are put down in PCLK_IN for high point, DE_IN
Between low period, RGB_IN samplings are the control data of blanking, and control data that need not be sampled, so whole
During a transmission, as long as ensureing that in DE_IN be transmission data during height.It will thus be changed in the first FPGA module 6
Good customized video data has been sent to the second FPGA module 2 by Camera Link interfaces.
As shown in fig. 7, the data flow diagram exported for the processing of the second FPGA module 2 by Camera Link interfaces.
First, corrupt data in order to prevent, and in order to carry out rate-matched, FIFO memory of second FPGA module 2 inside into
Row data store, and the depth of FIFO are arranged to 8192 storage units, width is arranged to 8bit；Then, the 2nd FPGA is passed through
Whether module 2 detects the count signal in FIFO, judge the buffer data size in FIFO up to 2892 bytes by count signal
When（That is two row effective video data）If reached, valid data are read by RD_EN signals, and are added again
The bytes such as EAV, SAV, Blank Video, the BT.656 data for reverting to standard again are handled to rear end video compressing module 1,
If be not reaching to, continue waiting for the second FPGA module 2 and receive data.By handling above, just can in real time to modification after
Data recovered, ensure the real-time of transmission of video, be ultimately sent in the video compressing module 1 of rear end.
Claims (6)
1. a kind of non-standard video agreement Transmission system of the Camera Link interfaces based on FPGA, which is characterized in that including
Power module, analog video camera, A/D modular converters, the first FPGA module, the second FPGA module, Camera Link interface modules
And video compressing module；Power module respectively with analog video camera, the first FPGA module, the second FPGA module and Camera
Link interface modules connect；Analog video camera is also connected with A/D modular converters；First FPGA module also respectively with A/D moduluss of conversion
Block, the connection of Camera Link interface modules；Second FPGA module also respectively with video compressing module, Camera Link interface moulds
Block connects.
2. a kind of non-standard video agreement transmission system of Camera Link interfaces based on FPGA according to claim 1
System, which is characterized in that second FPGA module, is the FPGA module based on ZYNQ7020 chips, is internally provided with FIFO and deposits
Reservoir.
3. a kind of non-standard video agreement transmission system of Camera Link interfaces based on FPGA according to claim 1
System, which is characterized in that first FPGA module is the FPGA module based on EP4CE6E22C8 chips, passes through IIC interfaces
It is connected with A/D modular converters.
4. a kind of non-standard video agreement transmission system of Camera Link interfaces based on FPGA according to claim 1
System, which is characterized in that the video compressing module is the video compressing module based on DM368 and ADV212 chips.
5. a kind of non-standard video agreement transmission system of Camera Link interfaces based on FPGA according to claim 1
System, which is characterized in that the power module is the power module based on MP2315 chips.
6. a kind of non-standard video agreement transmission system of Camera Link interfaces based on FPGA according to claim 1
System, which is characterized in that the power module, including the first capacitance, the second capacitance, the 3rd capacitance, the 4th capacitance, the 5th electricity
Appearance, first resistor, second resistance, 3rd resistor, the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance, the 8th resistance, electricity
Sense and MP2315 chips；One end of first capacitance, one end of second resistance, No. 2 pins of MP2315 chips connect+12V voltages；The
The other end ground connection of one capacitance；No. 6 pins of MP2315 chips connect respectively with one end of the other end of second resistance, first resistor
It connects；The other end ground connection of first resistor；One end ground connection of second capacitance, the other end are connected with No. 7 pins of MP2315 chips；The
One end ground connection of three resistance, the other end are connected with No. 1 pin of MP2315 chips；No. 5 pins of MP2315 chips and the 4th electricity
One end connection of resistance, the other end of the 4th resistance are connected with one end of the 3rd capacitance；No. 3 pins of MP2315 chips are respectively with
One end connection of the other end, inductance of three capacitances；The other end of inductance respectively with one end of the 6th resistance, the 4th capacitance one
End, one end connection of one end of the 5th capacitance, the 8th resistance；The other end of 4th capacitance, the other end ground connection of the 5th capacitance；The
Another termination+3.3V of eight resistance；No. 8 pins of MP2315 chips are connected with one end of the 5th resistance；5th resistance it is another
One end respectively with the other end of the 6th resistance, the 7th resistance is held to be connected；The other end ground connection of 7th resistance；MP2315 chips
No. 4 pin ground connection.
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| CN201721541762.8U CN207399413U (en) | 2017-11-17 | 2017-11-17 | The non-standard video agreement Transmission system of Camera Link interfaces based on FPGA |
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| CN201721541762.8U CN207399413U (en) | 2017-11-17 | 2017-11-17 | The non-standard video agreement Transmission system of Camera Link interfaces based on FPGA |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107770500A (en) * | 2017-11-17 | 2018-03-06 | 桂林电子科技大学 | The non-standard video agreement Transmission system and transmission method of Camera Link interfaces based on FPGA |
| CN111010541A (en) * | 2019-12-11 | 2020-04-14 | 重庆山淞信息技术有限公司 | Video processing module based on FPGA and compression processor |
-
2017
- 2017-11-17 CN CN201721541762.8U patent/CN207399413U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107770500A (en) * | 2017-11-17 | 2018-03-06 | 桂林电子科技大学 | The non-standard video agreement Transmission system and transmission method of Camera Link interfaces based on FPGA |
| CN111010541A (en) * | 2019-12-11 | 2020-04-14 | 重庆山淞信息技术有限公司 | Video processing module based on FPGA and compression processor |
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Granted publication date: 20180522 Termination date: 20211117 |