CN107770500A - The non-standard video agreement Transmission system and transmission method of Camera Link interfaces based on FPGA - Google Patents
The non-standard video agreement Transmission system and transmission method of Camera Link interfaces based on FPGA Download PDFInfo
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Abstract
The invention discloses a kind of the non-standard video agreement Transmission system and transmission method of the Camera Link interfaces based on FPGA, the system includes power module, analog video camera, A/D modular converters, the first FPGA module, the second FPGA module, Camera Link interface modules and video compressing module；Power module is connected with analog video camera, the first FPGA module and the second FPGA module respectively；Analog video camera is also connected with A/D modular converters；First FPGA module is also connected with A/D modular converters, Camera Link interface modules respectively；Second FPGA module is also connected with video compressing module, Camera Link interface modules respectively.This system improves the traffic rate of transmission of video, ensure that the real-time of transmission of video, and the internal memory module carried reduces the cost of Video transmission system.Military project is can be widely applied to, space flight, is communicated, monitoring, the multiple fields of traffic.
Description
Technical field
The present invention relates to video protocols transmission technique field, specifically a kind of Camera Link interfaces based on FPGA
Non-standard video agreement Transmission system and transmission method.
Background technology
With the fast development of video communication technology, transmission of video seems more and more important, however, in video transmitting procedure
In, transmit the premise that data reliability and real-time height are video high-speed transfers.
Investigation display, the video transmission technologies used both at home and abroad generally use the serial chips of 3 NS DS90CR by 28
Position CMOS/TTL level switchs to 4 pairs of LVDS signals, is then transmitted according to the BT.656 video interfaces agreement of standard, on the one hand, this
Sample generate whole Video transmission system speed is low, and expense is larger, the bit error rate is high and the shortcomings that high expensive.On the other hand,
Whole system rear end is compressed processing to video using MJPEG and MJPEG -2 grade conventional video compression methods, so makes whole
Substantial amounts of external memory storage is carried in individual Video transmission system, finally generates the shortcomings of system bulk is big, and load power consumption is higher.
The content of the invention
It is an object of the invention to overcome the deficiencies in the prior art, and a kind of Camera Link based on FPGA are provided and connect
The non-standard video agreement Transmission system and transmission method of mouth, the system transfer rate is high, and power consumption and cost are low.
Realizing the technical scheme of the object of the invention is：
A kind of non-standard video agreement Transmission system of the Camera Link interfaces based on FPGA, including power module, simulation are taken the photograph
Camera, A/D modular converters, the first FPGA module, the second FPGA module, Camera Link interface modules and video compressing module；
Power module is connected with analog video camera, the first FPGA module, the second FPGA module and Camera Link interface modules respectively；
Analog video camera is also connected with A/D modular converters；First FPGA module also respectively with A/D modular converters, Camera Link interfaces
Module connects；Second FPGA module is also connected with video compressing module, Camera Link interface modules respectively.
The second described FPGA module, it is the FPGA module based on ZYNQ7020 chips, inside is provided with FIFO memory.
The first described FPGA module, it is the FPGA module based on EP4CE6E22C8 chips, is turned by IIC interfaces and A/D
Change the mold block connection.
Described video compressing module, it is the video compressing module based on DM368 and ADV212 chips.
Described power module, it is the power module based on MP2315 chips.
Described power module, including the first electric capacity, the second electric capacity, the 3rd electric capacity, the 4th electric capacity, the 5th electric capacity, first
Resistance, second resistance, 3rd resistor, the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance, the 8th resistance, inductance and
MP2315 chips；One end of first electric capacity, one end of second resistance, No. 2 pins of MP2315 chips connect+12V voltages；First electricity
The other end ground connection of appearance；The other end with second resistance, one end of first resistor are connected No. 6 pins of MP2315 chips respectively；
The other end ground connection of first resistor；One end ground connection of second electric capacity, the other end are connected with No. 7 pins of MP2315 chips；3rd
One end ground connection of resistance, the other end are connected with No. 1 pin of MP2315 chips；No. 5 pins of MP2315 chips and the 4th resistance
One end connection, the other end of the 4th resistance is connected with one end of the 3rd electric capacity；No. 3 pins of MP2315 chips are respectively with the 3rd
One end connection of the other end, inductance of electric capacity；The other end of inductance respectively one end with the 6th resistance, the 4th electric capacity one end,
One end of 5th electric capacity, one end connection of the 8th resistance；The other end of 4th electric capacity, the other end ground connection of the 5th electric capacity；8th
Another termination+3.3V of resistance；No. 8 pins of MP2315 chips are connected with one end of the 5th resistance；The other end of 5th resistance
The other end with the 6th resistance, one end of the 7th resistance are connected respectively；The other end ground connection of 7th resistance；The 4 of MP2315 chips
Number pin ground connection.
A kind of transmission method of the non-standard video agreement Transmission system of the Camera Link interfaces based on FPGA, specifically
Comprise the following steps：
1）Power-on module, electric power source pair of module whole system is powered, ensure each module normal work；
2）Register parameters inside first FPGA module configuration A/D modular converters, make video camera output meet normal video association
The data flow of view；
3）The normal video protocol data-flow of first FPGA module acquisition module video camera output；
4）First FPGA module amendment step 3）In the normal video protocol data-flow that collects, and self-defined non-standard video passes
Defeated protocol format, for transmitting amended video data stream；
5）By step 4）In amended video data stream, the second FPGA module is transferred to by Camera Link interface modules
In；
6）The video data that the modification of second FPGA module receives, recovers the video protocol data stream of standard, and be transferred to and regard
Frequency compression module is handled；
By above-mentioned steps, the transmission of video protocol data stream is completed.
Beneficial effect：A kind of non-standard video agreement of Camera Link interfaces based on FPGA provided by the invention passes
Defeated system and transmission method, only the valid data in video format are extracted in transmitting procedure, to Elided data sum
Temporarily retained according to initial signal, so considerably reduce expense and load power consumption, improve the transmission rate of data, increased
The strong real-time in video transmitting procedure.And reduced using Camera Link interfaces and believed present in transmitting procedure
The problems such as number crosstalk, be advantageous to the stability and reliability of whole system, finally utilize the memory carried inside FPGA, solve
The shortcomings of external memory chip present in conventional video Transmission system is more, and volume is big, and cost is high.The army of can be widely applied to
Work, space flight, communicate, monitoring, the multiple fields of traffic.
Brief description of the drawings
Fig. 1 is a kind of non-standard video agreement Transmission system of Camera Link interfaces based on FPGA of the present invention
Structured flowchart；
Fig. 2 is the circuit diagram of the power module of the present invention；
The IIC interfaces that Fig. 3 is the present invention write timing diagram；
Fig. 4 is the schematic diagram of BT.656 standard Protocol Data forms；
Fig. 5 is the schematic diagram of non-standard video protocol data form；
Fig. 6 is MAX9247 timing diagram；
Fig. 7 is the caching design process chart of the second FPGA module.
Embodiment
The present invention is further elaborated with reference to the accompanying drawings and examples, but is not limitation of the invention.
Embodiment：
As shown in figure 1, a kind of non-standard video agreement Transmission system of the Camera Link interfaces based on FPGA, including power supply
Module 4, analog video camera 3, A/D modular converters 5, the first FPGA module 6, the second FPGA module 2, Camera Link interface moulds
Block 7 and video compressing module 1；Power module 4 respectively with analog video camera 3, the first FPGA module 6, the second FPGA module 2 and
Camera Link interface modules 7 connect；Analog video camera 3 is also connected with A/D modular converters 5；First FPGA module 6 is also distinguished
It is connected with A/D modular converters 5, Camera Link interface modules 7；Second FPGA module 2 also respectively with video compressing module 1,
Camera Link interface modules 7 connect.
The second described FPGA module 2, it is the FPGA module 2 based on ZYNQ7020 chips, inside is provided with FIFO memory.
The first described FPGA module 6, is the FPGA module 6 based on EP4CE6E22C8 chips, passes through IIC interfaces and A/D
Modular converter is connected, and the timing diagram of configuration parameter is write to A/D modular converters internal register；As shown in figure 3, first, when
Sequence figure most starts, and when SCL signal is between high period, SDA data bus signals is dragged down, then it represents that whole configuration flow
Belong to the START stages；Secondly, after START, and then SDA data/address bus response, is posted according to sequential sending device write address
The data such as storage byte address, response, the data in write-in register, response, stop position.It should be noted that because starting
Position and the change of stop position all occur between SCL high period, so in order to prevent the mistake of sequential, SDA data are total
The change of data on line can only be between each SCL low period.According to this standard agreement, it is possible to A/D cores will be configured
In the register of the data write-in A/D chip internals of piece, video camera output is set to meet the data flow of normal video agreement.
Described video compressing module 1, it is the video compressing module 2 based on DM368 and ADV212 chips.
Described power module 4, it is the power module 4 based on MP2315 chips,
As shown in Fig. 2 described power module 4, including the first electric capacity C1, the second electric capacity C2, the 3rd electric capacity C3, the 4th electric capacity
C4, the 5th electric capacity C5, first resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance
R6, the 7th resistance R7, the 8th resistance R8, inductance L324 and MP2315 chip U1；First electric capacity C1 one end, second resistance R2
One end, No. 2 pin IN of MP2315 chips connect+12V voltages；First electric capacity C1 other end ground connection；No. 6 of MP2315 chips U1
The other end with second resistance R2, first resistor R1 one end are connected pin EN/SYNC respectively；First resistor R1 another termination
Ground；Second electric capacity C2 one end ground connection, the other end are connected with MP2315 chips U1 No. 7 pin VCC；3rd resistor R3 one end
Ground connection, the other end are connected with MP2315 chips U1 No. 1 pin AAM；MP2315 chips U1 No. 5 pin BST and the 4th resistance
R4 one end connection, the 4th resistance R4 other end are connected with the 3rd electric capacity C3 one end；MP2315 chips U1 No. 3 pin SW
The other end with the 3rd electric capacity C3, inductance L324 one end are connected respectively；The inductance L324 other end respectively with the 6th resistance R6
One end, the 4th electric capacity C4 one end, the 5th electric capacity C5 one end, the 8th resistance R8 one end connection；4th electric capacity C4's is another
One end, the 5th electric capacity C5 other end ground connection；8th resistance R8 another termination+3.3V；MP2315 chips U1 No. 8 pin FB
It is connected with the 5th resistance R5 one end；The 5th resistance R5 other end other end with the 6th resistance R6, the 7th resistance R7 respectively
One end connection；7th resistance R7 other end ground connection；No. 4 pin GND ground connection of MP2315 core U1 pieces.
A kind of transmission method of the non-standard video agreement Transmission system of the Camera Link interfaces based on FPGA, specifically
Comprise the following steps：
1）Power-on module 4, electric power source pair of module whole system is powered, ensure each module normal work；
2）Register parameters inside first FPGA module 6 configuration A/D modular converters 5, make the output of analog video camera 3 meet standard
The data flow of video protocols；
3）The normal video protocol data-flow of the acquisition module video camera 3 of first FPGA module 6 output；
4）The amendment step 3 of first FPGA module 3）In the normal video protocol data-flow that collects, and self-defined non-standard video
Transmission format protocol, for transmitting amended video data stream；
5）By step 4）In amended video data stream, the second FPGA module is transferred to by Camera Link interface modules 7
In 2；
6）The video data that the modification of second FPGA module 2 receives, recovers the video protocol data stream of standard, and be transferred to and regard
Frequency compression module 1 is handled；
By above-mentioned steps, the transmission of video protocol data stream is completed.
As shown in figure 4, after to have configured the register in A/D modular converters 5, standard that analog video camera 3 exports first
Video protocol data stream（That is the data of BT.656 video formats）, can therefrom draw every a line of standard video data stream by
Each byte composition such as EAV, Blank Video, SAV, Active Video, wherein EAV, SAV are represented by 4BYte respectively, and
Blank Video are represented that last Active Video are represented by 1440BYte, then pass through first by 280 invalid datas
FPGA module 6 gets off data acquisition；First, master of first FPGA module 6 by the use of outside crystal oscillator clock as data acquisition
Clock, then, just will be it considers that be complete a line when detecting the signal such as EAV, SAV of each row standard video data stream
Starting and ending, and it is preserved.The normal video protocol data that such first FPGA module 6 just exports analog video camera
Collect.
As shown in figure 5, in order to improve the speed of communication and reduce expense, in the base of the video data protocols of standard BT. 656
On plinth, a kind of off-gauge video data protocols form have devised.First, it is each when detecting in the first FPGA module 6
During capable wardrobe start bit SAV, just EAV, SAV and 280BYte slack byte are deleted, only extract having in video data
Imitate data（Active Video）, and the 2BYte start of line FCFE and 4BYte top field and the counting of bottom field row are added again,
Because according to the pal mode of standard, using 720*576 resolution ratio, so there are 288 rows bottom field, there are 288 rows top field, common group
Into 576 rows, counted using this row, the later stage can detect whether each frame malfunction by it, to reach the function of error correction, make be
System is more stable.So by deleting invalid data and only extracting effective video data, and after with the addition of customized 6Byte,
It is formed customized video data transmission protocol format.
As shown in fig. 6, the timing diagram of data is transmitted for Camera Link interface modules 7.First, rise in PCLK_IN
Edge, and DE_IN is in high point flat period, RGB_IN samplings are effective video data, and are put down in PCLK_IN for high point, DE_IN
Between low period, what RGB_IN was sampled is the control data of blanking, and control data need not be sampled, so whole
During individual transmission, as long as ensureing that in DE_IN be transmission data during height.It will thus be changed in the first FPGA module 6
Good customized video data has been sent to the second FPGA module 2 by Camera Link interfaces.
As shown in fig. 7, the data flow diagram exported for the processing of the second FPGA module 2 by Camera Link interfaces.
First, in order to prevent corrupt data, and in order to carry out rate-matched, the second FPGA module 2 is entered using the FIFO memory of inside
Row data storage, FIFO depth is arranged to 8192 memory cell, width is arranged to 8bit；Then, the 2nd FPGA is passed through
Whether module 2 detects the count signal in FIFO, judge the buffer data size in FIFO up to 2892 bytes by count signal
When（That is two row effective video data）If reached, valid data are read by RD_EN signals, and adds again
The byte such as EAV, SAV, Blank Video, the BT.656 data for reverting to standard again are handled to rear end video compressing module 1,
If be not reaching to, continue waiting for the second FPGA module 2 and receive data.By more than handle, just can in real time to modification after
Data recovered, ensure the real-time of transmission of video, be ultimately sent in the video compressing module 1 of rear end.
Claims (7)
- A kind of 1. non-standard video agreement Transmission system of the Camera Link interfaces based on FPGA, it is characterised in that including Power module, analog video camera, A/D modular converters, the first FPGA module, the second FPGA module, Camera Link interface modules And video compressing module；Power module respectively with analog video camera, the first FPGA module, the second FPGA module and Camera Link interface modules connect；Analog video camera is also connected with A/D modular converters；First FPGA module also respectively with A/D moduluss of conversion Block, the connection of Camera Link interface modules；Second FPGA module also respectively with video compressing module, Camera Link interface moulds Block connects.
- A kind of 2. non-standard video agreement transmission system of Camera Link interfaces based on FPGA according to claim 1 System, it is characterised in that the second described FPGA module, be the FPGA module based on ZYNQ7020 chips, inside is deposited provided with FIFO Reservoir.
- A kind of 3. non-standard video agreement transmission system of Camera Link interfaces based on FPGA according to claim 1 System, it is characterised in that the first described FPGA module, be the FPGA module based on EP4CE6E22C8 chips, pass through IIC interfaces It is connected with A/D modular converters.
- A kind of 4. non-standard video agreement transmission system of Camera Link interfaces based on FPGA according to claim 1 System, it is characterised in that described video compressing module, be the video compressing module based on DM368 and ADV212 chips.
- A kind of 5. non-standard video agreement transmission system of Camera Link interfaces based on FPGA according to claim 1 System, it is characterised in that described power module, be the power module based on MP2315 chips.
- A kind of 6. non-standard video agreement transmission system of Camera Link interfaces based on FPGA according to claim 1 System, it is characterised in that described power module, including the first electric capacity, the second electric capacity, the 3rd electric capacity, the 4th electric capacity, the 5th electricity Appearance, first resistor, second resistance, 3rd resistor, the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance, the 8th resistance, electricity Sense and MP2315 chips；One end of first electric capacity, one end of second resistance, No. 2 pins of MP2315 chips connect+12V voltages；The The other end ground connection of one electric capacity；The other end with second resistance, one end of first resistor connect No. 6 pins of MP2315 chips respectively Connect；The other end ground connection of first resistor；One end ground connection of second electric capacity, the other end are connected with No. 7 pins of MP2315 chips；The One end ground connection of three resistance, the other end are connected with No. 1 pin of MP2315 chips；No. 5 pins of MP2315 chips and the 4th electricity One end connection of resistance, the other end of the 4th resistance are connected with one end of the 3rd electric capacity；No. 3 pins of MP2315 chips are respectively with One end connection of the other end, inductance of three electric capacity；The other end of inductance one end with the 6th resistance, the one of the 4th electric capacity respectively End, one end connection of one end of the 5th electric capacity, the 8th resistance；The other end of 4th electric capacity, the other end ground connection of the 5th electric capacity；The Another termination+3.3V of eight resistance；No. 8 pins of MP2315 chips are connected with one end of the 5th resistance；5th resistance it is another The other end with the 6th resistance, one end of the 7th resistance are connected respectively at end；The other end ground connection of 7th resistance；MP2315 chips No. 4 pin ground connection.
- 7. a kind of transmission method of the non-standard video agreement Transmission system of the Camera Link interfaces based on FPGA, its feature It is, specifically comprises the following steps：1）Power-on module, electric power source pair of module whole system is powered, ensure each module normal work；2）Register parameters inside first FPGA module configuration A/D modular converters, make video camera output meet normal video association The data flow of view；3）The normal video protocol data-flow of first FPGA module acquisition module video camera output；4）First FPGA module amendment step 3）In the normal video protocol data-flow that collects, and self-defined non-standard video passes Defeated protocol format, for transmitting amended video data stream；5）By step 4）In amended video data stream, the second FPGA module is transferred to by Camera Link interface modules In；6）The video data that the modification of second FPGA module receives, recovers the video protocol data stream of standard, and be transferred to and regard Frequency compression module is handled；By above-mentioned steps, the transmission of video protocol data stream is completed.
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