CN107317670A - A kind of video chaotic secret communication system and method - Google Patents
A kind of video chaotic secret communication system and method Download PDFInfo
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- CN107317670A CN107317670A CN201710670729.3A CN201710670729A CN107317670A CN 107317670 A CN107317670 A CN 107317670A CN 201710670729 A CN201710670729 A CN 201710670729A CN 107317670 A CN107317670 A CN 107317670A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/001—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using chaotic signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs
- H04N21/4408—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs involving video stream encryption, e.g. re-encrypting a decrypted video stream for redistribution in a home network
Abstract
The invention discloses a kind of video chaotic secret communication system and method, the real-time video data gathered by being arranged at the first process kernel of the first dual core processor in the first SOPC chips of dispensing device to video acquisition device carries out chaos encryption, and second processing kernel sends enciphered video data to reception device；3rd process kernel of reception device receives enciphered video data；The fourth process kernel decryption enciphered video data of the second dual core processor in the 2nd SOPC chips of reception device is arranged at, and is stored；Wherein, two process kernels in dual core processor pass through OCM memory communications；Decrypted video data is shown.The application in dispensing device and reception device by using dual core processor so that dual-thread enters row data communication parallel between the two, improves data processing speed, and then improve video chaotic secret communication efficiency.
Description
Technical field
The present invention relates to the communications field, more particularly to a kind of video chaotic secret communication system and method.
Background technology
Although chaotic secret communication algorithm reaches its maturity, but its realization technology but relatively lags behind.
Chaotic secret communication can be realized on a variety of hardware platforms, such as ARM and DSP.Because hardware realizes skill
Relatively backward, the video chaotic secret communication system of now few complete and powerfuls of art.And due to SOC hardware platform
The characteristics of, realize that video chaotic communication is still highly difficult on SOC hardware platform.
But, the existing video chaotic secret communication based on SOC hardware platform is usually to enter line number using single-threaded serial
According to communication, and then cause communication efficiency low.
The content of the invention
It is existing hard based on SOC to solve it is an object of the invention to provide a kind of video chaotic secret communication system and method
The video chaotic secret communication of part platform enters row data communication using single-threaded serial causes the problem of efficiency is low.
In order to solve the above technical problems, the present invention provides a kind of video chaotic secret communication system, the system includes：Video
Harvester, the dispensing device being connected with the video acquisition device, the reception device that is connected of communicating with the dispensing device and
The first video display devices being connected with the reception device；
The dispensing device includes the first dual core processor being arranged in the first SOPC chips；The first double-core processing
First process kernel of device is used to carry out at chaos encryption, second the real-time video data that the video acquisition device is gathered
Reason kernel is used to send enciphered video data to the reception device；First process kernel and the second processing kernel
Pass through the first OCM memory communications；
The reception device includes the second dual core processor being arranged in the 2nd SOPC chips；The second double-core processing
3rd process kernel of device is used to receive the enciphered video data, and fourth process kernel is used to decrypt the encrypted video number
According to, and stored；3rd process kernel and the fourth process kernel pass through the 2nd OCM memory communications.
Alternatively, the dispensing device includes the first buffer area, the second buffer area, the first FPGA；The first FPGA bags
Include the first read-write controller, the second read-write controller, first network module；
First read-write controller is used for the video data write-in that gathers the video acquisition device described the
One buffer area；
Second read-write controller is used to reading the video data in first buffer area, and by the video
Data write second buffer area；
The first network module is connected with the second processing kernel communication, for sending the enciphered video data.
Alternatively, in addition to the second video display devices, the FPGA also includes the first HDMI controllers；
Second video display devices are used to show that the first HDMI controllers are controlled by the described first read-write in real time
The video data for first buffer area that device processed is read.
Alternatively, the reception device includes the 3rd buffer area, the 4th buffer area, the 2nd FPGA；The 2nd FPGA bags
Include the 3rd read-write controller, the 4th read-write controller, the second mixed-media network modules mixed-media, the 2nd HDMI controllers；
Second mixed-media network modules mixed-media is used to receive the enciphered video data；3rd buffer area is regarded for storing decryption
Frequency evidence；
3rd read-write controller is used to read the decrypted video data in the 3rd buffer area, and will be described
Decrypted video data writes the 4th buffer area；
4th read-write controller is used to read the decrypted video data of the 4th buffer area to described second
HDMI controllers；
The 2nd HDMI controllers are used to the decrypted video data being shown in first video display devices.
Alternatively, the first OCM memories and the 2nd OCM memories include predetermined number storage region；Its
In, each described storage region corresponds to the flag variable of predistribution.
In addition, present invention also offers a kind of video Development of Chaotic Secure Communication Method, this method includes：
The real-time video data that first process kernel is gathered to video acquisition device carries out chaos encryption；
Second processing kernel sends enciphered video data to reception device；Wherein, dispensing device includes being arranged at first
The first dual core processor in SOPC chips, first dual core processor is included at first process kernel and described second
Kernel is managed, the first processor kernel and the second processing kernel pass through the first OCM memory communications；
3rd process kernel of the reception device receives the enciphered video data；
The fourth process kernel of the reception device decrypts the enciphered video data, and is stored；Wherein, it is described to connect
Receiving apparatus includes the second dual core processor being arranged in the 2nd SOPC chips, and second dual core processor includes the described 3rd
Process kernel and the fourth process kernel, the 3rd processor cores and the fourth process kernel are deposited by the 2nd OCM
Reservoir communicates；
Decrypted video data is shown in video display devices.
A kind of video chaotic secret communication system provided by the present invention and method, are adopted by the first process kernel to video
The real-time video data of acquisition means collection carries out chaos encryption；Enciphered video data is sent to reception and filled by second processing kernel
Put；Wherein, dispensing device includes being arranged at the first dual core processor in the first SOPC chips, and the first dual core processor includes the
One process kernel and second processing kernel, first processor kernel and second processing kernel pass through the first OCM memory communications；Connect
3rd process kernel of receiving apparatus receives enciphered video data；The fourth process kernel decryption enciphered video data of reception device,
And stored；Wherein, reception device includes the second dual core processor being arranged in the 2nd SOPC chips, the processing of the second double-core
Device includes the 3rd process kernel and fourth process kernel, and the 3rd processor cores and fourth process kernel are stored by the 2nd OCM
Device communicates；Decrypted video data is shown in video display devices.The application in dispensing device and reception device by adopting
With dual core processor so that dual-thread enters row data communication parallel between the two, data processing speed is improved, and then improve video
Chaotic secret communication efficiency.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the accompanying drawing used required in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
The embodiment of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
The accompanying drawing of offer obtains other accompanying drawings.
Fig. 1 is the structural schematic block diagram of video chaotic secret communication system provided in an embodiment of the present invention；
Fig. 2 realizes general diagram for the hardware of video chaotic secret communication system provided in an embodiment of the present invention；
Fig. 3 shows for a kind of flow of embodiment of video Development of Chaotic Secure Communication Method provided in an embodiment of the present invention
It is intended to；
Fig. 4 is dispensing device dual core processor handling process schematic diagram provided in an embodiment of the present invention；
Fig. 5 is reception device dual core processor handling process schematic diagram provided in an embodiment of the present invention.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
A part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
Fig. 1 is refer to, Fig. 1 is the structural schematic block diagram of video chaotic secret communication system provided in an embodiment of the present invention,
The system can include：
Video acquisition device 11, the dispensing device 12 being connected with video acquisition device 11, with dispensing device 12 communication be connected
Reception device 13 and the first video display devices 14 for being connected with reception device 13.Video acquisition device 11 can be gathered in real time
Video data, it can be specially to image first-class video capture device.And the first video display devices 14 can be specially to show
Screen, it can show the video data after reception device decryption.
Dispensing device 12 includes the first dual core processor being arranged in the first SOPC chips；The of first dual core processor
One process kernel 121 is used to carry out chaos encryption, second processing kernel to the real-time video data that video acquisition device is gathered
122 are used to send enciphered video data to reception device；First process kernel and second processing kernel are stored by the first OCM
Device 123 communicates.
Reception device 13 includes the second dual core processor being arranged in the 2nd SOPC chips；The of second dual core processor
Three process kernels 131 are used to receive enciphered video data, and fourth process kernel 132 is used to decrypt enciphered video data, and carries out
Storage；3rd process kernel and fourth process kernel are communicated by the 2nd OCM memories 133.
It is appreciated that above-mentioned SOPC (System-on-a-Programmable-Chip, programmable system on chip chip) can
With including ARM dual core processors and FPGA.Specifically, the SOPC chips can be specially the chips of ZYNQ 7020, can also be specific
For other types of SOPC chips, it is not limited thereto.
Wherein, the arm processor in the SOPC chips in reception device and dispensing device is dual core processor.Send dress
The dual core processor put is mainly used in the encryption and transmission of video data, specifically can realize video by one of process kernel
Encryption, another process kernel realizes the transmission of encrypted video.And the dual core processor of reception device is mainly used in video data
Decryption and reception, the reception of enciphered video data is specifically realized by one of process kernel, another process kernel realize
The decryption of enciphered video data.
Above-mentioned OCM (On Chip Memory, on-chip memory) is low delay on-chip memory, and it is used to realize at two
Internuclear data communication in reason.And the data syn-chronization between two process kernels in same processor can be by flag variable come real
It is existing, i.e., the storage region and corresponding flag variable of predetermined number are distributed to OCM in advance, therefore in some embodiments of the present invention
In, the first OCM memories and the 2nd OCM memories include predetermined number storage region；Wherein, each storage region is corresponded to
The flag variable of predistribution.
For example, distributing 3 storage region r in OCM1、r2、r3The flag variable f corresponding with this 3 storage regions1、
f2、f3.Pass through flag variable states (being, for example, 0 or 1), it is determined whether by data storage to respective regions, to realize same processing
Synchronization for data communication internuclear in two in device.
Certainly, the kernel of above-mentioned processor can also be that more than 2, i.e. processor can be polycaryon processor, also can be real
The purpose of the existing embodiment of the present invention, therefore also fall the protection domain in the embodiment of the present invention.
In the present embodiment, dispensing device 12 can include the first buffer area, the second buffer area, the first FPGA；First FPGA
Including the first read-write controller, the second read-write controller, first network module；First read-write controller is used to fill video acquisition
The video data for putting collection writes the first buffer area；Second read-write controller is used to read the video data in the first buffer area,
And write video data into the second buffer area；First network module is connected with second processing kernel communication, is regarded for sending encryption
Frequency evidence.
First read-write controller and the second read-write controller can ensure that the read-write of dispensing device is synchronous, and it can be specially
VDMA1 and VDMA2.And mixed-media network modules mixed-media can be specially ethernet controller, now, VDMAIP cores bridge joint fpga logic circuit and
DDR memory chips, the function of being transmitted with data double-way.Fpga logic circuit data is write internal memory by VDMA write access, reads logical
Internal storage data is write fpga logic circuit by road.That is the fpga logic circuit of dispensing device can realize video acquisition, video counts
According to functions such as storage, network controls.
Herein, the ARM dual core processors of dispensing device can be used for carrying out chaos encryption to video data.Control in FPGA
Network controller and AMR processor processed, which is engaged, is transmitted enciphered video data, and specifically arm processor is realized
TCP/IP layer function, network controller realizes link layer functionality.
Preferably, in order to intuitively embody the synchronism of transmitting terminal and receiving terminal, the system can also include the second video
Display device, FPGA also includes the first HDMI controllers；Second video display devices are used to show the first HDMI controllers in real time
The video data of the first buffer area read by the first read-write controller.
Now, the video data collected can be shown in the second video display devices by dispensing device, specifically, can
The display of video data is realized to be connected by HDMI with VDMA1.The first display device and the second display device can be passed through
Shown video image, carrys out the current communications status of intuitive judgment.
In the present embodiment, reception device 13 includes the 3rd buffer area, the 4th buffer area, the 2nd FPGA；2nd FPGA includes
3rd read-write controller, the 4th read-write controller, the second mixed-media network modules mixed-media, the 2nd HDMI controllers；Second mixed-media network modules mixed-media is used to connect
Receive enciphered video data；3rd buffer area is used to store decrypted video data；3rd read-write controller is used to read the 3rd caching
Decrypted video data in area, and decrypted video data is write into the 4th buffer area；4th read-write controller is used to read the 4th
The decrypted video data of buffer area is to the 2nd HDMI controllers；2nd HDMI controllers are used to decrypted video data being shown in the
One video display devices.
Second mixed-media network modules mixed-media can be specially ethernet controller.3rd read-write controller and the 4th read-write controller can be with
Ensure that the read-write of the video data of reception device is synchronous, it can be specially VDMA3 and VDMA4.
Herein, the ARM dual core processors in the 2nd SOPC chips can be used for carrying out the enciphered video data received
Chaos is decrypted.Correspondingly, FPGA and arm processor are engaged, and complete the reception of enciphered video data, and by the video after decryption
Data display comes out.
It is appreciated that chaos encryption is generally based on key to complete, and in embodiments of the present invention, used chaos
Encrypting equation can be with as follows：
Wherein, X, Y and Z are state variable, key parameter aij(i, j=1,2,3), its size can be：
O (k) in chaos encryption equation is encrypted video sequence, and its expression formula can be： S (k) is raw video signal.
According to formula provided above, state variable X (k) is iterated.State variable X (k) once, takes repeatedly per iteration
The least-significant byte (be equal to and round the computing of modulus 256) of generation value integer-bit obtains a byte bit wide.Chaos sequence and original video number
An encrypted byte O (k) is obtained according to XOR is carried out, to complete the encryption to video pixel, so as to carry out chaos to video
Encryption.
And chaos decryption is the inverse process of chaos encryption, therefore key parameter, identical chaos decryption equation pair can be used
The enciphered video data of reception is decrypted, and detailed process will not be repeated here.
It should be evident that when key parameter matching it is correct when, can restore decryption after original video, successful decryption,
Now, display device can normally show the video data after decryption；When key parameter matches mismatch, then it can not restore
Original video, decryption failure, now, display device can not normally show video data, it is shown go out be snow.
The video chaotic secret communication system that the present embodiment is provided, by being arranged in the first SOPC chips of dispensing device
The real-time video data that first process kernel of the first dual core processor is gathered to video acquisition device carries out chaos encryption, the
Two process kernels send enciphered video data to reception device；3rd process kernel of reception device receives encrypted video number
According to；It is arranged at the fourth process kernel decryption encrypted video number of the second dual core processor in the 2nd SOPC chips of reception device
According to, and stored；Wherein, two process kernels in dual core processor pass through OCM memory communications；By decrypted video data
Shown.By using dual core processor in dispensing device and reception device so that dual-thread is carried out parallel between the two
Data communication, improves data processing speed, and then improve video chaotic secret communication efficiency.
In order to which the hardware for preferably introducing video chaotic secret communication system is realized, carried out below in conjunction with Fig. 2 specific
Introduce, Fig. 2 realizes general diagram for the hardware of video chaotic secret communication system provided in an embodiment of the present invention.
As shown in Fig. 2 transmitting terminal and receiving terminal pass through wan communication.Transmitting terminal is connected with camera, display, sends
End includes the chips of ZYNQ 7020, DDR internal memories, router and network card chip, wherein, ARM double-cores are included in the chips of ZYNQ 7020
Processor, VDMA1, VDMA2, HDMI controller and ethernet controller, DDR internal memories include buffering area 1 and buffering area 2, often
Individual buffering area is used to realize video frame buffer.ARM dual core processors include two process kernels of CPU1 and CPU0.Receiving terminal includes
Router, network card chip, the chips of ZYNQ 7020, DDR internal memories and display, wherein, the chips of ZYNQ 7020 include Ethernet
Controller, ARM dual core processors, VDMA3, VDMA4 and HDMI controller, DDR internal memories include buffering area 3 and buffering area 4, often
Individual buffering area is used to realize video frame buffer.ARM dual core processors include two process kernels of CPU1 and CPU0.
The FPAG of transmitting terminal can complete the collection, display and transmission of video data, specifically, camera and VDMA1 phases
Even, VDMA1 read channel and write access are connected with buffering area 1, and VDMA2 read channel is connected with buffering area 1, and VDMA2's writes
Passage is connected with buffering area 2；Now, the video data that camera is gathered is write to buffering area 1 by VDMA1 write access,
And read channel and HDMI controllers by VDMA1, video data is shown in display；Read by VDMA2 read channels
The video data of buffering area 1, and write video data into by VDMA2 write access to buffering area 2.ARM dual core processors can be with
Chaos encryption and the transmission of video data are completed, specifically, CPU1 reads the video data of buffering area 2, runs advance burning
Program, chaos encryption is carried out to video data, and CPU1 is stored the video data after encryption by judging the state of flag variable
Into OCM respective memory regions, CPU0 reads the enciphered video data in OCM by flag variable states, passes through ether network control
Video data after encryption is transmitted by device processed.
The dual core processor of transmitting terminal and receiving terminal includes two process kernels, realizes the concurrent working of double-core dual-thread
Row data communication is entered by the OCM of low delay in piece between pattern, double-core.
For example, distributing the region r that three capacity are 1446 bytes in OCM1、r2、r3With 3 flag variable f1、f2、f3。
When CPU1 judges fiWhen=1, then r is arrived into encryption data storageiIn, and allow fi=0, wherein i=1,2,3.As a same reason, CPU0
Judge fiWhen=0, accordingly from riMiddle reading encryption data is transmitted, and allows fi=1.It is effectively real by way of flag judges
The data communication and synchronization between CPU1 and CPU0 are showed.
The router and network card chip of receiving terminal, the enciphered video data sent for receiving end/sending end, pass through ZYNQ
The FPGA of 7020 chips ethernet controller, the enciphered video data received is transmitted to the CPU1 of ARM dual core processors,
CPU1 can carry out chaos decryption to enciphered video data, then store the video data after decryption to OCM respective storage areas
In domain, CPU0 reads the decrypted video data in OCM respective memory regions, stored by judging the state of flag variable
To buffer area 3；Then the video data in buffering area 3 is read by VDMA3 read channel, then will by VDMA3 write access
Video data writes buffering area 4, the video data in buffering area 4 is read finally by VDMA4 read channel, and control by HDMI
Device processed, display is shown in by video data.
It is appreciated that each buffering area may each comprise 3 frame buffers, each frame buffer can store a frame video.Can
So that frame buffer information in the 3 of buffering area 1 is respectively configured into posting for VDMA1 read channels, VDMA1 write access and VDMA2 read channels
In storage；Similarly, the frame buffer of buffering area 2 is configured in VDMA2 write access；The frame buffer of buffering area 3 is configured to VDMA3 and reads logical
In road；The frame buffer of buffering area 4 is configured in VDMA2 write access and VDMA4 read channel.
VDMA1 can realize the transmitting function of frame of video between video acquisition module, HDMI controllers and DDR internal memories.Adopt
Collect after video data, by 3 frame buffers of VDMA1 write access successively recurrent wrIting.At this point it is possible to which tuser signals are matched somebody with somebody
The frame synchronizing signal of write access input is set to, the signal is by video acquisition module control.HDMI controllers complete a frame video
After display, fsync signals are configured to the frame synchronizing signal of read channel input by the new frame video of triggering VDMA1 transmission, should
Signal is controlled by HDMI controllers.By configuring dynamic master slave mode dynamic master and dynamic slave so that write
Passage and read channel realize that synchronously, i.e. two passages of synchronization do not operate identical frame buffer, it is ensured that video data read-write
Accuracy.
Video data from buffering area 1 can be sent to buffering area 2 by VDMA2.VDMA2 read channel and write access is selected respectively
The fsync signals and tuser signals of input are selected as frame synchronizing signal, two synchronizing signals are respectively by arm processor and reading
Passage is controlled.Read channel is configured to dynamic slave patterns, and receives the frame_ptr_out from VDMA1 write access
Signal, it is synchronous that two passages obtain read-write.Frame_ptr_out signals are the id signal of current frame buffer.
The ARM dual core processors circulation of transmitting terminal completes encryption and sending for task, and triggering VDMA2 by CPU1 starts newly
A frame video transmission and storage.The circulation of receiving terminal ARM dual core processors completes the task that network is received and decrypted, and passes through
CPU1 triggerings VDMA3 carries out the access and transmission of frame of video.
Video data from buffering area 3 can be sent to buffering area 4 by VDMA3.VDMA3 read channel and write access is selected respectively
The fsync signals and tuser signals of input are selected as frame synchronizing signal, two synchronizing signals are respectively by arm processor and reading
The control of passage.VDMA4 can realize video data transmitting function between HDMI controllers and internal memory, fsync can be selected to believe
Number as its read channel frame synchronizing signal, the signal is by arm processor control.VDMA4 read channels and VDMA3 write access difference
It is configured to dynamic slave and dynamic master patterns.VDMA4 read channels are received from VDMA3 write access
Frame_ptr_out signals, so as to realize that read-write is synchronous.
As can be seen that the video chaotic secret communication system for the double-core dual-thread that the present embodiment is provided can be improved at system
Managing speed, there is provided data communication efficiency.
Video chaotic secret communication system provided in an embodiment of the present invention is introduced below, video described below is mixed
Ignorant secret signalling can be mutually to should refer to above-described video Development of Chaotic Secure Communication Method.
Fig. 3 is refer to, Fig. 3 is a kind of specific embodiment party of video Development of Chaotic Secure Communication Method provided in an embodiment of the present invention
The schematic flow sheet of formula, this method comprises the following steps：
Step 301：The real-time video data that first process kernel is gathered to video acquisition device carries out chaos encryption.
Step 302：Second processing kernel sends enciphered video data to reception device；Wherein, dispensing device includes setting
The first dual core processor being placed in the first SOPC chips, the first dual core processor is included in the first process kernel and second processing
Core, first processor kernel and second processing kernel pass through the first OCM memory communications.
It is to be appreciated that the handling process of the dual core processor in dispensing device may refer to Fig. 4, Fig. 4 is implemented for the present invention
The dispensing device dual core processor handling process schematic diagram that example is provided.Herein, transmitting terminal CPU1 triggers VDMA2 and starts to transmit video
Frame, while loading frame buffer first address, reading n=1446 byte every time in pointer offset mode carries out chaos encryption and OCM
Storage, circulation m=849 time after complete a frame video operation, then trigger VDMA2 into next frame operation.It is same
OCM storage region is read in moment, CPU0 circulations, and carries out network transmission.Receiving terminal CPU0 carries out the circulation behaviour of network reception
Make the storage of progress OCM simultaneously；CPU1 triggered after OCM reading, decryption and DDR access, complete frame video
Frame of video is stored to buffering area 4 and shown by VDMA3 from buffering area 3.
Step 303：3rd process kernel of reception device receives enciphered video data.
Step 304：The fourth process kernel decryption enciphered video data of reception device, and stored；Wherein, dress is received
Put the second dual core processor including being arranged in the 2nd SOPC chips, the second dual core processor includes the 3rd process kernel and the
Four process kernels, the 3rd processor cores and fourth process kernel pass through the 2nd OCM memory communications.
It is to be appreciated that the handling process of the dual core processor in reception device may refer to Fig. 5, Fig. 5 is implemented for the present invention
The reception device dual core processor handling process schematic diagram that example is provided.Herein, the state that the CPU1 of receiving terminal passes through flag variable
To read the encryption data in OCM, and carry out that Chaotic Solution is close, the video data after decryption is stored into DDR.Meanwhile, CPU0
Carry out corresponding data storage operations.
Step 305：Decrypted video data is shown in video display devices.
The video Development of Chaotic Secure Communication Method that the present embodiment is provided, by being used in dispensing device and reception device
Dual core processor so that dual-thread enters row data communication parallel between the two, improves data processing speed, and then improves video and mix
Ignorant secret communication efficiency.
The embodiment of each in specification is described by the way of progressive, and what each embodiment was stressed is and other realities
Apply the difference of example, between each embodiment identical similar portion mutually referring to.For device disclosed in embodiment
Speech, because it is corresponded to the method disclosed in Example, so description is fairly simple, related part is referring to method part illustration
.
Professional further appreciates that, with reference to the unit of each example of the embodiments described herein description
And algorithm steps, can be realized with electronic hardware, computer software or the combination of the two, in order to clearly demonstrate hardware and
The interchangeability of software, generally describes the composition and step of each example according to function in the above description.These
Function is performed with hardware or software mode actually, depending on the application-specific and design constraint of technical scheme.Specialty
Technical staff can realize described function to each specific application using distinct methods, but this realization should not
Think beyond the scope of this invention.
Video chaotic secret communication system provided by the present invention and method are described in detail above.Herein should
The principle and embodiment of the present invention are set forth with specific case, the explanation of above example is only intended to help and managed
Solve the method and its core concept of the present invention.It should be pointed out that for those skilled in the art, not departing from
On the premise of the principle of the invention, some improvement and modification can also be carried out to the present invention, these are improved and modification also falls into this hair
In bright scope of the claims.
Claims (6)
1. a kind of video chaotic secret communication system, it is characterised in that including video acquisition device and the video acquisition device
Connected dispensing device, the reception device being connected that communicated with the dispensing device and the first video being connected with the reception device
Display device；
The dispensing device includes the first dual core processor being arranged in the first SOPC chips；First dual core processor
First process kernel is used to carry out in chaos encryption, second processing the real-time video data that the video acquisition device is gathered
Core is used to send enciphered video data to the reception device；First process kernel and the second processing kernel pass through
First OCM memory communications；
The reception device includes the second dual core processor being arranged in the 2nd SOPC chips；Second dual core processor
3rd process kernel is used to receive the enciphered video data, and fourth process kernel is used to decrypt the enciphered video data, and
Stored；3rd process kernel and the fourth process kernel pass through the 2nd OCM memory communications.
2. video chaotic secret communication system as claimed in claim 1, it is characterised in that the dispensing device includes first and delayed
Deposit area, the second buffer area, the first FPGA；First FPGA includes the first read-write controller, the second read-write controller, the first net
Network module；
The video data write-in described first that first read-write controller is used to gather the video acquisition device is delayed
Deposit area；
Second read-write controller is used to reading the video data in first buffer area, and by the video data
Write second buffer area；
The first network module is connected with the second processing kernel communication, for sending the enciphered video data.
3. video chaotic secret communication system as claimed in claim 2, it is characterised in that also show and fill including the second video
Put, the FPGA also includes the first HDMI controllers；
Second video display devices are used to show that the first HDMI controllers pass through first read-write controller in real time
The video data of first buffer area read.
4. video chaotic secret communication system as claimed in claim 2, it is characterised in that the reception device includes the 3rd and delayed
Deposit area, the 4th buffer area, the 2nd FPGA；2nd FPGA includes the 3rd read-write controller, the 4th read-write controller, the second net
Network module, the 2nd HDMI controllers；
Second mixed-media network modules mixed-media is used to receive the enciphered video data；3rd buffer area is used to store decryption video counts
According to；
3rd read-write controller is used to reading the decrypted video data in the 3rd buffer area, and by the decryption
Video data writes the 4th buffer area；
4th read-write controller is used to read the decrypted video data of the 4th buffer area to the 2nd HDMI
Controller；
The 2nd HDMI controllers are used to the decrypted video data being shown in first video display devices.
5. the video chaotic secret communication system as described in any one of Claims 1-4, it is characterised in that the first OCM is deposited
Reservoir and the 2nd OCM memories include predetermined number storage region；Wherein, each described storage region corresponds to pre- point
The flag variable matched somebody with somebody.
6. a kind of video Development of Chaotic Secure Communication Method, it is characterised in that including：
The real-time video data that first process kernel is gathered to video acquisition device carries out chaos encryption；
Second processing kernel sends enciphered video data to reception device；Wherein, dispensing device includes being arranged at the first SOPC
The first dual core processor in chip, first dual core processor is included in first process kernel and the second processing
Core, the first processor kernel and the second processing kernel pass through the first OCM memory communications；
3rd process kernel of the reception device receives the enciphered video data；
The fourth process kernel of the reception device decrypts the enciphered video data, and is stored；Wherein, it is described to receive dress
The second dual core processor including being arranged in the 2nd SOPC chips is put, second dual core processor includes the described 3rd processing
Kernel and the fourth process kernel, the 3rd processor cores and the fourth process kernel pass through the 2nd OCM memories
Communication；
Decrypted video data is shown in video display devices.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107770500A (en) * | 2017-11-17 | 2018-03-06 | 桂林电子科技大学 | The non-standard video agreement Transmission system and transmission method of Camera Link interfaces based on FPGA |
| CN109788347A (en) * | 2019-01-21 | 2019-05-21 | 广东工业大学 | A kind of video chaotic secret communication device and method |
| CN113890722A (en) * | 2021-10-11 | 2022-01-04 | 湖南科技大学 | Compressible six-dimensional nondegenerate hyperchaotic image security system and method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101345615A (en) * | 2008-08-05 | 2009-01-14 | 广东工业大学 | Design method for chaos digital secret communication system based on FPGA |
| CN105744294A (en) * | 2016-02-04 | 2016-07-06 | 广东工业大学 | Video chaotic secure communication method implemented in cellphone |
| CN105791853A (en) * | 2016-03-04 | 2016-07-20 | 广东工业大学 | Encrypted embedded video chaotic secret communication method after H.264 coding |
-
2017
- 2017-08-08 CN CN201710670729.3A patent/CN107317670A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101345615A (en) * | 2008-08-05 | 2009-01-14 | 广东工业大学 | Design method for chaos digital secret communication system based on FPGA |
| CN105744294A (en) * | 2016-02-04 | 2016-07-06 | 广东工业大学 | Video chaotic secure communication method implemented in cellphone |
| CN105791853A (en) * | 2016-03-04 | 2016-07-20 | 广东工业大学 | Encrypted embedded video chaotic secret communication method after H.264 coding |
Non-Patent Citations (1)
| Title |
|---|
| 姚翔辉: "基于SOPC技术的数字图像混沌保密通信研究", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107770500A (en) * | 2017-11-17 | 2018-03-06 | 桂林电子科技大学 | The non-standard video agreement Transmission system and transmission method of Camera Link interfaces based on FPGA |
| CN109788347A (en) * | 2019-01-21 | 2019-05-21 | 广东工业大学 | A kind of video chaotic secret communication device and method |
| CN109788347B (en) * | 2019-01-21 | 2021-09-21 | 广东工业大学 | Video chaotic secret communication device and method |
| CN113890722A (en) * | 2021-10-11 | 2022-01-04 | 湖南科技大学 | Compressible six-dimensional nondegenerate hyperchaotic image security system and method |
| CN113890722B (en) * | 2021-10-11 | 2023-10-24 | 湖南科技大学 | Compressible six-dimensional non-degeneracy hyper-chaotic image confidentiality system and method |
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