CN109981496A - OMCI framing device and framing method for XGPON OLT - Google Patents
OMCI framing device and framing method for XGPON OLT Download PDFInfo
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- CN109981496A CN109981496A CN201910236227.9A CN201910236227A CN109981496A CN 109981496 A CN109981496 A CN 109981496A CN 201910236227 A CN201910236227 A CN 201910236227A CN 109981496 A CN109981496 A CN 109981496A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9057—Arrangements for supporting packet reassembly or resequencing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0062—Network aspects
- H04Q11/0067—Provisions for optical access or distribution networks, e.g. Gigabit Ethernet Passive Optical Network (GE-PON), ATM-based Passive Optical Network (A-PON), PON-Ring
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Abstract
The present invention is provided to the OMCI framing devices and framing method of XGPON OLT, are related to the communications field, comprising: DMA write control circuit；MIC, which is calculated, reads control circuit, it is connected with the MIC reading mouth for calculating OMCI frame data caching and MIC calculating OMCI frame delineation FIFO, read procedure for calculating the reading mouth that OMCI frame data caching and MIC calculate OMCI frame delineation FIFO to MIC controls, and after MIC value is calculated, OMCI data frame and the frame delineation of the corresponding correct MIC value of band are exported；OMCI frame rewritting circuit is connected with the MIC output end for calculating reading control circuit, for rewriting corresponding OMCI content frame in OMCI frame data caching and OMCI frame delineation FIFO.The process of writing of the DMA data block of speedy carding process is carried out controlling the lasting high speed processing that ensure that data block, is not in disorder and blocking；Even if CPU sends multiple OMCI frames in DMA data block, there is a small amount of original frame length description and the unmatched mistake of practical frame length, still be able to restore normal in subsequent transmission, keep robustness.
Description
Technical field
The present invention relates to the communications fields, send OMCI (ONU pipe by CPU in XGPON access field more particularly to one kind
Reason and control interface) frame framing circuit.
Background technique
In PON (Passive Optical Network, passive optical-fiber network), OLT (Optical Line
Terminal, the entitled optical line terminal of Chinese) it is terminal device for connecting fiber optic backbone.It is connected in PON using optical fiber
OLT, then OLT is connected to ONU (Optical Network Unit, the entitled optical network unit of Chinese.Finally number is provided by ONU
According to, business such as IPTV (i.e. Interactive Internet TV), voice to the user of terminal.
In order to guarantee high speed, continue, stable transmission downlink OMCI signaling, sent in the CPU of XGPON OLT to 256 ONU
In instruction process, high speed, healthy and strong control circuit will play very important effect.
Chinese patent application CN201310080961.3 discloses a kind of XGEM framing device of ONU end in XGPON system
Grade framing method, is the device that a kind of ONU uplink sets up XGEM frame according to 2.5Gbps maximum bandwidth, but the program is to be directed to
ONU's, this method and device mainly receive after need to being forwarded to the service message of OLT, rapidly forward to OLT, and cannot
It realizes and uses PCIE DMA channel, the continuous OMCI frame set up more than the big bandwidth rates of 1.6Gbps.
Chinese patent application CN200910175197.1 discloses the method for downlink framing a kind of, optical line terminal and passive
Optical network system proposes a kind of downlink framing, and particularly, the program is periodically inserted into the seat PCBd in each default frame
Frame head forms the fused data frame of fixed length, is not related to continuously being set up with PCIE DMA channel more than the big bandwidth rates of 1.6Gbps
The technical requirements of OMCI frame
Summary of the invention
The present invention is to carry out to solve the above-mentioned problems, and it is an object of the present invention to provide a kind of OMCI for XGPON OLT
Framing device and framing method, the device can receive what CPU PCIE DMA channel was sent continuously with about 1.6Gbps rate
OMCI frame, and based on XGEM frame encapsulate, complete OMCI frame to XGEM frame framing, and can in the case where certain error rate,
Guarantee the robustness sent.
The present invention provides a kind of OMCI framing device for XGPON OLT and connects with the PCIE DMA channel of CPU, uses
It is handled in the DMA data block for issuing CPU characterized by comprising
DMA write control circuit is connected with the PCIE DMA channel, for control MIC calculate OMCI frame data caching and
The writing process of MIC calculating OMCI frame delineation FIFO；
MIC, which is calculated, reads control circuit and MIC calculating OMCI frame data caching and MIC calculating OMCI frame delineation FIFO
Reading mouth connection, for MIC calculate OMCI frame data caching and MIC calculate OMCI frame delineation FIFO reading mouth read procedure into
After row controls and MIC value is calculated, OMCI data frame and the frame delineation of the corresponding correct MIC value of band are exported；
OMCI frame rewritting circuit is connected with the MIC output end for calculating reading control circuit, and slow with OMCI frame data
It deposits and is connected with the input of OMCI frame delineation FIFO, for rewriting OMCI frame for corresponding OMCI frame data content and description
In data buffer storage and OMCI frame delineation FIFO.
Provided by the present invention for the OMCI framing device of XGPON OLT, can also have the following features:
Wherein, the MIC calculates reading control circuit and MIC calculates OMCI frame data caching and MIC calculates OMCI frame delineation
FIFO and MIC calculating logic is connected,
The MIC calculates OMCI frame data caching and MIC calculates OMCI frame delineation FIFO input terminal and DMA write control
The output end of circuit is connected, and output end is connected with the MIC input terminal for calculating reading control circuit, and the MIC calculating is patrolled
It collects and is connected with MIC calculating reading control circuit.
Provided by the present invention for the OMCI framing device of XGPON OLT, can also have the following features:
Wherein, in the OMCI frame rewritting circuit, the input terminal of the OMCI frame rewritting circuit and the MIC are calculated and are read
The connection of control circuit output end.
Provided by the present invention for the OMCI framing device of XGPON OLT, can also have the following features:
Wherein, XGEM framer is connect with the output end of OMCI frame data caching, OMCI frame delineation FIFO,
The XGTC framer is connect with the output end of the XGEM framer.
The present invention also provides a kind of framing methods of above-mentioned OMCI framing device for XGPON OLT, are used for CPU
PCIE DMA channel issue DMA data block handled, obtain corresponding XGEM frame and XGTC frame, which is characterized in that packet
Include following steps:
The frame data content write-in MIC of OMCI frame in DMA data block is calculated OMCI frame data and delayed by DMA write control circuit
It deposits, OMCI frame delineation is handled, write-in MIC is calculated in OMCI frame delineation FIFO, when the DMA data block end of transmission, is stopped
Only this DMA data block writing process；
OMCI frame is calculated OMCI frame data from MIC by the frame delineation information that OMCI frame delineation FIFO write-in is calculated according to MIC
Caching is read, while being sent to MIC calculating logic, generates the corresponding MIC value of this frame；
It according to the mic_en instruction in description, determines in each complete OMCI tail, if replacement MIC value；
The OMCI frame of the 32bit bit wide of MIC value will be substituted, according to the odd even position in 64bit new data bus, with
And tail length scale, second of OMCI frame data that 64bit is written caches, and OMCI frame delineation is written in OMCI frame delineation
FIFO, and finally cached by OMCI frame data and OMCI frame delineation FIFO reads the XGEM framer of side, it is encapsulated into band XGEM
The OMCI frame of frame head, is downstream sent with the rate of 10G bps.
Framing method provided by the invention, can also have the following features:
Wherein, when PCIE DMA channel generates end mark signal tx_req_clr, that is, corresponding full unit is indicated
The DMA data block end of transmission, the DMA data block include multiple OMCI frames, which includes OMCI frame delineation and frame data
Content, OMCI frame delineation include Frame Properties description and the description of original frame length.
It is corresponding, after the DMA write control circuit is handled the OMCI frame delineation in DMA data block, write-in MIC meter
It calculates in OMCI frame delineation FIFO, frame data content is written to MIC and calculates OMCI frame data caching.
Framing method provided by the invention, can also have the following features:
The data structure of the OMCI frame includes empty data, Frame Properties describes, original frame length describes, frame data content,
The empty all binary zeros of data, the length is 32bit,
DMA write control circuit processing PCIE DMA channel issue OMCI frame process include:
In idle state, it is all zero and the effective position of envelope according to empty data, searches the head of frame delineation；
The transmission process that Frame Properties description, the description of original frame length are defined after empty data mode, by frame category in transmission process
Property description write-in register, regard the description of original frame length as initial value, write-in frame length describes down counter, while frame length is incremented by
Counter is zero by tax initial value, then retransmits frame data content.
The frame delineation entry of multiple data frames is stored in the control circuit of MIC calculating OMCI frame delineation FIFO, which retouches
State the data structure of entry are as follows: onu_num, port id, mic_en, frame_len, start_addr,
Onu_num, port id, mic_en are the attribute descriptions of frame,
Onu_num indicates the sequence number for the PON ONU that the data frame will pass down,
Port id indicates the GEM port id label of OMCI frame,
Mic_en is whether the mark that progress MIC value is reruned,
Frame_len is the real bytes length of data frame,
Start_addr is the initial address that OMCI frame is written and calculates OMCI frame data caching in MIC,
Send frame data process include:
In the previous bat for sending data frame, it regarding the description of original frame length as initial value, write-in frame length describes down counter,
Thereafter it is effectively indicated according to envelope, into data buffer storage, frame length describes down counter and subtracts 4 bytes, frame one beat of data of every write-in
Long count-up counter adds 4 bytes；
When frame length, which describes down counter, to be decremented to less than or equal to 4 byte, above-mentioned frame delineation entry is just written, is written
The frame_len that MIC calculates the description entry of OMCI frame delineation FIFO is the real bytes length that data frame is written, as frame length
The value that down counter adds frame length count-up counter is described.
Framing method provided by the invention, can also have the following features:
When the reality of original frame length description and the data frame in the frame delineation of some OMCI data frame in DMA data block
When length mismatches, robustness processing is carried out in accordance with the following methods:
A. when the original frame length description in the frame delineation of some OMCI data frame is greater than the physical length of the data frame,
Subsequent envelope effectively indicates that corresponding data as idle data, mend the end for arriving data frame；
When frame length, which describes down counter, to be decremented to less than or equal to 4, write-in MIC calculates retouching for OMCI frame delineation FIFO
The frame_len of entry is stated, the value that down counter adds frame length count-up counter is described for current frame length, frame delineation item is written
Destination frame long value frame_len is also original frame length description；
It is then return to idle state, continues to be all zero and the effective position of envelope according to empty data, searches frame delineation
Head；
If frame length describes down counter and still cannot when a carrying block end, that is, tx_req_clr signal has provided
It is decremented to and is less than or equal to 4, then according to frame length count-up counter at this time plus after 4 bytes, write-in frame delineation entry simultaneously stops
The write-in of data frame content describes the frame length of entry to guarantee to be written frame length at this time and is actually written into the frame length matching of caching；
B. it when the original frame length description in the frame delineation of some data frame is less than the physical length of the data frame, does not just write
Enter the postamble data that the frame is more than the description of original frame length；
When frame length, which describes down counter, to be decremented to less than or equal to 4, write-in MIC calculates retouching for OMCI frame delineation FIFO
The frame_len of entry is stated, the value of down counter is described for frame length, in addition the value of frame length count-up counter, is written frame delineation
The frame length value frame_len of entry is exactly original frame length description in fact.
Framing method provided by the invention, can also have the following features:
Wherein, the frame delineation information being written in OMCI frame delineation FIFO is calculated according to MIC, by the OMCI in DMA data block
Frame is calculated in OMCI frame data caching from MIC and is read, and is sent to MIC calculating logic, calculates corresponding MIC value.
Framing method provided by the invention, can also have the following features:
Wherein, it will be added to the OMCI data fragmentation of MIC value, every two 32bit synthesizes the bus data of a 64bit；
Bus data and MIC value progress are spliced after obtaining complete OMCI data frame again, passes through OMCI frame and rewrite electricity
Road is written in corresponding OMCI frame data caching, and the complete OMCI data frame of data buffer storage is sealed by XGEM framer
Dress, obtains XGEM frame, and XGEM framer determines the reading starting of XGEM content frame by the initial address of each frame delineation of reading
Position, encapsulation process thereafter include that the addition of XGEM frame head, CRC rerun, as defined in the XGPON agreement such as XGEM frame fragment framing
The operation of XGEM framing.
The effect of invention and effect are: the OMCI framing device and framing of XGPON OLT involved according to the present invention
Method, it is slow for controlling MIC calculating OMCI frame data because having DMA write control circuit to connect with the PCIE DMA channel
Deposit and MIC calculate OMCI frame delineation FIFO writing process, it is ensured that the OMCI frame data of DMA data block and frame delineation are connected respectively
Continuous high speed writein, writes process to the caching of the DMA data block of speedy carding process and controls, ensure that at the lasting high speed of data block
Reason, is not in disorder and blocking；After there is a small amount of mistake, it still is able to restore normal in subsequent transmission, keeps healthy and strong
Property.
Due to that after guaranteeing that data frame read-write and transmission mistake occur or be modified, can be sent out by downstream with MIC calculating process
Now and abandon.OMCI frame data cache, the output end of OMCI frame delineation FIFO is connect with GEM frame framer input terminal, GTC frame group
Frame device is connect with the output end of the GEM frame framer, can be corresponded to and be generated GEM frame and GTC frame.
Detailed description of the invention
Fig. 1 is that the OMCI framing device for XGPON OLT in the embodiment of the present invention shows with what XGPON ONU was connect
It is intended to.
Fig. 2 is the structural block diagram of the OMCI framing device for XGPON OLT in the embodiment of the present invention.
The step of Fig. 3 is the framing method in the embodiment of the present invention for the OMCI framing device of XGPON OLT is illustrated
Figure.
Fig. 4 is the data structure schematic diagram of single OMCI data frame in DMA data block in the embodiment of the present invention.
Fig. 5 is the frame delineation structural schematic diagram that MIC calculates OMCI frame in the embodiment of the present invention.
Fig. 6 is the method flow diagram of the DMA write control circuit in the embodiment of the present invention.
Fig. 7 is the MIC value calculating process schematic diagram of OMCI frame.
Fig. 8 is the frame delineation structural schematic diagram that OMCI frame delineation FIFO is written in OMCI frame rewritting circuit.
Specific embodiment
It is real below in order to be easy to understand the technical means, the creative features, the aims and the efficiencies achieved by the present invention
It applies example combination attached drawing and the present invention is specifically addressed for the OMCI framing device and framing method of XGPON OLT.
The meaning of the english abbreviation occurred in the present embodiment
XGPON, rate are the high speed passive optical network of 10Gbps.
Optical line terminal (OLT:Optical Line Terminal) in OLT, i.e. PON.
OMCI, OMCI (optical network unit management control interface, i.e. ONU Management and Control
It Interface is) a kind of agreement of the information interaction of OLT and ONT defined in GPON standard, in GPON network
OLT management to ONT, including configuration management, fault management, performance management and safety management etc..According to the number of the protocol encapsulation
It is OMCI frame according to frame.
ONU, network unit/optical network terminal (the ONU/ONT Optical Network Unit/ of user terminal
Optical Network Terminal)。
DMA, Direct Memory Access direct memory access.
MIC, Messages Integrity Check, message integrity check.
XGEM, XGEM (XG-PON Encapsulation Mode, XGPON packaged type) are that one kind encapsulates on XGPON
The mode of data.
The framing sublayer of XGTC, XGTC (XGPON Transmission Convergence).
PCIE, PCI-Express (Peripheral Component Interconnect Express), are a kind of high
Fast serial computer expansion bus standard
The abbreviation of FIFO, First Input First Output, First Input First Output, this is a kind of traditional sequentially to hold
Row method, the instruction being introduced into first are completed and retire from office, and Article 2 instruction is and then just executed.
BWMAP, bandwidth map, Bandwidth map.
PLOAM, Physical Layer Operations, Administration and Maintenance physical layer
Operations,Administration And Maintenance.
Serdes, Serdes are English SERializer (serializer)/DESerializer (deserializer) abbreviations.It is
A kind of time division multiplexing of mainstream (TDM), point-to-point (P2P) serial communication technology.
RAM, random access memory (Random Access Memory, RAM), also referred to as " random access memory "
UPI, user program interface (User Program Interface).
IDLE, i.e. English idle, the idle meaning, in the present embodiment fingering enter the state of idle waiting.
Fig. 1 is that the OMCI framing device for XGPON OLT in the embodiment of the present invention shows with what XGPON ONU was connect
It is intended to.
Fig. 2 is the structural block diagram of the OMCI framing device for XGPON OLT in the embodiment of the present invention.
As shown in Figure 1, 2, for the OMCI framing device of XGPON OLT there is DMA write control circuit 10, MIC to calculate to read
The units such as control circuit 40, OMCI frame rewritting circuit 50 and XGEM framer 70 are constituted.
DMA write control circuit 10 is connected with the PCIE DMA channel of the CPU in XGPON OLT, and calculates OMCI with MIC
The side of writing that frame data cache 20 and MIC calculating OMCI frame delineation FIFO30 connects, for controlling the writing process of DMA data block.
MIC, which is calculated, reads control circuit 40 and MIC calculating OMCI frame data caching 20 and MIC calculating OMCI frame delineation FIFO
30 reading side connection, controls for the read procedure to FIFO.
MIC calculating logic 41 calculates reading control circuit 40 with MIC and connect, for calculating the control for reading control circuit 40 in MIC
Under system, the MIC value of data frame is calculated；After calculating MIC value, output replaces corresponding MIC to corresponding data frame, in postamble
Value.
MIC calculates OMCI frame data caching 20, in the DMA data block for will export in DMA write control circuit 10
OMCI data frame is cached.
MIC calculates OMCI frame delineation FIFO 30, for will be from the DMA data block exported in DMA write control circuit 10
OMCI frame delineation is cached according to the rule of FIFO (First Input First Output, first in first out) and controls reading
Out.
The MIC calculates OMCI frame data and caches input terminal and the DMA that 20 and MIC calculates OMCI frame delineation FIFO30
The output end of write control circuit 10 is connected, and output end is connected with the MIC input terminal for calculating reading control circuit 40.Institute
State MIC and calculate OMCI frame delineation FIFO 30 and be used for treated in DMA data block OMCI frame delineation, according to fifo structure and
The MIC calculates the OMCI data frame stored in OMCI frame data caching 20 and is associated；The MIC calculating logic 41 and described
MIC, which is calculated, reads the connection of control circuit 40.
OMCI frame rewritting circuit 50 calculates reading control circuit 40 with the MIC and connect；OMCI frame rewritting circuit 50, with
OMCI frame data cache the connection of 51 and OMCI frame delineation FIFO 52, are used for corresponding OMCI agreement content frame and describe again
It is written in OMCI frame data caching 51 and OMCI frame delineation FIFO 52.
XGEM framer 70 is connected with OMCI frame data caching 51 with OMCI frame delineation FIFO52 readout window.
XGEM framer 70 not only caches the output end phase of 51 and OMCI frame delineation FIFO 52 with the OMCI frame data
Even, but also with business frame data the 60 read output end FIFO is cached and describes to be connected.XGEM framer 70 is according to internal priority
Arbitration circuit, the reading request of an OMCI frame of secondary response one or traffic frame.
XGTC framer 80 is connected with XGEM framer 70, completes the XGTC framing after XGEM framing.
In the present embodiment, MIC calculates OMCI frame data and caches the 20 and MIC calculating reading mouth category of OMCI frame delineation FIFO 30
In the passive optical network clock domain of 155.52M；MIC calculates OMCI frame data and caches 20 and MIC calculating OMCI frame delineation FIFO 30
Write mouth, belong to PCIE DMA channel CPU clock domain；
Below in conjunction with the OMCI framing device for XGPON OLT of the present embodiment, to illustrate corresponding framing side
Method.
The step of Fig. 3 is the framing method in the embodiment of the present invention for the OMCI framing device of XGPON OLT is illustrated
Figure.
As shown in figure 3, the framing method of the OMCI framing device for XGPON OLT, the PCIE DMA channel of CPU is sent out
DMA data block out is handled, and is obtained the XGEM frame that can continuously send back-to-back and XGTC frame, is included the following steps that S1 is arrived
S4:
The frame data content write-in MIC of OMCI frame in DMA data block is calculated OMCI frame data caching, will located by step S1
OMCI frame delineation write-in MIC after reason is calculated in OMCI frame delineation FIFO, when the DMA data block end of transmission, stops this DMA
Data block writing process.
OMCI frame delineation calculates OMCI frame data caching in postamble write-in MIC.Postamble write-in description, it is ensured that write-in frame
The practical frame length description of entry write-in is described, and the practical occupancy cache size of frame of write-in data buffer storage matches, if writing
Mistake is found during entire frame, can be covered refreshing by way of rollback data buffer storage first address and be had been written into erroneous frame
Hold, and be not written into description entry, guarantees that erroneous frame will not be read reading side, forwarding will not be swum still further below and filtered out completely.
Specifically, PCIE DMA channel controls the end of each DMA transmission process by following procedure:
When PCIE DMA channel, which generates one, claps high effective DMA data end of block flag signal tx_req_clr, indicate
This DMA carrying terminates；Last of the envelope signal dma_data_we of tx_req_clr signal and DMA data block claps alignment.
The end of data block marking signal tx_req_clr that 10 responding DMA channel of DMA write control circuit generates, and generate just
True writes end operation logic: calculating OMCI frame data in MIC and caches 20 and MIC calculating OMCI frame delineation FIFO 30 in non-
When full state, the request to send signal tx_req that DMA channel issues is high level, guarantees that PCIE DMA data in upstream can be written
OMCI frame data are calculated to MIC to cache in 20 and MIC calculating OMCI frame delineation FIFO30.The DMA data block length of handling process
It can configure.For example, one time DMA data block can if the DMA data block length of one handling process of configuration is 16K byte
To load the OMCI frame of 8 1980 bytes.
Wherein, one DMA data block may include multiple OMCI frames, which includes frame delineation and frame data
(frame_data)。
Fig. 4 is the data structure schematic diagram of OMCI data frame in the embodiment of the present invention.
OMCI data in DMA data block are the mixtures of frame delineation and frame data: the beginning of each OMCI data frame
128bit is the frame delineation of the frame, including the description of empty data, Frame Properties, and original frame length description is followed by frame data；Above data
Corresponding envelope signal dma_data_we is high level, remaining is low level.The interface DMA frame for defining PCIE and DMA channel is write
The data structure entered is as shown in Figure 4.
First 32bit (Dummy Data, empty data) of OMCI frame in each DMA data block will be (4 with 128bit
Double Word) boundary alignment, i.e., can only be since at the 1st, 5,9 ... a Double Word, Dummy Data, that is, full 0 data
It is written at first.That is, if the last byte of a upper frame does not reach the boundary 128bit, behind can fill it is invalid
Byte, until the boundary 128bit, length described in the length field in frame delineation is the length of data packet, i.e., original frame length
Description.
One DMA data root tuber can load one or more OMCI frame according to its configured length difference.If CPU is sent out
Existing remaining data block space can not fill a complete OMCI frame, then be placed in the data block of next handling process and send out
It send.
DMA channel data width is 32bit, i.e. 4 bytes, fixation, which uses, continues 4 bats burst Burst, each burst burst
Pass 4x4=16 byte data.There may be gaps between previous burst and the latter burst, it is also possible to gap be not present.Frame
Tail is filled dummy field and is mended into 16 bytes less than 16 bytes.DMA write control circuit 10 is by the subsequent data of OMCI frame delineation
Frame_data is written MIC and calculates OMCI frame data caching 20；At the postamble moment for having sent frame_data, by DMA
Frame length after the Frame Properties on the OMCI frame structure head of data block is described, recalculated describes frame_len and frame initial address
Start_addr is written to MIC with OMCI frame delineation fifo structure and calculates in OMCI frame delineation FIFO 30.MIC calculates OMCI frame
The data structure corresponding diagram 5 of the content of each address of FIFO is described.
The spatial cache size that MIC calculating OMCI frame data caching 20 is set meets while loading as 4K (4096) byte
The demand of two longest OMCI frames.MIC calculates OMCI frame data caching 20 using the buffer structure of 4K byte, this is allowed for
The maximum frame length of OMCI is 1980 bytes, can store two longest frames simultaneously and go wrong without spill-over.The depth of FIFO
It is 1024, width 32bit, width design is mainly in view of the width 32bit of UPI data/address bus.When the postamble of a data
When only 1~3 byte is effective, needs the position less than 4 bytes mending 0, mend and be written at 4 bytes.
Fig. 5 is the frame delineation structural schematic diagram of OMCI frame in the embodiment of the present invention.
MIC calculates the frame delineation entry that multiple data frames are stored in OMCI frame delineation FIFO 30, each frame delineation item
The data structure definition of mesh mic_dscp_info is as shown in Figure 5:
The onu num of onu_num:8bit OMCI frame is marked, and can be used to indicate maximum 256 ONU sequence numbers.
The GEM port id of port id:14bit OMCI frame is marked, and can indicate maximum 16K port id.
Mic_en: decide whether to carry out the mark that mic reruns.
Frame_len:11bit indicates data frame length, indicates that maximum length is the frame of 2048 bytes.
The caching depth for the data frame delineation that MIC is calculated is 27=128；Description caching be greater than 4K/48=83, using 27
128 addresses of power.
Start_addr: write-in MIC calculates the initial address of the OMCI frame of OMCI frame data caching 20.
Fig. 6 is the method flow diagram of DMA write control circuit.
MIC calculates the common normal read-write of OMCI frame data caching, i.e., as the primitive frame long message frame of OMCI frame delineation
When len and subsequent burst (pulse) length strictly match, control circuit can be by the original frame length description information of every frame, really
Fixed starting and ending position of the frame data in caching.The write-in initial position of each frame is the write-in of a upper frame
The next address of end position.The property continuously read and write according to RAM, the write-in initial position of present frame, in addition frame length describes
The corresponding clock number of information is exactly the initial address of next frame.
DMA write control circuit 10 overfills existing or when writing frame delineation and unmatched practical frame length writing, and is counted by MIC
It calculates OMCI frame data and caches the 20 and MIC calculating improper read-write treatment mechanism of OMCI frame delineation FIFO 30, and pass through DMA data
The tx_req_clr of block is indicated, guarantees when writing full and write robustness when frame delineation and practical frame length mismatch.Once going out
After mistake, it can restore normal in next DMA data block.The method flow diagram of DMA write control circuit can indicate with Fig. 6
Reach robustness target in two kinds of situation in 10th area of DMA write control circuit:
DMA write control circuit 10 such as encounters the description of postamble length and physical length mismatches, in DMA write control circuit 10
It writes frame state machine and needs to distinguish situation and handle respectively, guarantee the robustness of FIFO read-write, so that RAM write is entered reality in write state pusher side
Data frame length is consistent with description frame length, and the failure of RAM read/write address disorder continuously read does not occur.The present apparatus, which can guarantee, to be come from
In the vicious situation of the individual frame lengths of PCIE Upstream Interface, the stability that RAM continuously reads and writes is still ensured that.In DMA data block
When original frame length description in the frame delineation of some OMCI frame is mismatched with the physical length of the data frame, in accordance with the following methods into
The processing of row robustness:
When original frame length description in the frame delineation of some data frame is greater than the physical length of the data frame, subsequent envelope
Effectively indicate that corresponding data as idle data, mend the end for arriving data frame；
At the time of frame length, which describes down counter, to be decremented to less than or equal to 4, according to the frame of attached drawing 5OMCI frame above
Frame delineation entry is written in description scheme；The frame length value of write-in frame delineation entry is exactly original frame length description；It is then return to idle shape
State continues to be all zero and the effective position of envelope according to empty data, searches the head of frame delineation；
If frame length, which describes down counter, cannot still successively decrease until a carrying block end tx_req_clr signal has provided
To being less than or equal to 4, then frame delineation entry is written plus after 4 bytes according to frame length count-up counter at this time, stops in data frame
The write-in of appearance guarantees that write-in frame length describes the frame length of entry and is actually written into the frame length matching of OMCI frame data caching at this time；This
When the frame length count-up counter that is written why to be because number is written in dma when tx_req_clr signal provides plus 4 bytes
According to envelope signal dma_data_we be simultaneously also high level, it is the electric that next bats envelope signal dma_data_we, which is just overturn,
It is flat, so OMCI frame data content will also write a bat, i.e. 4 bytes again, could stop that MIC calculating OMCI frame data caching is written.
When the original frame length description in the frame delineation of some data frame is less than the physical length of the data frame, just it is not written into
The frame is more than the postamble data of original frame length description；
When frame length, which describes down counter, to be decremented to less than or equal to 4, frame delineation entry is written.Frame delineation entry is written
Frame length value be exactly the description of original frame length.
It encounters practical frame length and frame length describes unmatched situation, mic_en does not rerun without exception, guarantees this erroneous frame energy
In receiving end because mic effect cannot be by abandoning.
Above situation can guarantee that frame length when erroneous frame write-in describes the length of attribute and data buffer storage write-in content frame
Matching, the frame length that 20 and MIC of guarantee write-in MIC calculating OMCI frame data caching calculates OMCI frame delineation describe consistency, without
Address disorder mistake occurs.
The method of DMA write control circuit as shown in FIG. 6, validity combination attached drawing 6 can be demonstrate,proved by discussion below
It is bright:
The occupancy umber of beats that MIC calculates the practical frame length of OMCI frame data caching is written, exactly searches original frame length description,
Frame length is described after down counter initializes, it is assumed that the lasting umber of beats of subsequent envelope signal dma_data_we is N, then
Frame length count-up counter is equal to 4N byte.
It is that the description of original frame length subtracts 4N byte that frame length, which describes down counter, is decremented to when frame length describes down counter
When less than or equal to 4 byte, frame length at this time describes down counter plus frame length count-up counter, is equal to original frame length description -4
(N-1)+4 (N-1) eliminates 4 (N-1), practical to be just equal to the long description of primitive frame；If frame length describes last bat of down counter
Less than 4 bytes, the MIC that also occupy 4 byte of a bat calculates OMCI frame data buffer address reading lateral root and only takes most according to frame length description
The effective byte of latter bat.
In case of tx_req_clr be high but frame length describe down counter be not decremented to also it is improper less than or equal to 4 bytes
Situation, the frame length that write-in MIC calculates OMCI frame delineation FIFO are described as 4 (N-1)+4 bytes, clap nybble divided by one, just etc.
In the lasting umber of beats N of dma_data_we.
Above frame length describes down counter, frame length count-up counter is safeguarded by " DMA write control circuit 10 ",
Actually frame length describes down counter, frame length count-up counter is also to operate in DMA write control circuit 10.
Step S2 calculates the frame delineation information of OMCI frame delineation FIFO write-in according to MIC, and OMCI frame is calculated from MIC
OMCI frame data caching is read, while being sent to MIC calculating logic, generates the corresponding MIC value of this frame.
Corresponding, MIC calculating logic 41 is described according to frame length, is arrived OMCI postamble once calculating, is just indicated according to mic_en,
Complete the replacement to OMCI data frame MIC value.MIC calculates OMCI frame data caching 20 using the buffer structure of 4K byte, this is
In view of the maximum frame length of OMCI is 1980 bytes, two longest OMCI frames can be loaded simultaneously, are gone wrong without spill-over.
Excessive in case of write-in burst rate, the MIC value of OMCI frame calculates data buffer storage and full situation still occurs, and OMCI frame is write
Circuit is not written into frame delineation in postamble, and calculates the content frame that OMCI frame data cache 20 for MIC is had been written into, by returning back to
The mode for writing initial address of this frame is removed before, and subsequent OMCI frame is written after the initial address, is covered and is refreshed previously
Have been written into content.
MIC, which is calculated, to be read control circuit 40 from MIC calculating OMCI frame delineation FIFO 30 reading and latches onu_num, port
The description informations such as id, frame_len.
It is 2 that MIC, which calculates 30 depth of OMCI frame delineation FIFO,7=128, reason is that the caching of FIFO is greater than byte/48 4K
Byte=83, using 27 power, 128 addresses.The OMCI frame length of Base type is 48 bytes.Continuous omci report is not considered
Text is smaller than the situation of 48 bytes, and 128 addresses can meet substantially continuous read-write demand.
It is divided into following state with the write control logic of the DMA write control circuit 10 of PCIE DMA channel interface: idle
Wait IDLE state, description parsing, data write state.Realize that the frame length of write-in MIC calculating OMCI frame delineation FIFO 30 is retouched
It states, and the length for the MIC calculating OMCI frame data caching 20 being actually written into matches, and is an important step.The operation passes through
The original frame length description information of OMCI frame is successively decreased according to Burst is reached, and is actually written into MIC and is calculated OMCI frame data caching 20
Practical BURST length it is cumulative, the moment is written in the postamble of OMCI frame, is finally just written to MIC and calculates OMCI frame delineation FIFO
In 30.
MIC calculating logic 41 calculates reading control circuit 40 with MIC and is connected, and MIC, which is calculated, reads control circuit 40 according to AES
The timing of CMAC is combined into 128bit data and envelope after continuous 4 clap reading 32bit data/address bus bit wide, is sent into AES
The IP kernel of CMAC.MIC calculating logic 41 and MIC, which are calculated, reads the combination that control circuit 40 is connected to form, and is verified with the MIC of OMCI
Value is calculated as core to work, detailed process are as follows:
For the channel OMCI, sender is using the information integrity inspection domain (MIC) of 4 bytes for examining and preventing to take advantage of
It deceives.The domain MIC is generated using AES_CMAC.AES_CMAC algorithm based on AES_ECB algorithm, commonly used in message certification and
Completeness check, it is similar with the CRC check being commonly used in Ethernet protocol.
Fig. 7 is the MIC value calculating process schematic diagram of OMCI frame.
Transation ID, business number.
Message type, information type.
Device ID, device numbering.
ME ID, this device numbering.
Message Contents, the information content.
Diection Code, transmission direction code.
Message, information, information to be transmitted.
AES-CMAC-32, AES, that is, Advanced Encryption Standard (English: Advanced Encryption Standard, abbreviation:
AES), it is also known as Rijndael enciphered method in cryptography, is a kind of block encryption standard that U.S. Federal Government uses.CMAC's
Full name is Cypher-Based Message Authentication Code, realizes message based on the symmetric cryptographies mode such as AES
Certification.AES-CMAC-32 is a kind of existing encrypt-decrypt canonical algorithm.AES-CMAC-32engine runs AES-
The encryption and decryption device of CMAC-32 encrypt-decrypt canonical algorithm.Present invention application AES-CMAC-32engine is in 32 bit bit wides
MIC is calculated on the read bus of OMCI frame data caching, generates 4 bytes/32 bits mic value.
OMCI IK is exactly the key value of OMCI frame, is in the present invention exactly 16 bytes/128 bit A ES-CMAC-
The key value of 32engine.
The calculation method in the domain MIC, as shown in Figure 7:
OMCI-MIC=AES-CMAC (OMCI_IK, (and Cdir | OMCI_CONTENT), 32)
Wherein Cdir (being exactly Diection Code) is used to indicate uplink or down direction, and Cdir=0x01 is downlink
Direction, Cdir=0x02 are up direction.OMCI_CONTENT indicates that the content of OMCI message removes last 4 bytes, OMCI_
IK is the key value for calculating the domain OMCI frame MIC.
From MIC calculate OMCI frame data caching 20 in read OMCI frame when, according in frame head mic_en instruction or
Global UPI configures OMCI_mic_force, decides whether that the MIC verification for re-starting OMCI frame is calculated and replaced.When
When needing to carry out MIC calculating and replacement, need to calculate pervious 4 byte of MIC value replacement for generating 4 bytes.
Control circuit 40 is read according to MIC calculating OMCI frame delineation FIFO's 30 when having there is OMCI data frame to be calculated by MIC
After current description information is read, if MIC calculates OMCI frame delineation FIFO 30 as non-null states, and the frame length pointer of a upper frame
Successively decrease and be less than or equal to 16, and the description signal read enable signal dscp_rd_allow signal that downstream DMA rewritting circuit 50 is fed back is
Height then generates MIC and calculates 30 read signal mic_dscp_rd_en of OMCI frame delineation FIFO, opens to calculate from MIC and reads control circuit
40 read the frame delineation process of next OMCI frame.It describes signal read enable signal dscp_rd_allow signal and electricity is rewritten by DMA
The state that the write state machine on road 50 writes OMCI frame into OMCI frame data caching 51 and OMCI frame delineation FIFO 52 generates.
If having had begun the frame delineation process for reading OMCI frame, and MIC is started and has calculated OMCI frame data caching 20
Reading, then forbid reading frame delineation in the read procedure of OMCI frame data, to the last AES CMAC circuit counting goes out MIC value
This bat, according to the MIC_DATA_EN signal of AES CMAC, release read MIC calculate OMCI frame delineation FIFO 30 signal is described
Read enable signal dscp_rd_allow comes back to MIC and calculates the caching 20 and MIC calculating OMCI frame delineation of OMCI frame data
The reading wait state of FIFO 30.
After starting to read the content frame of an OMCI frame, while generating and AES CMAC IP kernel interface control signal.Frame
Next bat of head description read signal mic_dscp_rd_en, reads description, and extracts the frame length information of OMCI frame to frame length pointer.
Since frame length pointer latched this bat of the frame length information of description just now, 4 continuously are read to 32bit bit wide data FIFO and is clapped, then
The 4 continuous 32bit data of bat are spliced into 128bit data and envelope is sent to AES CMAC IP kernel.This first 128bit is sent
To AES CMAC IP kernel data, and highest 8bit adds a direction code, and subsequent 128bit MIC value calculates input
Signal mic_data_chk successively moves 8bit backward.As shown in Figure 7.After each liaison 4 claps 32bit data, frame length pointer
Byte that frame_ptr subtracts 16.After liaison 4 claps one bat 128bit AES CMAC input data of 32bit data generation and envelope,
Several bats are waited again, can be regarded 16 byte datas as and be read gap this period of waiting, restart and continuous 4 clap next time
The read procedure of 32bit.
A 16 byte burst are read every time when frame length pointer to successively decrease, and until being less than or equal to 16 byte, then can be determined that
The tail portion of OMCI frame has been arrived, has given the instruction of AES CMAC IP kernel postamble and tail length instruction at this time.
Step S3 is indicated according to the mic_en in description, is determined in each complete OMCI tail, if replacement
MIC value.
The OMCI frame of the 32bit bit wide of MIC value will be substituted in step S4, according to the odd even in 64bit new data bus
Position and tail length scale, second of OMCI frame data that 64bit is written caches, and OMCI frame delineation is written
OMCI frame delineation FIFO, and finally cached by OMCI frame data and OMCI frame delineation FIFO reads the XGEM framer of side, by its envelope
The OMCI frame with XGEM frame head is dressed up, is downstream sent with the rate of 10G bps.
By corresponding second of write-in OMCI frame data caching, the 51 and OMCI frame delineation FIFO52 of the OMCI frame for being added to MIC value
In, and pass through XGEM framer and XGTC framer, data frame and frame delineation are encapsulated as and the matched XGEM frame of bus bit wide
XGTC frame.
After the MIC calculating for completing OMCI frame, also OMCI used in XGEM framing is completed by OMCI frame rewritting circuit 50
Frame data caching 51 and OMCI frame delineation FIFO52's writes process.The OMCI frame data caching 51 of XGEM framing uses a 4K
The synchronization dual port RAM of byte equally can be continuously the same as two maximum OMCI of fashionable dress because OMCI frame longest is up to 1980 bytes
Frame.It is wide that OMCI rewritting circuit 50 becomes 32bit bit wide the bit wide of 64bit bit wide and 10G GEM framer, interface ram data
Degree is consistent.OMCI rewrites data buffer storage specification 64bit x 512；OMCI frame rewritting circuit mainly completes the place of following two steps
Reason:
1. general data is handled.Prime MIC is calculated in the DMA data block for reading the 32bit that control circuit 40 is read out
OMCI frame, it is every two clap synthesis 64bit bus data, complete 32bit to 64bit bus bit wide mapping function.
2. the MIC value that AES CMAC IP kernel is calculated claps the difference and MIC data of residue length according to postamble one
It is spliced into complete OMCI frame, write-in OMCI frame data caching 51.
Fig. 8 is each description entry data structural schematic diagram of OMCI frame delineation FIFO.
XGEM framing is with OMCI frame delineation FIFO 52 using the FIFO of 128 addresses of depth.XGEM framing is retouched with OMCI frame
State the definition of data fifo structure as shown in Figure 8, each entry is explained as follows:
Start_addr2: the initial address of write-in OMCI frame data caching 51.
MIC, which is calculated, to be read control circuit 40 from MIC calculating OMCI frame delineation FIFO 30 reading and latches onu_num, port
The description informations such as id, frame_len.The same level OMCI frame rewritting circuit caches these description informations and this frame in OMCI frame data
The 51 initial address start_addr2 that writes is merged together, and puts together and OMCI frame delineation FIFO 52 is written again.
After OMCI frame data caching 51 and OMCI frame delineation FIFO 52 is written by apparatus above in complete OMCI frame, lead to
Cross the XGTC frame framing state machine in XGEM frame framing state machine and XGTC framer in the reading control circuit of XGEM framing 70
Read control action, complete G.987.3 agreement XGPON downlink XGEM XGTC frame encapsulation, encapsulation process includes that XGEM frame head adds
Add, CRC reruns, XGEM fragment frame framing, GTC frame head addition, further can also according to circumstances be added BWMAP structural adjustment and
The functions such as PLOAM message transmission.As shown in Figure 1, being passed after the completion of XGEM/XGTC frame framing by downlink Serdes and optical channel
It send to each ONU.
The effect of embodiment and effect are: according to the OMCI framing device and framing of the XGPON OLT that embodiment provides
Method, it is slow for controlling MIC calculating OMCI frame data because having DMA write control circuit to connect with the PCIE DMA channel
Deposit and MIC calculate OMCI frame delineation FIFO writing process, it is ensured that the OMCI frame data of DMA data block and frame delineation are connected respectively
Continuous high speed writein；Due to writing process to the caching of the DMA data block of speedy carding process and controlling with DMA write control circuit, protect
The continuous high speed processing for having demonstrate,proved data block, is not in disorder and blocking；After there is a small amount of mistake, it still is able in rear supervention
It send middle recovery normal, guarantees robustness.
Due to that after guaranteeing that data frame read-write and transmission mistake occur or be modified, can be sent out by downstream with MIC calculating process
Now and abandon.
Due to writing process to the caching of the DMA data block of speedy carding process and controlling with DMA write control circuit, guarantee
The lasting high speed processing of data block, is not in disorder and blocking.
Further, due to having caching robustness processing, even if CPU transmission a small amount of description occurs and frame length is unmatched
Erroneous frame can also restore normal in subsequent transmission, keep robustness.
The present invention is not limited to the above-described embodiments, for those skilled in the art, is not departing from
Under the premise of the principle of the invention, several improvements and modifications can also be made, these improvements and modifications are also considered as protection of the invention
Within the scope of.The content being not described in detail in this specification belongs to the prior art well known to professional and technical personnel in the field.
Claims (10)
1. a kind of OMCI framing device for XGPON OLT is connected with the PCIE DMA channel of CPU, for issue CPU
DMA data block is handled characterized by comprising
DMA write control circuit is connected with the PCIE DMA channel, is calculated based on OMCI frame data caching and MIC by controlling MIC
Calculate the writing process of OMCI frame delineation FIFO；
MIC calculates the reading for reading control circuit and MIC calculating OMCI frame data caching and MIC calculating OMCI frame delineation FIFO
Mouth connection, the read procedure for calculating the reading mouth that OMCI frame data caching and MIC calculate OMCI frame delineation FIFO to MIC are controlled
After making and MIC value being calculated, OMCI data frame and the frame delineation of the corresponding correct MIC value of band are exported；
OMCI frame rewritting circuit, with the MIC calculate read control circuit output end be connected, and with OMCI frame data caching and
The input of OMCI frame delineation FIFO is connected, for rewriting OMCI frame data for corresponding OMCI frame data content and description
Caching and OMCI frame delineation FIFO in.
2. the OMCI framing device according to claim 1 for XGPON OLT, it is characterised in that:
Wherein, the MIC calculates reading control circuit and MIC calculates OMCI frame data caching and MIC calculates OMCI frame delineation FIFO
And MIC calculating logic is connected,
The MIC calculates OMCI frame data caching and MIC calculates OMCI frame delineation FIFO input terminal and the DMA write control circuit
Output end be connected, output end and the MIC, which are calculated, to be read the input terminal of control circuit and is connected, the MIC calculating logic and
The MIC, which is calculated, reads control circuit connection.
3. the OMCI framing device according to claim 2 for XGPON OLT, it is characterised in that:
Wherein, in the OMCI frame rewritting circuit, the input terminal of the OMCI frame rewritting circuit and the MIC are calculated and are read control
Circuit output end connection.
4. the OMCI framing device according to claim 3 for XGPON OLT, it is characterised in that:
Wherein, XGEM framer is connect with the output end of OMCI frame data caching, OMCI frame delineation FIFO,
The XGTC framer is connect with the output end of the XGEM framer.
5. the framing method of the OMCI framing device as claimed in any of claims 1 to 4 for XGPON OLT,
For handling the DMA data block of the PCIE DMA channel sending of CPU, corresponding XGEM frame and XGTC frame are obtained, spy
Sign is, comprising the following steps:
The frame data content write-in MIC of OMCI frame in DMA data block is calculated OMCI frame data caching by DMA write control circuit, will
OMCI frame delineation is handled, and write-in MIC is calculated in OMCI frame delineation FIFO, when the DMA data block end of transmission, stops this
DMA data block writing process；
OMCI frame is calculated OMCI frame data caching from MIC by the frame delineation information that OMCI frame delineation FIFO write-in is calculated according to MIC
It reads, while being sent to MIC calculating logic, generate the corresponding MIC value of this frame；
It according to the mic_en instruction in description, determines in each complete OMCI tail, if replacement MIC value；
The OMCI frame of the 32bit bit wide of MIC value will be substituted, according in 64bit new data bus odd even position and frame
Tail length size, second of OMCI frame data that 64bit is written caches, and OMCI frame delineation is written in OMCI frame delineation
FIFO, and finally cached by OMCI frame data and OMCI frame delineation FIFO reads the XGEM framer of side, it is encapsulated into band XGEM
The OMCI frame of frame head, is downstream sent with the rate of 10G bps.
6. framing method according to claim 5, it is characterised in that:
Wherein, when PCIE DMA channel generates end mark signal tx_req_clr, that is, the DMA number of corresponding full unit is indicated
According to the block end of transmission, the DMA data block includes multiple OMCI frames, which includes OMCI frame delineation and frame data content,
OMCI frame delineation includes Frame Properties description and the description of original frame length.
Corresponding, after the DMA write control circuit is handled the OMCI frame delineation in DMA data block, write-in MIC is calculated
In OMCI frame delineation FIFO, frame data content is written to MIC and calculates OMCI frame data caching.
7. framing method according to claim 5, it is characterised in that:
The data structure of the OMCI frame includes empty data, Frame Properties describes, original frame length describes, frame data content,
The empty all binary zeros of data, the length is 32bit,
DMA write control circuit processing PCIE DMA channel issue OMCI frame process include:
In idle state, it is all zero and the effective position of envelope according to empty data, searches the head of frame delineation；
The transmission process that Frame Properties description, the description of original frame length are defined after empty data mode, retouches Frame Properties in transmission process
Write-in register is stated, regard the description of original frame length as initial value, write-in frame length describes down counter, while frame length incremental count
Device is zero by tax initial value, then retransmits frame data content.
The frame delineation entry of multiple data frames, the frame delineation item are stored in the control circuit of MIC calculating OMCI frame delineation FIFO
Purpose data structure are as follows: onu_num, port id, mic_en, frame_len, start_addr, onu_num, port id,
Mic_en is the attribute description of frame,
Onu_num indicates the sequence number for the PON ONU that the data frame will pass down,
Port id indicates the GEM port id label of OMCI frame,
Mic_en is whether the mark that progress MIC value is reruned,
Frame_len is the real bytes length of data frame,
Start_addr is the initial address that OMCI frame is written and calculates OMCI frame data caching in MIC,
Send frame data process include:
In the previous bat for sending data frame, it regard the description of original frame length as initial value, write-in frame length describes down counter, thereafter
It is effectively indicated according to envelope, one beat of data of every write-in is into data buffer storage, and frame length describes down counter and subtracts 4 bytes, and frame length is passed
Device is counted up plus 4 bytes；
When frame length, which describes down counter, to be decremented to less than or equal to 4 byte, above-mentioned frame delineation entry is just written, MIC is written
The frame_len for calculating the description entry of OMCI frame delineation FIFO is the real bytes length that data frame is written, and as frame length is retouched
State the value that down counter adds frame length count-up counter.
8. framing method according to claim 7, it is characterised in that:
When the physical length of original frame length description and the data frame in the frame delineation of some OMCI data frame in DMA data block
When mismatch, robustness processing is carried out in accordance with the following methods:
A. when the original frame length description in the frame delineation of some OMCI data frame is greater than the physical length of the data frame, subsequent
Envelope effectively indicates that corresponding data as idle data, mend the end for arriving data frame；
When frame length, which describes down counter, to be decremented to less than or equal to 4, write-in MIC calculates the description item of OMCI frame delineation FIFO
Purpose frame_len describes the value that down counter adds frame length count-up counter for current frame length, write-in frame delineation entry
Frame length value frame_len is also original frame length description；
It is then return to idle state, continues to be all zero and the effective position of envelope according to empty data, searches the head of frame delineation；
If frame length, which describes down counter, cannot still successively decrease when a carrying block end, that is, tx_req_clr signal has provided
To being less than or equal to 4, then according to frame length count-up counter at this time plus after 4 bytes, write-in frame delineation entry simultaneously stops data
The write-in of content frame describes the frame length of entry to guarantee to be written frame length at this time and is actually written into the frame length matching of caching；
B. when the original frame length description in the frame delineation of some data frame is less than the physical length of the data frame, just it is not written into this
Frame is more than the postamble data of original frame length description；
When frame length, which describes down counter, to be decremented to less than or equal to 4, write-in MIC calculates the description item of OMCI frame delineation FIFO
Purpose frame_len describes the value of down counter for frame length, in addition the value of frame length count-up counter, is written frame delineation entry
Frame length value frame_len be in fact exactly the description of original frame length.
9. framing method according to claim 5, it is characterised in that:
Wherein, calculate the frame delineation information that is written in OMCI frame delineation FIFO according to MIC, by the OMCI frame in DMA data block from
MIC is calculated to be read in OMCI frame data caching, and is sent to MIC calculating logic, calculates corresponding MIC value.
10. framing method according to claim 5, it is characterised in that:
Wherein, it will be added to the OMCI data fragmentation of MIC value, every two 32bit synthesizes the bus data of a 64bit；
Bus data and MIC value progress are spliced after obtaining complete OMCI data frame again, is write by OMCI frame rewritting circuit
Enter in corresponding OMCI frame data caching, the complete OMCI data frame of data buffer storage be packaged by XGEM framer,
XGEM frame is obtained, XGEM framer determines the reading start bit of XGEM content frame by the initial address of each frame delineation of reading
Set, encapsulation process thereafter include the addition of XGEM frame head, CRC rerun, XGEM as defined in the XGPON agreement such as XGEM frame fragment framing
Framing operation.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112084136A (en) * | 2020-07-23 | 2020-12-15 | 西安电子科技大学 | Queue cache management method, system, storage medium, computer device and application |
| CN113115132A (en) * | 2021-03-01 | 2021-07-13 | 烽火通信科技股份有限公司 | Method and device for recombining frames in OLT (optical line terminal) |
| CN114449192A (en) * | 2020-11-04 | 2022-05-06 | 格科微电子（上海）有限公司 | Virtual active image acquisition equipment and data transmission method, storage medium and terminal thereof |
| CN115801181A (en) * | 2022-10-14 | 2023-03-14 | 北京机电工程研究所 | Digital quantity telemetering method based on double-cache structure |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006001073A1 (en) * | 2004-06-25 | 2006-01-05 | Mitsubishi Denki Kabushiki Kaisha | Pon system telephone accommodating port testing method and pon system |
| CN101764647A (en) * | 2009-12-17 | 2010-06-30 | 浙江工业大学 | ONU (Optical Network Unit) management and control platform of GPON (Gigabit Passive Optical Network) network management system |
| CN102045130A (en) * | 2009-10-20 | 2011-05-04 | 华为技术有限公司 | Downlink framing method, optical line terminal and passive optical network system |
| CN103117954A (en) * | 2013-01-09 | 2013-05-22 | 烽火通信科技股份有限公司 | Method for acceleratedly processing PLOAM information of optical network unit (PLO) terminal of XG-PON1 system |
| CN103152292A (en) * | 2013-03-14 | 2013-06-12 | 烽火通信科技股份有限公司 | Device and method for framing XGEM (XGPON Encapsulation Method) in ONU (Optical Network Unit) in XGPON (XG-Passive Optical Network) system |
| CN105450324A (en) * | 2016-01-07 | 2016-03-30 | 烽火通信科技股份有限公司 | ONU-end time synchronization method and apparatus of XG-PON1 system |
| CN105592373A (en) * | 2014-11-07 | 2016-05-18 | 中兴通讯股份有限公司 | Work channel regulation method, device and system, ONU and OLT |
| CN109040868A (en) * | 2018-08-07 | 2018-12-18 | 烽火通信科技股份有限公司 | The method and system of ONU end uplink framing in a kind of XGSPON |
-
2019
- 2019-03-27 CN CN201910236227.9A patent/CN109981496B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006001073A1 (en) * | 2004-06-25 | 2006-01-05 | Mitsubishi Denki Kabushiki Kaisha | Pon system telephone accommodating port testing method and pon system |
| CN102045130A (en) * | 2009-10-20 | 2011-05-04 | 华为技术有限公司 | Downlink framing method, optical line terminal and passive optical network system |
| CN101764647A (en) * | 2009-12-17 | 2010-06-30 | 浙江工业大学 | ONU (Optical Network Unit) management and control platform of GPON (Gigabit Passive Optical Network) network management system |
| CN103117954A (en) * | 2013-01-09 | 2013-05-22 | 烽火通信科技股份有限公司 | Method for acceleratedly processing PLOAM information of optical network unit (PLO) terminal of XG-PON1 system |
| CN103152292A (en) * | 2013-03-14 | 2013-06-12 | 烽火通信科技股份有限公司 | Device and method for framing XGEM (XGPON Encapsulation Method) in ONU (Optical Network Unit) in XGPON (XG-Passive Optical Network) system |
| CN105592373A (en) * | 2014-11-07 | 2016-05-18 | 中兴通讯股份有限公司 | Work channel regulation method, device and system, ONU and OLT |
| CN105450324A (en) * | 2016-01-07 | 2016-03-30 | 烽火通信科技股份有限公司 | ONU-end time synchronization method and apparatus of XG-PON1 system |
| CN109040868A (en) * | 2018-08-07 | 2018-12-18 | 烽火通信科技股份有限公司 | The method and system of ONU end uplink framing in a kind of XGSPON |
Non-Patent Citations (1)
| Title |
|---|
| 麻鑫锋等: ""GPON网管系统中OMCI协议的研究和实现"", 《光通信技术》 * |
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|---|---|---|---|---|
| CN112084136A (en) * | 2020-07-23 | 2020-12-15 | 西安电子科技大学 | Queue cache management method, system, storage medium, computer device and application |
| CN112084136B (en) * | 2020-07-23 | 2022-06-21 | 西安电子科技大学 | Queue cache management method, system, storage medium, computer device and application |
| CN114449192A (en) * | 2020-11-04 | 2022-05-06 | 格科微电子（上海）有限公司 | Virtual active image acquisition equipment and data transmission method, storage medium and terminal thereof |
| CN114449192B (en) * | 2020-11-04 | 2024-02-27 | 格科微电子（上海）有限公司 | Virtual active image acquisition device, data transmission method thereof, storage medium and terminal |
| CN113115132A (en) * | 2021-03-01 | 2021-07-13 | 烽火通信科技股份有限公司 | Method and device for recombining frames in OLT (optical line terminal) |
| CN115801181A (en) * | 2022-10-14 | 2023-03-14 | 北京机电工程研究所 | Digital quantity telemetering method based on double-cache structure |
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