CN207302594U - Shifting deposit unit, gate driving circuit and display device - Google Patents
Shifting deposit unit, gate driving circuit and display device Download PDFInfo
- Publication number
- CN207302594U CN207302594U CN201721411630.3U CN201721411630U CN207302594U CN 207302594 U CN207302594 U CN 207302594U CN 201721411630 U CN201721411630 U CN 201721411630U CN 207302594 U CN207302594 U CN 207302594U
- Authority
- CN
- China
- Prior art keywords
- shifting deposit
- node
- deposit unit
- switching transistor
- clock signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn - After Issue
Links
Abstract
The utility model discloses a kind of shifting deposit unit, gate driving circuit and display device, wherein shifting deposit unit includes the first input module, the second input module, first node control module, section point control module, the 3rd node control module and N number of output module, and the first input module, the second input module and first node control module are used to be controlled first node；Section point control module is used to be controlled section point, so that the 3rd node control module is controlled the 3rd node according to section point and first node, and N number of output module is respectively used under the control of first node be controlled corresponding output terminal according to corresponding clock signal terminal.The shifting deposit unit controls multiple output terminals by multiple output modules, therefore a shifting deposit unit can connect a plurality of grid line, when the shifting deposit unit is applied to display panel, it is possible to reduce the quantity of shifting deposit unit, is conducive to narrow frame design.
Description
Technical field
Display technology field is the utility model is related to, espespecially a kind of shifting deposit unit, gate driving circuit and display dress
Put.
Background technology
In TFT thin film transistor monitor, each thin film transistor (TFT) usually by gate driving circuit to pixel region
The grid of (TFT, Thin Film Transistor) provides gate drive signal.Gate driving circuit can pass through array processes
It is formed on the array base palte of liquid crystal display, i.e. array base palte row driving (Gate Driver on Array, GOA) technique,
This integrated technique not only saves cost, and can accomplish the symmetrical design for aesthetic in liquid crystal panel (Panel) both sides, together
When, also eliminate binding (Bonding) region of grid integrated circuits (IC, Integrated Circuit) and be fanned out to
(Fan-out) wiring space, so as to realize the design of narrow frame；Also, this integrated technique may be omitted with grid
The Bonding techniques of scan-line direction, so as to improve production capacity and yield.
At present, existing gate driving circuit is made of the cascade of multiple shifting deposit units, per level-one shifting deposit unit
It is mainly used for sending scanning signal to a corresponding scan line on display panel.But with display panel resolution ratio by
Gradually improve, the quantity of shifting deposit unit also gradually increases in gate driving circuit, so as to be unfavorable for narrow frame design.
Utility model content
The utility model embodiment provides a kind of shifting deposit unit, gate driving circuit and display device, to realize
Narrow frame design.
The utility model embodiment provide a kind of shifting deposit unit, including the first input module, the second input module,
First node control module, section point control module, the 3rd node control module and N number of output module, wherein N are more than 1
Integer；
First input module, for being supplied to the signal at the first reference potential end under the control at input signal end
First node；
Second input module, for being supplied to the signal at the second reference potential end under the control at reset signal end
The first node；
The first node control module, for providing the signal at the 4th reference potential end under the control of the 3rd node
To the first node；
The section point control module, under the control at the first reference potential end by the first clock signal terminal
Signal be supplied to section point, the signal of second clock signal end is supplied under the control at the second reference potential end
The section point；
3rd node control module, under the control of the section point by the signal at the 3rd reference potential end
The 3rd node is supplied to, the signal at the 4th reference potential end is supplied to the described 3rd under the control of the first node
Node；
In N number of output module, n-th of output module is used for n-th+2 under the control of the first node
The signal of clock signal terminal is supplied to n-th of output terminal, and n takes any integer more than 0 and less than or equal to N.
Alternatively, in the shifting deposit unit that the utility model embodiment provides, first input module includes：The
One switching transistor；Second input module includes：Second switch transistor；
The grid of the first switch transistor is connected with the input signal end, and the first of the first switch transistor
Pole is connected with the first reference potential end, and the second pole of the first switch transistor is connected with the first node；
The grid of the second switch transistor is connected with the reset signal end, and the first of the second switch transistor
Pole is connected with the second reference potential end, and the second pole of the second switch transistor is connected with the first node.
Alternatively, in the shifting deposit unit that the utility model embodiment provides, the section point control module bag
Include：3rd switching transistor and the 4th switching transistor；
The grid of 3rd switching transistor is connected with the first reference potential end, the 3rd switching transistor
First pole is connected with first clock signal terminal, and the second pole of the 3rd switching transistor is connected with the section point；
The grid of 4th switching transistor is connected with the second reference potential end, the 4th switching transistor
First pole is connected with the second clock signal end, and the second pole of the 4th switching transistor is connected with the section point.
Alternatively, in the shifting deposit unit that the utility model embodiment provides, the 3rd node control module bag
Include：5th switching transistor and the 6th switching transistor；
The grid of 5th switching transistor is connected with the section point, the first pole of the 5th switching transistor
It is connected with the 3rd reference potential end, the second pole of the 5th switching transistor is connected with the 3rd node；
The grid of 6th switching transistor is connected with the first node, the first pole of the 6th switching transistor
It is connected with the 4th reference potential end, the second pole of the 6th switching transistor is connected with the 3rd node.
Alternatively, in the shifting deposit unit that the utility model embodiment provides, the first node control module bag
Include：7th switching transistor；
The grid of 7th switching transistor is connected with the 3rd node, the first pole of the 7th switching transistor
It is connected with the 4th reference potential end, the second pole of the 7th switching transistor is connected with the first node.
Alternatively, in the shifting deposit unit that the utility model embodiment provides, the shifting deposit unit further includes：
Current potential keeps module, wherein the current potential keeps module to include：First capacitance and the second capacitance；
First capacitance connection is between the first node and the 4th reference potential end；
Second capacitance connection is between the 3rd node and the 4th reference potential end.
Alternatively, in the shifting deposit unit that the utility model embodiment provides, each output module includes：One
A 8th switching transistor；
In n-th of output module, the grid of the 8th switching transistor is connected with the first node, and described
First pole of eight switching transistors is connected with n-th+2 clock signal terminal, the second pole of the 8th switching transistor and institute
State n-th of output terminal connection.
Alternatively, in the shifting deposit unit that the utility model embodiment provides, each output module further includes：
One the 9th switching transistor；
The grid of 9th switching transistor is connected by the 9th switching transistor with the first node, and institute
The grid for stating the 9th switching transistor is connected with the 3rd reference potential end.
Alternatively, in the shifting deposit unit that the utility model embodiment provides, the shifting deposit unit further includes：
Reseting module is exported correspondingly with each output terminal；
The output reseting module corresponding with n-th of output terminal is used for described the under the control of the 3rd node
The signal at four reference potential ends is supplied to n-th of output terminal.
Alternatively, in the shifting deposit unit that the utility model embodiment provides, the output reseting module includes：The
Ten switching transistors；
The grid of tenth switching transistor is connected with the 3rd node, the first pole of the tenth switching transistor
It is connected with the 4th reference potential end；
In the output reseting module corresponding with n-th of output terminal, the second pole of the tenth switching transistor and institute
State n-th of output terminal connection.
Alternatively, in the shifting deposit unit that the utility model embodiment provides, the shifting deposit unit further includes：
Discharge module；
The discharge module is used to be supplied to the signal at the 4th reference potential end under the control of enabled control terminal
3rd node.
Alternatively, in the shifting deposit unit that the utility model embodiment provides, the discharge module includes：11st
Switching transistor；
The grid of 11st switching transistor is connected with the enabled control terminal, the 11st switching transistor
First pole is connected with the 4th reference potential end, and the second pole and the section point of the 11st switching transistor connect
Connect.
Correspondingly, the utility model embodiment additionally provides a kind of gate driving circuit, including at least one by cascading
The cascade circuit of multiple shifting deposit unit compositions, the shifting deposit unit are above-mentioned that the utility model embodiment provides
A kind of shifting deposit unit；
In the cascade circuit, in addition to afterbody shifting deposit unit, per the n-th of level-one shifting deposit unit
Output terminal is connected with the input signal end of next stage shifting deposit unit；
In addition to first order shifting deposit unit, first output terminal per level-one shifting deposit unit is shifted with upper level
The reset signal end of deposit unit is connected.
Alternatively, in the gate driving circuit that the utility model embodiment provides, including two cascade circuits, and
The shifting deposit unit includes two output modules；
In first cascade circuit：The first clock signal terminal and even level shift LD of odd level shifting deposit unit
3rd clock signal terminal of unit is connected with the 5th clock cable；The second clock signal end of odd level shifting deposit unit
It is connected with the 4th clock signal terminal of even level shifting deposit unit with the 6th clock cable；Odd level shifting deposit unit
The 3rd clock signal terminal and the first clock signal terminal of even level shifting deposit unit be connected with the first clock cable；Odd number
Level the 4th clock signal terminal of shifting deposit unit and the second clock signal end and second clock of even level shifting deposit unit
Signal wire connects；
In second cascade circuit：The first clock signal terminal and even level shift LD of odd level shifting deposit unit
3rd clock signal terminal of unit is connected with the 7th clock cable；The second clock signal end of odd level shifting deposit unit
It is connected with the 4th clock signal terminal of even level shifting deposit unit with the 8th clock cable；Odd level shifting deposit unit
The 3rd clock signal terminal and the first clock signal terminal of even level shifting deposit unit be connected with the 3rd clock cable；Odd number
Level the 4th clock signal terminal of shifting deposit unit and the second clock signal end and the 4th clock of even level shifting deposit unit
Signal wire connects；
Wherein, the clock signal that the first clock cable is exported to the 8th clock cable differed for 1/8 clock cycle successively.
Correspondingly, the utility model embodiment additionally provides a kind of display device, including the utility model embodiment provides
Above-mentioned gate driving circuit.
The utility model has the beneficial effect that：
Above-mentioned shifting deposit unit, gate driving circuit and the display device that the utility model embodiment provides, wherein moving
Position deposit unit includes：First input module, the second input module, first node control module, section point control module,
Three node control modules and N number of output module, wherein N are the integer more than 1；Wherein, the first input module is used for according to input
Signal end is controlled first node；Second input module is used to be controlled first node according to reset signal end；The
One node control module is used to be controlled first node according to the 3rd node；Section point control module is used for according to first
Clock signal terminal and second clock signal end are controlled section point, so that the 3rd node control module is according to section point
The 3rd node is controlled with first node, and N number of output module is respectively used under the control of first node according to correspondence
Clock signal terminal corresponding output terminal is controlled.The shifting deposit unit that the utility model embodiment provides passes through multiple
Output module controls multiple output terminals, therefore a shifting deposit unit can connect a plurality of grid line, when the shifting deposit unit
During applied to display panel, it is possible to reduce the quantity of shifting deposit unit, is conducive to narrow frame design.
Brief description of the drawings
Fig. 1 is one of structure diagram of shifting deposit unit that the utility model embodiment provides；
Fig. 2 is the second structural representation for the shifting deposit unit that the utility model embodiment provides；
Fig. 3 is the third structural representation for the shifting deposit unit that the utility model embodiment provides；
Fig. 4 is the four of the structure diagram for the shifting deposit unit that the utility model embodiment provides；
Fig. 5 is the five of the structure diagram for the shifting deposit unit that the utility model embodiment provides；
Fig. 6 is the six of the structure diagram for the shifting deposit unit that the utility model embodiment provides；
Fig. 7 is the seven of the structure diagram for the shifting deposit unit that the utility model embodiment provides；
Fig. 8 is one of structure diagram of gate driving circuit that the utility model embodiment provides；
Fig. 9 a are the corresponding sequence diagram of first grid drive circuit shown in Fig. 8；
Fig. 9 b are the corresponding sequence diagram of second grid drive circuit shown in Fig. 8；
Figure 10 is the overall corresponding sequence diagram of two gate driving circuits shown in Fig. 8；
Figure 11 is the second structural representation for the gate driving circuit that the utility model embodiment provides；
Figure 12 is the sequence diagram of the gate driving circuit shown in Figure 11；
Figure 13 is one of corresponding sequence diagram of shifting deposit unit that the utility model embodiment provides；
Figure 14 is the two of the corresponding sequence diagram of shifting deposit unit that the utility model embodiment provides.
Embodiment
In order to make the purpose of this utility model, technical solution and advantage clearer, below in conjunction with attached drawing to this practicality
It is new to be described in further detail, it is clear that described embodiment is only the utility model part of the embodiment, rather than entirely
The embodiment in portion.Based on the embodiment in the utility model, those of ordinary skill in the art are not before creative work is made
The all other embodiment obtained is put, shall fall within the protection scope of the present invention.
The shapes and sizes of each component do not reflect actual proportions in attached drawing, and purpose is in schematically illustrate the utility model
Hold.
A kind of shifting deposit unit that the utility model embodiment provides, as shown in Figure 1, including the first input module 1, the
Two input modules 2, first node control module 3, section point control module 4, the 3rd node control module 5 and N number of output mould
Block 6_n, wherein N are integer more than 1, n=1,2,3 ... what N, Fig. 1 were illustrated by taking N=2 as an example.
First input module 1, for providing the signal of the first reference potential end CN under the control of input signal end In
Give first node PUCN；
Second input module 2, under the control of reset signal end Reset by the signal of the second reference potential end CNB
It is supplied to first node PUCN；
First node control module 3, for carrying the signal of the 4th reference potential end VGL under the control of the 3rd node PD
Supply first node PUCN；
Section point control module 4, under the control of the first reference potential end CN by the first clock signal terminal CK1's
Signal is supplied to section point PN, provides the signal of second clock signal end CK2 under the control of the second reference potential end CNB
Give section point PN；
3rd node control module 5, for carrying the signal of the 3rd reference potential end VGH under the control of section point PN
The 3rd node PD is supplied, the signal of the 4th reference potential end VGL is supplied to the 3rd node under the control of first node PUCN
PD；
Into 6_N, n-th of output module 6_n is used for n-th under the control of first node PUCN N number of output module 6_1
The signal of+2 clock signal terminal CKn+2 is supplied to n-th of output terminal, and n takes any integer more than 0 and less than or equal to N.
The shifting deposit unit that the utility model embodiment provides, including the first input module, the second input module, first
Node control module, section point control module, the 3rd node control module and N number of output module, wherein N are whole more than 1
Number；Wherein, the first input module is used to be controlled first node according to input signal end；Second input module is used for basis
Reset signal end is controlled first node；First node control module is used to control first node according to the 3rd node
System；Section point control module is used to be controlled section point according to the first clock signal terminal and second clock signal end,
So that the 3rd node control module is controlled the 3rd node according to section point and first node, and N number of output module point
Corresponding output terminal Yong Yu be controlled according to corresponding clock signal terminal under the control of first node.The utility model
The shifting deposit unit that embodiment provides controls multiple output terminals by multiple output modules, therefore a shifting deposit unit can
To connect a plurality of grid line, when the shifting deposit unit is applied to display panel, it is possible to reduce the quantity of shifting deposit unit, has
Beneficial to narrow frame design.
In the specific implementation, when the shifting deposit unit that the utility model embodiment provides is applied to display panel, move
Each output module corresponds to a grid line of display panel, therefore, the shifting that the utility model embodiment provides in the deposit unit of position
Output module is more in the deposit unit of position, during applied to display panel, it is necessary to shifting deposit unit quantity it is fewer.But
It is, since each output module is controlled by first node in shifting deposit unit, respectively to be exported in shifting deposit unit
The quantity of module is more, it is necessary to and the current potential of first node can be kept for a long time, but under normal circumstances, first node
Current potential will decay after being kept for one end time, and the current potential of first node once decaying, stablize by the output that will influence output terminal
Property.Therefore, in the shifting deposit unit that the utility model embodiment provides, 2 output modules or 3 output moulds are preferably provided with
Block.More output modules can certainly be set, be not limited thereto.
With reference to specific embodiment, the utility model is described in detail.It should be noted that it is in the present embodiment
In order to preferably explain the utility model, but do not limit the utility model.
Alternatively, in the shifting deposit unit that the utility model embodiment provides, as shown in Figures 2 to 6, the first input
Module 1 includes：First switch transistor T1；
The grid of first switch transistor T1 is connected with input signal end IN, the first pole of first switch transistor T1 and the
One reference potential end CN connections, the second pole of first switch transistor T1 is connected with first node PUCN.
Specifically, when being turned under control of the first switch transistor at input signal end, by the first reference potential end
Signal is supplied to first node, and the voltage of first node is controlled.
It the above is only the concrete structure for illustrating the first input module in shifting deposit unit, in the specific implementation, the
The concrete structure of one input module is not limited to the said structure of the utility model embodiment offer, can also be people in the art
Other structures knowable to member, do not limit herein.
Alternatively, in the shifting deposit unit that the utility model embodiment provides, as shown in Figures 2 to 6, the second input
Module 2 includes：Second switch transistor T2；
The grid of second switch transistor T2 is connected with reset signal end Reset, the first pole of second switch transistor T2
It is connected with the second reference potential end CNB, the second pole of second switch transistor T2 is connected with first node PUCN.
Specifically, when being turned under control of the second switch transistor at reset signal end, by the second reference potential end
Signal is supplied to first node, and the voltage of first node is controlled.
It the above is only the concrete structure for illustrating the second input module in shifting deposit unit, in the specific implementation, the
The concrete structure of two input modules is not limited to the said structure of the utility model embodiment offer, can also be people in the art
Other structures knowable to member, do not limit herein.
Alternatively, in the shifting deposit unit that the utility model embodiment provides, as shown in Figures 2 to 6, section point
Control module 4 includes：3rd switching transistor T3 and the 4th switching transistor T5；
The grid of 3rd switching transistor T3 is connected with the first reference potential end CN, the first pole of the 3rd switching transistor T3
It is connected with the first clock signal terminal CK1, the second pole of the 3rd switching transistor T3 is connected with section point PN；
The grid of 4th switching transistor T4 is connected with the second reference potential end CNB, and the first of the 4th switching transistor T4
Pole is connected with second clock signal end CK2, and the second pole of the 4th switching transistor T4 is connected with section point PN.
Specifically, when being turned under control of the 3rd switching transistor at the first reference potential end, by the first clock signal
The signal at end is supplied to section point, alternatively, when being turned under control of the 4th switching transistor at the second reference potential end, will
The signal of second clock signal end is supplied to section point, and the voltage of section point is controlled.
It the above is only the concrete structure for illustrating section point control module in shifting deposit unit, be embodied
When, the concrete structure of section point control module is not limited to the said structure of the utility model embodiment offer, can also be this
Other structures knowable to field technology personnel, do not limit herein.
Alternatively, in the shifting deposit unit that the utility model embodiment provides, as shown in Figures 2 to 6, the 3rd node
Control module 5 includes：5th switching transistor T5 and the 6th switching transistor T6；
The grid of 5th switching transistor T5 is connected with section point PN, the first pole and the 3rd of the 5th switching transistor T5
The VGH connections of reference potential end, the second pole of the 5th switching transistor T5 is connected with the 3rd node PD；
The grid of 6th switching transistor T6 is connected with first node PUCN, the first pole of the 6th switching transistor T6 and the
Four reference potential end VGL connections, the second pole of the 6th switching transistor T6 is connected with the 3rd node PD.
Specifically, when the 5th switching transistor turns under the control of section point, by the letter at the 3rd reference potential end
Number the 3rd node is supplied to, alternatively, when the 6th switching transistor turns under the control of first node, by the 4th reference potential
The signal at end is supplied to the 3rd node, and the voltage of the 3rd node is controlled.
It the above is only the concrete structure for illustrating the 3rd node control module in shifting deposit unit, be embodied
When, the concrete structure of the 3rd node control module is not limited to the said structure of the utility model embodiment offer, can also be this
Other structures knowable to field technology personnel, do not limit herein.
Alternatively, in the shifting deposit unit that the utility model embodiment provides, as shown in Figures 2 to 6, first node
Control module 3 includes：7th switching transistor T7；
The grid of 7th switching transistor T7 is connected with the 3rd node PD, the first pole and the 4th of the 7th switching transistor T7
The VGL connections of reference potential end, the second pole of the 7th switching transistor T7 is connected with first node PU.
Specifically, when the 7th switching transistor turns under the control of the 3rd node, by the letter at the 4th reference potential end
Number first node is supplied to, the voltage of first node is controlled.
It the above is only the concrete structure for illustrating first node control module in shifting deposit unit, be embodied
When, the concrete structure of first node control module is not limited to the said structure of the utility model embodiment offer, can also be this
Other structures knowable to field technology personnel, do not limit herein.
Alternatively, in the shifting deposit unit that the utility model embodiment provides, as shown in Figures 4 to 6, shift LD
Unit further includes：Current potential keeps module 7, and wherein current potential keeps module 7 to include：First capacitance C1 and the second capacitance C2；
First capacitance C1 is connected between first node PUCN and the 4th reference potential end VGL；
Second capacitance C2 is connected between the 3rd node PD and the 4th reference potential end VGL.
Specifically, when first node is in floating (floating), the first capacitance is used to keep first node
Current potential, to slow down the decay of first node current potential.Similarly, when section point is in floating, the second capacitance is used to keep
The current potential of section point, to slow down the decay of section point current potential.
Alternatively, in the shifting deposit unit that the utility model embodiment provides, as shown in Figures 2 to 6, each output
Module 6_n includes：One the 8th switching transistor T8n；
In n-th of output module 6_n, the 8th switching transistor T8nGrid be connected with first node PUCN, the 8th switch
Transistor T8nThe first pole be connected with the n-th+2 clock signal terminal CKn+2, the 8th switching transistor T8nThe second pole and n-th it is defeated
Outlet OUTn connections.
Such as Fig. 2, into Fig. 6, wherein Fig. 2 to Fig. 6 is that shifting deposit unit includes being said exemplified by 2 output modules
Bright.First output module 6_1 includes：8th switching transistor T81, the 8th switching transistor T81The second pole with the 1st
Output terminal OUT1 connections；Second output module 6_2 includes：8th switching transistor T82, the 8th switching transistor T82Second
Pole is connected with the 2nd output terminal OUT2.
Specifically, when first node controls the 8th switching transistor conducting in each output module, each output terminal difference
The 3rd clock signal terminal is exported to the signal of N+2 clock signal terminals, therefore, during by setting the 3rd clock signal terminal to N+2
The sequential of the clock signal of clock signal end, it is possible to realize that output terminal exports signal line by line.
Alternatively, in the shifting deposit unit that the utility model embodiment provides, as shown in Figures 3 to 6, each output
Module 6_n is further included：One the 9th switching transistor T9n；
8th switching transistor T8nGrid pass through the 9th switching transistor T9nIt is connected with first node PUCN, and the 9th
Switching transistor T9nGrid be connected with the 3rd reference potential end VGH.
Specifically, the 3rd reference potential end controls the 9th switching transistor in the conduction state, so that the 8th switch is brilliant
The grid of body pipe is connected by the 9th switching transistor of conducting with first node, this is direct with the grid of the 8th switching transistor
Compared with first node, the leakage current of the grid of the 8th switching transistor can be reduced, so as to keep the 8th switching transistor
Grid potential.
It the above is only the concrete structure for illustrating each output module in shifting deposit unit, in the specific implementation, output
The concrete structure of module be not limited to the utility model embodiment offer said structure, can also be skilled person will appreciate that
Other structures, do not limit herein.
Alternatively, in the shifting deposit unit that the utility model embodiment provides, as shown in Figure 5 and Figure 6, shift LD
Unit further includes：Reseting module 8_n is exported correspondingly with each output terminal OUTn；
Output reseting module 8_n corresponding with n-th of output terminal OUTn is used for the 4th under the control of the 3rd node PD
The signal of reference potential end VGL is supplied to n-th of output terminal OUTn.
Alternatively, in the shifting deposit unit that the utility model embodiment provides, as shown in fig. 6, output reseting module
8_n includes：Tenth switching transistor T10n；
Tenth switching transistor T10nGrid be connected with the 3rd node PD, the tenth switching transistor T10nThe first pole with
4th reference potential end VGL connections；
In output reseting module 8_n corresponding with n-th of output terminal OUTn, the tenth switching transistor T10nThe second pole with
N-th of output terminal OUTn connection.
Specifically, when the tenth switching transistor turns under the control of the 3rd node, by the letter at the 4th reference potential end
Number corresponding output terminal is supplied to, corresponding output terminal is resetted, it is steady further to stablize the circuit of shifting deposit unit
It is qualitative.
It the above is only the concrete structure for illustrating each output reseting module in shifting deposit unit, in the specific implementation,
The concrete structure of output reseting module is not limited to the said structure of the utility model embodiment offer, can also be art technology
Other structures knowable to personnel, do not limit herein.
Alternatively, in the shifting deposit unit that the utility model embodiment provides, as shown in fig. 6, shifting deposit unit
Further include：Discharge module 9；
Discharge module 9 is used under the control of enabled control terminal EN the signal of the 4th reference potential end VGL being supplied to the
Three node PD.
Alternatively, in the shifting deposit unit that the utility model embodiment provides, as shown in fig. 6, discharge module 9 wraps
Include：11st switching transistor T11；
The grid of 11st switching transistor T11 is connected with enabled control terminal EN, and the first of the 11st switching transistor T11
Pole is connected with the 4th reference potential end VGL, and the second pole of the 11st switching transistor T11 is connected with the 3rd node PD.
Specifically, in display panel, after a frame scan, control of the 11st switching transistor in enabled control terminal
The lower conducting of system, is supplied to the 3rd node by the signal at the 4th reference potential end, corresponding output terminal is resetted, with further
Stablize the circuit stability of shifting deposit unit.
It the above is only the concrete structure for illustrating discharge module in shifting deposit unit, in the specific implementation, discharge mould
The concrete structure of block be not limited to the utility model embodiment offer said structure, can also be skilled person will appreciate that
Other structures, do not limit herein.
Specifically, in order to which manufacture craft is unified, in the shifting deposit unit that the utility model embodiment provides, such as Fig. 2 extremely
Shown in Fig. 6, all switching transistors are N-type transistor.Alternatively, as shown in fig. 7, all switching transistors are P-type crystal
Pipe.
Specifically, in the utility model embodiment offer with deposit unit, N-type transistor is made in high potential signal
With lower conducting, end under low-potential signal effect；P-type transistor turns under low-potential signal effect, in high potential signal
The lower cut-off of effect.
Specifically, in the shifting deposit unit that the utility model embodiment provides, the first of transistor extremely can be source
Pole, second extremely drains, or transistor first can be extremely drain electrode, and the second extremely source electrode, is not distinguished specifically herein.
It should be noted that in the shifting deposit unit that the utility model embodiment provides, when all transistors are N
During transistor npn npn, the signal at the 3rd reference potential end is high potential signal, and the signal at the 4th reference potential end is low-potential signal；
When all transistors are P-type transistor, the signal at the 3rd reference potential end is low-potential signal, the 4th reference potential end
Signal is high potential signal.
Specifically, in the shifting deposit unit that the utility model embodiment provides, from the point of view of leakage current is reduced,
Any switching transistor could be provided as double-gate structure, be not limited thereto.
Specifically, in the above-mentioned shifting deposit unit that the utility model embodiment provides, the first input module and second
Input module is symmetric design, it is possible to achieve exchange function, therefore the above-mentioned shift register that the utility model embodiment provides
It can realize bilateral scanning.During forward scan, the first input module is used as input module, and the second input module is as reset mould
Block is used.During reverse scan, the second input module is used as input module, and the first input module is used as reseting module.
When all switching transistors are N-type transistor, in forward scan, the current potential at the first reference potential end is height
Current potential, the current potential at the second reference potential end is low potential.During reverse scan, the current potential at the first reference potential end is low potential, the
The current potential at two reference potential ends is high potential.
When all switching transistors are P-type transistor, in forward scan, the current potential at the first reference potential end is low
Current potential, the current potential at the second reference potential end is high potential.During reverse scan, the current potential at the first reference potential end is high potential, the
The current potential at two reference potential ends is low potential.
Conceived based on same utility model, the utility model embodiment additionally provides a kind of gate driving circuit, due to grid
The principle that pole drive circuit solves the problems, such as is similar to a kind of foregoing shifting deposit unit, therefore the implementation of the gate driving circuit can
With referring to the implementation of aforementioned shift deposit unit, overlaps will not be repeated.
Specifically, it is more by what is cascaded including at least one in the gate driving circuit that the utility model embodiment provides
The cascade circuit of a shifting deposit unit composition；
In cascade circuit, in addition to afterbody shifting deposit unit, the n-th output per level-one shifting deposit unit
End is connected with the input signal end of next stage shifting deposit unit；
In addition to first order shifting deposit unit, first output terminal per level-one shifting deposit unit is shifted with upper level
The reset signal end of deposit unit is connected.
Specifically, the scan line that gate driving circuit is used on to display panel provides scanning signal, due to display surface
Scan line on plate is relatively more, thus the quantity of shifting deposit unit corresponding with scan line also compared with it is more, therefore in view of aobvious
Show the border width of panel, two cascade circuits, one of cascade electricity are set in design generally in gate driving circuit
Road is placed on the left frame of display panel, another cascade circuit is placed on the left frame of display panel.
There are two output modules with level-one shifting deposit unit below, that is, have and illustrate exemplified by two output terminals, it is right
There are more output modules in level-one shifting deposit unit, can be carried out according to the example with two output modules
Analogize, be not limited thereto.
Specifically, as shown in figure 8, the both sides of display panel are respectively arranged with the first cascade circuit 101 and the second cascade electricity
Road 102, in each cascade circuit, is all connected with two scan line Scan, it is possible to achieve two-stage is continuous per level-one shifting deposit unit
Output, wherein, in the first cascade circuit 101, including shifting deposit unit：VSR_1L, VSR_2L ... VSR_NL, odd number
Level shifting deposit unit the first clock signal terminal CK1 and even level shifting deposit unit the 3rd clock signal terminal CK3 with
5th clock cable clk5 connections；The second clock signal end CK2 and even level shift LD of odd level shifting deposit unit
4th clock signal terminal CK4 of unit is connected with the 6th clock cable clk6；Odd level shifting deposit unit the 3rd when
First clock signal terminal CK1 of clock signal end CK3 and even level shifting deposit unit is connected with the first clock cable clk1；Very
4th clock signal terminal CK4 of the several levels shifting deposit unit and second clock signal end CK2 of even level shifting deposit unit with
The clk2 connections of second clock signal wire；The sequence diagram of the corresponding forward scan of first cascade circuit is as illustrated in fig. 9.In the second level
Join in circuit 102, the first clock signal terminal CK1 of odd level shifting deposit unit and even level shifting deposit unit the 3rd when
Clock signal end CK3 is connected with the 7th clock cable clk7；The second clock signal end CK2 of odd level shifting deposit unit and
4th clock signal terminal CK4 of even level shifting deposit unit is connected with the 8th clock cable clk8；Odd level displacement is posted
3rd clock signal terminal CK3 of memory cell and the first clock signal terminal CK1 of even level shifting deposit unit with the 3rd clock
Signal wire clk3 connections；4th clock signal terminal CK4 of odd level shifting deposit unit and the of even level shifting deposit unit
Two clock signal terminal CK2 are connected with the 4th clock cable clk4；The sequence diagram of the corresponding forward scan of second cascade circuit
As shown in figure 9b.Wherein, the first clock cable clk1 to the 8th clock cable clk8 clock signals exported differ successively
1/8 clock cycle.The sequence diagram of the overall corresponding forward scan of gate driving circuit is as shown in Figure 10.
Specifically, as shown in figure 8, in cascade circuit, the of the input signal end IN connections of kth level shifting deposit unit
Second output terminal OUT2 of k-1 grades of shifting deposit units, the kth of the reset signal end Reset connections of kth level shifting deposit unit
First output terminal OUT of+1 grade of shifting deposit unit, the input signal end IN of first order shifting deposit unit and it is last and
The reset signal end Reset of shifting deposit unit is connected with signal wire STVL or STVR.
Certainly, in the specific implementation, the corresponding shifting deposit unit of each scan line in display panel can also be integrated in
The side of display panel, i.e., all scan lines of one gate driving circuit connection display panel.As shown in figure 11, raster data model
Circuit 100 includes 1 cascade circuit, specifically includes shifting deposit unit：VSR_1, VSR_2 ... VSR_N, is connected with 4
Clock cable is respectively clk1, clk2, clk3, clk4, and the kth of the input signal end IN connections of kth level shifting deposit unit-
Second output terminal OUT2 of 1 grade of shifting deposit unit, the kth+1 of the reset signal end Reset connections of kth level shifting deposit unit
First output terminal OUT of level shifting deposit unit, the input signal end of first order shifting deposit unit and last and displacement
The reset signal end of deposit unit is connected with signal wire STV, and the sequence diagram of the corresponding forward scan of raster data model is as shown in figure 12.
Below by taking forward scan as an example, combined circuit sequence diagram describes this practicality in detail with wherein level-one shifting deposit unit
The course of work for the gate driving circuit that new embodiment provides is described.High potential is represented with 1,0 represents in described below
Low potential.It should be noted that 1 and 0 is logic level, it is merely to preferably explain the specific of the utility model embodiment
The course of work, rather than specific magnitude of voltage.
By taking the gate driving circuit that shifting deposit unit is applied to shown in Fig. 8 as an example.
Example one,
By taking the shifting deposit unit shown in Fig. 3 as an example, wherein CN=1, CNB=0, VGH=1, VGL=0, corresponding sequential
Figure is as shown in 13 figures.
In the PI stages, IN=1, Reset=0, CK1=0, CK2=0, CK3=0, CK4=0.
IN=1, first switch transistor T1 are turned on, the high potential signal of the first reference potential end CN pass through conducting first
Switching transistor T1 is transmitted to first node PUCN, and the current potential of first node PUCN is high potential, and the 6th switching transistor T6 is led
It is logical.Due to VGH=1, the 9th switching transistor T91And T92Conducting, the first control node PU1 and the second control node PU2
Current potential be high potential, the 8th switching transistor T81And T82Conducting, the low-potential signal of the 3rd clock signal terminal CK3 is by leading
The 8th logical switching transistor T81The current potential for being transmitted to the first output terminal OUT1, the first output terminal OUT1 is low potential, when the 4th
The 8th switching transistor T8 that the low-potential signal of clock signal end CK4 passes through conducting2The second output terminal OUT2 is transmitted to, second is defeated
The current potential of outlet OUT2 is low potential, the 6th switching transistor that the low-potential signal of the 4th reference potential end VGL passes through conducting
T6 is transmitted to the 3rd node PD, and the current potential of the 3rd node PD is low potential, and the 7th switching transistor T7 ends.Due to CN=1,
Three switching transistor T3 are turned on, and the low-potential signal of the first clock signal terminal CK1 is passed by the 3rd switching transistor T3 of conducting
Section point PN is transported to, the current potential of section point PN is low potential, and the 5th switching transistor T5 ends.Due to CNB=0, the 4th
Switching transistor T4 ends.Since Reset=0, second switch transistor T2 end.
In the P2 stages, IN=0, Reset=0, CK1=0, CK2=0, CK3=1, CK4=0.
IN=0, first switch transistor cutoff, Reset=0, second switch transistor T2 cut-off.Therefore at first node
In Floating states, the current potential of first node PUCN remains high potential.9th switching transistor T91And T92Conducting, first
The current potential of control node PU1 and the second control node PU2 are still high potential, and the high potential signal of the 3rd clock signal terminal CK3 leads to
Cross the 8th switching transistor T8 of conducting1The first output terminal OUT1 is transmitted to, the current potential of the first output terminal OUT1 is changed into high potential,
Due to the 8th switching transistor T81Coupled capacitor boot strap, the current potential of the first control node PU1 is further pulled up,
So as to ensure the stability of output, as the current potential of the first control node PU1 is further pulled up, the 9th switching transistor T91
Gate source voltage be less than cut-in voltage, the 9th switching transistor T91Cut-off.The low-potential signal of 4th clock signal terminal CK4 leads to
Cross the 8th switching transistor T8 of conducting2The current potential for being transmitted to the second output terminal OUT2, the second output terminal OUT2 is low potential, the
The low-potential signal of four reference potential end VGL is transmitted to the 3rd node PD by the 6th switching transistor T6 of conducting, Section three
The current potential of point PD is low potential, and the 7th switching transistor T7 ends.Since CN=1, the 3rd switching transistor T3 are turned on, when first
The low-potential signal of clock signal end CK1 is transmitted to section point PN, section point PN by the 3rd switching transistor T3 of conducting
Current potential be low potential, the 5th switching transistor T5 cut-offs.Since CNB=0, the 4th switching transistor T4 end.
In the P3 stages, IN=0, Reset=0, CK1=0, CK2=0, CK3=0, CK4=1.
IN=0, first switch transistor cutoff, Reset=0, second switch transistor T2 cut-off.Therefore at first node
In Floating states, the current potential of first node PUCN remains high potential, the 6th switching transistor T6 conductings.9th switch is brilliant
Body pipe T91And T92Conducting, the current potential of the first control node PU1 and the second control node PU2 are still high potential, the 3rd clock signal
The 8th switching transistor T8 that the low-potential signal of end CK3 passes through conducting1It is transmitted to the first output terminal OUT1, the first output terminal
The current potential of OUT1 is changed into low potential, due to the 8th switching transistor T81Coupled capacitor boot strap, the first control node
The current potential of PU1 remains at high potential with reduction.The high potential signal of 4th clock signal terminal CK4 passes through conducting
8th switching transistor T82The second output terminal OUT2 is transmitted to, the current potential of the second output terminal OUT2 is changed into high potential, due to the 8th
Switching transistor T82Coupled capacitor boot strap, the current potential of the second control node PU2 is further pulled up, so as to ensure
The stability of output, as the current potential of the second control node PU2 is further pulled up, the 9th switching transistor T92Grid source electricity
Pressure is less than cut-in voltage, the 9th switching transistor T92Cut-off.The low-potential signal of 4th reference potential end VGL passes through conducting
6th switching transistor T6 is transmitted to the 3rd node PD, and the current potential of the 3rd node PD is low potential, and the 7th switching transistor T7 is cut
Only.Since CN=1, the 3rd switching transistor T3 are turned on, the low-potential signal of the first clock signal terminal CK1 pass through conducting the 3rd
Switching transistor T3 is transmitted to section point PN, and the current potential of section point PN is low potential, and the 5th switching transistor T5 ends.By
End in CNB=0, the 4th switching transistor T4.
In the P4 stages, IN=0, Reset=0, CK1=0, CK2=0, CK3=0, CK4=0.
IN=0, first switch transistor cutoff, Reset=0, second switch transistor T2 cut-off.First node is in
Floating states, the current potential of first node PUCN remain high potential.9th switching transistor T91And T92Conducting, the first control
The current potential of node PU1 processed and the second control node PU2 are still high potential, and the low-potential signal of the 3rd clock signal terminal CK3 passes through
8th switching transistor T8 of conducting1The first output terminal OUT1 is transmitted to, the current potential of the first output terminal OUT1 is changed into low potential, the
The 8th switching transistor T8 that the low-potential signal of four clock signal terminal CK4 passes through conducting2The second output terminal OUT2 is transmitted to, the
The current potential of two output terminal OUT2 is changed into low potential, due to the 8th switching transistor T82Coupled capacitor boot strap, second control
The current potential of node PU2 processed remains at high potential with reduction.The low-potential signal of 4th reference potential end VGL passes through
6th switching transistor T6 of conducting is transmitted to the 3rd node PD, and the current potential of the 3rd node PD is low potential, and the 7th switchs crystal
Pipe T7 ends.Since CN=1, the 3rd switching transistor T3 are turned on, the low-potential signal of the first clock signal terminal CK1 passes through conducting
The 3rd switching transistor T3 be transmitted to section point PN, the current potential of section point PN is low potential, the 5th switching transistor T5
Cut-off.Since CNB=0, the 4th switching transistor T4 end.
In the P5 stages, IN=0, Reset=1, CK1=1, CK2=0, CK3=0, CK4=0.
IN=0, first switch transistor cutoff, Reset=1, second switch transistor T2 conducting.Second reference potential end
The low-potential signal of CNB is transmitted to first node PUCN, the electricity of first node PUCN by the second switch transistor T2 of conducting
Position is changed into low potential, and the 6th switching transistor T6 cut-offs, pass through the 9th switching transistor T9 of conducting1And T92, the first control section
The current potential of point PU1 and the second control node PU2 are changed into low potential, the 8th switching transistor T81And T82Cut-off.Due to CN=1,
Three switching transistor T3 are turned on, and the high potential signal of the first clock signal terminal CK1 is passed by the 3rd switching transistor T3 of conducting
Section point PN is transported to, the current potential of section point PN is changed into high potential, the 5th switching transistor T5 conductings.3rd reference potential end
The high potential signal of VGH is transmitted to the 3rd node PD by the 5th switching transistor T5 of conducting, and the current potential of the 3rd node PD becomes
For high potential, the 7th switching transistor T7 conductings, the low-potential signal of the 4th reference potential end VGL passes through the 7th of conducting and switchs
Transistor T7 is transmitted to first node PUCN, and the current potential for being further ensured that first node PUCN is low potential.Due to CNB=0,
Four switching transistor T4 end.
In the P6 stages, IN=0, Reset=0, CK1=0, CK2=1, CK3=0, CK4=0.
IN=0, first switch transistor cutoff, Reset=1, second switch transistor T2 cut-off.First node is in
Floating states, the current potential of first node PUCN remain low potential, the 6th switching transistor T6 cut-offs.Pass through the of conducting
Nine switching transistor T91And T92, the current potential of the first control node PU1 and the second control node PU2 is still low potential, the 8th switch
Transistor T81And T82Cut-off.Since CN=1, the 3rd switching transistor T3 are turned on, the low potential letter of the first clock signal terminal CK1
Number section point PN being transmitted to by the 3rd switching transistor T3 of conducting, the current potential of section point PN is changed into low potential, and the 5th
Switching transistor T5 ends.3rd node is in Floating states, and the current potential of the 3rd node PD keeps high potential, the 7th switch
Transistor T7 is turned on, and the low-potential signal of the 4th reference potential end VGL is transmitted to the by the 7th switching transistor T7 of conducting
One node PUCN, the current potential for being further ensured that first node PUCN are low potential.Due to CNB=0, the 4th switching transistor T4 is cut
Only.
Afterwards until next frame starts, first node PUCN is always maintained at low potential, and the 3rd node PD is always maintained at height
Current potential, when section point PN every CK1=1, are changed into charging once, with to the 3rd node PD chargings once.
Example two,
By taking the shifting deposit unit shown in Fig. 5 as an example, wherein CN=1, CNB=0, VGH=1, VGL=0, corresponding sequential
Figure is as shown in 13 figures.
In the PI stages, IN=1, Reset=0, CK1=0, CK2=0, CK3=0, CK4=0.
Tenth switching transistor T101And T102Cut-off, the working status of other switching transistors and the P1 stages of example one
Identical, therefore not to repeat here.
In the P2 stages, IN=0, Reset=0, CK1=0, CK2=0, CK3=1, CK4=0.
Tenth switching transistor T101And T102Cut-off, the working status of other switching transistors and the P2 stages of example one
Identical, therefore not to repeat here.
In the P3 stages, IN=0, Reset=0, CK1=0, CK2=0, CK3=0, CK4=1.
Tenth switching transistor T101And T102Cut-off, the working status of other switching transistors and the P3 stages of example one
Identical, therefore not to repeat here.
In the P4 stages, IN=0, Reset=0, CK1=0, CK2=0, CK3=0, CK4=0.
Tenth switching transistor T101And T102Cut-off, the working status of other switching transistors and the P4 stages of example one
Identical, therefore not to repeat here.
In the P5 stages, IN=0, Reset=1, CK1=1, CK2=0, CK3=0, CK4=0.
Tenth switching transistor T101And T102Conducting, the low-potential signal of the 4th reference potential end VGL pass through conducting respectively
The tenth switching transistor T101And T102The first output terminal OUT1 and the second output terminal OUT2 are transmitted to, is the first output terminal
OUT1 and the second output terminal OUT2 electric discharges.The working status of other switching transistors is identical with the P5 stages of example one, herein not
Repeat.
In the P6 stages, IN=0, Reset=0, CK1=0, CK2=1, CK3=0, CK4=0.
Tenth switching transistor T101And T102Conducting, the low-potential signal of the 4th reference potential end VGL pass through conducting respectively
The tenth switching transistor T101And T102The first output terminal OUT1 and the second output terminal OUT2 are transmitted to, is the first output terminal
OUT1 and the second output terminal OUT2 electric discharges.The working status of other switching transistors is identical with the P5 stages of example one, herein not
Repeat.
Afterwards until next frame starts, first node PUCN is always maintained at low potential, and the 3rd node PD is always maintained at height
Current potential, when section point PN every CK1=1, are changed into charging once, with to the 3rd node PD chargings once, the tenth switching transistor
T101And T102Conducting, the low-potential signal of the 4th reference potential end VGL pass through the tenth switching transistor T10 of conducting respectively1With
T102The first output terminal OUT1 and the second output terminal OUT2 are transmitted to, is put for the first output terminal OUT1 and the second output terminal OUT2
Electricity.The working status of other switching transistors is identical with example one, and therefore not to repeat here.
Example three,
Gate driving circuit shown in Figure 11 is applied to shifting deposit unit, and with the shifting deposit unit shown in Fig. 5
Exemplified by, corresponding sequential is as shown in figure 14.
In the PI stages, IN=1, Reset=0, CK1=0, CK2=0, CK3=0, CK4=0.
Working status is identical with the P1 stages of example two, and therefore not to repeat here.
In the P2 stages, IN=0, Reset=0, CK1=0, CK2=0, CK3=1, CK4=0.
Working status is identical with the P2 stages of example two, and therefore not to repeat here.
In the P3 stages, IN=0, Reset=0, CK1=0, CK2=0, CK3=0, CK4=1.
Working status is identical with the P3 stages of example two, and therefore not to repeat here.
In the P4 stages, IN=0, Reset=1, CK1=1, CK2=0, CK3=0, CK4=0.
Working status is identical with the P5 stages of example two, and therefore not to repeat here.
In the P5 stages, IN=0, Reset=0, CK1=0, CK2=1, CK3=0, CK4=0.
Working status is identical with the P6 stages of example two, and therefore not to repeat here.
Afterwards until next frame starts, first node PUCN is always maintained at low potential, and the 3rd node PD is always maintained at height
Current potential, when section point PN every CK1=1, are changed into charging once, with to the 3rd node PD chargings once.
Further, the shifting deposit unit for including discharge module provided for the utility model embodiment, such as
Shifting deposit unit shown in Fig. 6, as soon as after frame end is scanned, the current potential of the 4th reference potential end VGL is changed into high potential, makes
Can control terminal EN control the 11st switching transistor T11 conductings, the 11st switching transistor T11 of conducting is by the 4th reference potential
The high potential signal of end VGL is transmitted to the 3rd node PD, the tenth switching transistor T10 of the 3rd node PD control1And T102Conducting,
The high potential signal of 4th reference potential end VGL passes through the tenth switching transistor T10 of conducting respectively1And T102It is transmitted to first
Output terminal OUT1 and the second output terminal OUT2, so as to discharge display panel.
It should be noted that the utility model embodiment be with include the shifting deposit unit of two output modules into
Illustrate exemplified by row forward scan, when corresponding to reverse scan, the sequential of the clock signal of clock signal terminal is done accordingly
Change, operation principle is identical, and therefore not to repeat here.
Conceived based on same utility model, the utility model embodiment additionally provides a kind of drive of above-mentioned shifting deposit unit
Dynamic method, since the principle that the driving method solves the problems, such as is similar to a kind of foregoing shifting deposit unit, the driving method
Implementation may refer to the implementation of aforementioned shift deposit unit, overlaps will not be repeated.
Specifically, in the driving method that the utility model embodiment provides, including：
The signal at the first reference potential end is supplied to by input phase, the first input module under the control at input signal end
First node；The signal at the 4th reference potential end is supplied to Section three by the 3rd node control module under the control of first node
Point；
The signal of n-th+2 clock signal terminal is supplied to by output stage, n-th of output module under the control of first node
N-th of output terminal；
The signal at the second reference potential end is supplied to by reseting stage, the second input module under the control at reset signal end
First node；The signal of first clock signal terminal is supplied to by section point control module under the control at the first reference potential end
Section point, or the signal of second clock signal end is supplied to section point under the control at the second reference potential end；3rd
The signal at the 3rd reference potential end is supplied to the 3rd node, first node control by node control module under the control of section point
The signal at the 4th reference potential end is supplied to first node by molding block under the control of the 3rd node.
Specifically, the above-mentioned driving method that the utility model embodiment provides may refer to examples detailed above one to example three,
Do not repeating herein.
Conceived based on same utility model, the utility model embodiment additionally provides a kind of display device, including this practicality
Any of the above-described kind of gate driving circuit that new embodiment provides.The display device can be mobile phone, naturally it is also possible to be tablet
Any product or component with display function such as computer, television set, display, laptop, Digital Frame, navigator.
The implementation of the display device may refer to the embodiment of above-mentioned gate driving circuit, and overlaps will not be repeated.
Above-mentioned shifting deposit unit, gate driving circuit and the display device that the utility model embodiment provides, wherein moving
Position deposit unit includes：First input module, the second input module, first node control module, section point control module,
Three node control modules and N number of output module, wherein N are the integer more than 1；Wherein, the first input module is used for according to input
Signal end is controlled first node；Second input module is used to be controlled first node according to reset signal end；The
One node control module is used to be controlled first node according to the 3rd node；Section point control module is used for according to first
Clock signal terminal and second clock signal end are controlled section point, so that the 3rd node control module is according to section point
The 3rd node is controlled with first node, and N number of output module is respectively used under the control of first node according to correspondence
Clock signal terminal corresponding output terminal is controlled.The shifting deposit unit that the utility model embodiment provides passes through multiple
Output module controls multiple output terminals, therefore a shifting deposit unit can connect a plurality of grid line, when the shifting deposit unit
During applied to display panel, it is possible to reduce the quantity of shifting deposit unit, is conducive to narrow frame design.
Obviously, those skilled in the art can carry out the utility model various modification and variations without departing from this practicality
New spirit and scope.If in this way, these modifications and variations of the utility model belong to the utility model claims and
Within the scope of its equivalent technologies, then the utility model is also intended to comprising including these modification and variations.
Claims (15)
1. a kind of shifting deposit unit, it is characterised in that including the first input module, the second input module, first node control
Module, section point control module, the 3rd node control module and N number of output module, wherein N are the integer more than 1；
First input module, for the signal at the first reference potential end to be supplied to first under the control at input signal end
Node；
Second input module, it is described for being supplied to the signal at the second reference potential end under the control at reset signal end
First node；
The first node control module, for the signal at the 4th reference potential end to be supplied to institute under the control of the 3rd node
State first node；
The section point control module, under the control at the first reference potential end by the letter of the first clock signal terminal
Number section point is supplied to, be supplied to the signal of second clock signal end under the control at the second reference potential end described
Section point；
3rd node control module, for providing the signal at the 3rd reference potential end under the control of the section point
To the 3rd node, the signal at the 4th reference potential end is supplied to described Section three under the control of the first node
Point；
In N number of output module, n-th of output module is used for the n-th+2 clock under the control of the first node
The signal of signal end is supplied to n-th of output terminal, and n takes any integer more than 0 and less than or equal to N.
2. shifting deposit unit as claimed in claim 1, it is characterised in that first input module includes：First switch
Transistor, second input module include：Second switch transistor；
The grid of the first switch transistor is connected with the input signal end, the first pole of the first switch transistor with
The first reference potential end connection, the second pole of the first switch transistor is connected with the first node；
The grid of the second switch transistor is connected with the reset signal end, the first pole of the second switch transistor with
The second reference potential end connection, the second pole of the second switch transistor is connected with the first node.
3. shifting deposit unit as claimed in claim 1, it is characterised in that the section point control module includes：3rd
Switching transistor and the 4th switching transistor；
The grid of 3rd switching transistor is connected with the first reference potential end, and the first of the 3rd switching transistor
Pole is connected with first clock signal terminal, and the second pole of the 3rd switching transistor is connected with the section point；
The grid of 4th switching transistor is connected with the second reference potential end, and the first of the 4th switching transistor
Pole is connected with the second clock signal end, and the second pole of the 4th switching transistor is connected with the section point.
4. shifting deposit unit as claimed in claim 1, it is characterised in that the 3rd node control module includes：5th
Switching transistor and the 6th switching transistor；
The grid of 5th switching transistor is connected with the section point, the first pole of the 5th switching transistor and institute
The connection of the 3rd reference potential end is stated, the second pole of the 5th switching transistor is connected with the 3rd node；
The grid of 6th switching transistor is connected with the first node, the first pole of the 6th switching transistor and institute
The connection of the 4th reference potential end is stated, the second pole of the 6th switching transistor is connected with the 3rd node.
5. shifting deposit unit as claimed in claim 1, it is characterised in that the first node control module includes：7th
Switching transistor；
The grid of 7th switching transistor is connected with the 3rd node, the first pole of the 7th switching transistor and institute
The connection of the 4th reference potential end is stated, the second pole of the 7th switching transistor is connected with the first node.
6. shifting deposit unit as claimed in claim 1, it is characterised in that the shifting deposit unit further includes：Current potential is protected
Module is held, wherein the current potential keeps module to include：First capacitance and the second capacitance；
First capacitance connection is between the first node and the 4th reference potential end；
Second capacitance connection is between the 3rd node and the 4th reference potential end.
7. shifting deposit unit as claimed in claim 1, it is characterised in that each output module includes：One the 8th
Switching transistor；
In n-th of output module, the grid of the 8th switching transistor is connected with the first node, and the described 8th opens
The first pole for closing transistor is connected with n-th+2 clock signal terminal, the second pole and described n-th of the 8th switching transistor
A output terminal connection.
8. shifting deposit unit as claimed in claim 7, it is characterised in that each output module further includes：One
Nine switching transistors；
The grid of 9th switching transistor is connected by the 9th switching transistor with the first node, and described
The grid of nine switching transistors is connected with the 3rd reference potential end.
9. such as claim 1-8 any one of them shifting deposit units, it is characterised in that the shifting deposit unit also wraps
Include：Reseting module is exported correspondingly with each output terminal；
The output reseting module corresponding with n-th of output terminal is used for the described 4th ginseng under the control of the 3rd node
The signal for examining potential end is supplied to n-th of output terminal.
10. shifting deposit unit as claimed in claim 9, it is characterised in that the output reseting module includes：Tenth switch
Transistor；
The grid of tenth switching transistor is connected with the 3rd node, the first pole of the tenth switching transistor and institute
State the connection of the 4th reference potential end；
In the output reseting module corresponding with n-th of output terminal, the second pole and described n-th of the tenth switching transistor
A output terminal connection.
11. shifting deposit unit as claimed in claim 9, it is characterised in that the shifting deposit unit further includes：Discharge mould
Block；
The discharge module is used under the control of enabled control terminal the signal at the 4th reference potential end being supplied to described
3rd node.
12. shifting deposit unit as claimed in claim 11, it is characterised in that the discharge module includes：11st switch
Transistor；
The grid of 11st switching transistor is connected with the enabled control terminal, and the first of the 11st switching transistor
Pole is connected with the 4th reference potential end, and the second pole of the 11st switching transistor is connected with the section point.
13. a kind of gate driving circuit, it is characterised in that be made of including at least one the multiple shifting deposit units cascaded
Cascade circuit, wherein the shifting deposit unit is such as claim 1-12 any one of them shifting deposit units；
In the cascade circuit, in addition to afterbody shifting deposit unit, the n-th output per level-one shifting deposit unit
End is connected with the input signal end of next stage shifting deposit unit；
In addition to first order shifting deposit unit, first output terminal and upper level shift LD per level-one shifting deposit unit
The reset signal end of unit is connected.
14. gate driving circuit as claimed in claim 13, it is characterised in that including two cascade circuits, and it is described
Shifting deposit unit includes two output modules；
In first cascade circuit：The first clock signal terminal and even level shifting deposit unit of odd level shifting deposit unit
The 3rd clock signal terminal be connected with the 5th clock cable；The second clock signal end and idol of odd level shifting deposit unit
4th clock signal terminal of several levels shifting deposit unit is connected with the 6th clock cable；The of odd level shifting deposit unit
First clock signal terminal of three clock signal terminals and even level shifting deposit unit is connected with the first clock cable；Odd level
4th clock signal terminal of shifting deposit unit and the second clock signal end of even level shifting deposit unit are and second clock
Signal wire connects；
In second cascade circuit：The first clock signal terminal and even level shifting deposit unit of odd level shifting deposit unit
The 3rd clock signal terminal be connected with the 7th clock cable；The second clock signal end and idol of odd level shifting deposit unit
4th clock signal terminal of several levels shifting deposit unit is connected with the 8th clock cable；The of odd level shifting deposit unit
First clock signal terminal of three clock signal terminals and even level shifting deposit unit is connected with the 3rd clock cable；Odd level
4th clock signal terminal of shifting deposit unit and the second clock signal end of even level shifting deposit unit with the 4th clock
Signal wire connects；
Wherein, the clock signal that the first clock cable is exported to the 8th clock cable differed for 1/8 clock cycle successively.
15. a kind of display device, it is characterised in that including gate driving circuit as claimed in claim 14.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721411630.3U CN207302594U (en) | 2017-10-27 | 2017-10-27 | Shifting deposit unit, gate driving circuit and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721411630.3U CN207302594U (en) | 2017-10-27 | 2017-10-27 | Shifting deposit unit, gate driving circuit and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207302594U true CN207302594U (en) | 2018-05-01 |
Family
ID=62274832
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721411630.3U Withdrawn - After Issue CN207302594U (en) | 2017-10-27 | 2017-10-27 | Shifting deposit unit, gate driving circuit and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207302594U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107633834A (en) * | 2017-10-27 | 2018-01-26 | 京东方科技集团股份有限公司 | Shifting deposit unit, its driving method, gate driving circuit and display device |
| CN112037727A (en) * | 2020-09-14 | 2020-12-04 | 京东方科技集团股份有限公司 | Shift register unit and gate drive circuit |
-
2017
- 2017-10-27 CN CN201721411630.3U patent/CN207302594U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107633834A (en) * | 2017-10-27 | 2018-01-26 | 京东方科技集团股份有限公司 | Shifting deposit unit, its driving method, gate driving circuit and display device |
| US11282470B2 (en) | 2017-10-27 | 2022-03-22 | Ordos Yuansheng Optoelectronics Co., Ltd. | Shift register element, method for driving the same, gate driver circuit, and display device |
| CN112037727A (en) * | 2020-09-14 | 2020-12-04 | 京东方科技集团股份有限公司 | Shift register unit and gate drive circuit |
| CN112037727B (en) * | 2020-09-14 | 2022-01-11 | 京东方科技集团股份有限公司 | Shift register unit and gate drive circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107633834A (en) | Shifting deposit unit, its driving method, gate driving circuit and display device | |
| CN106057147B (en) | Shift register cell and its driving method, gate driving circuit, display device | |
| CN106157912B (en) | Shift register cell, its driving method, gate driving circuit and display device | |
| CN105788555B (en) | Shift register cell and its driving method, gate driving circuit, display device | |
| CN105529009B (en) | Shift register and its driving method, gate driving circuit and display device | |
| CN105096902B (en) | A kind of shift register, its driving method, gate driving circuit and display device | |
| CN104299590B (en) | A kind of shift register, its driving method, gate driver circuit and display device | |
| CN105741744B (en) | A kind of shift register cell, gate driving circuit and display device | |
| CN106098101B (en) | A kind of shift register, gate driving circuit and display device | |
| CN106887216B (en) | The driving method of gate driving circuit, display panel and gate driving circuit | |
| CN105632562B (en) | A kind of shift register, gate driving circuit, display panel and display device | |
| CN104575411B (en) | Liquid crystal display and its bi-directional shift apparatus for temporary storage | |
| CN110111831A (en) | Shift register, gate driving circuit and display device | |
| CN107093414B (en) | A kind of shift register, its driving method, gate driving circuit and display device | |
| CN205984242U (en) | Shifting register unit, gate driving circuit and display device | |
| CN107507556A (en) | Shift register cell and driving method, gate driving circuit and display device | |
| CN108231034A (en) | Shift register cell, gate driving circuit, display panel and display device | |
| CN105632563B (en) | A kind of shift register, gate driving circuit and display device | |
| CN104952406B (en) | Shift register and its driving method, gate driving circuit and display device | |
| CN105551422B (en) | A kind of shift register, gate driving circuit and display panel | |
| CN108573673A (en) | Shift register, driving circuit, display device | |
| CN108122529A (en) | Drive element of the grid and its driving method and gate driving circuit | |
| CN106782399A (en) | A kind of shift register, its driving method, gate driving circuit and display device | |
| CN108877632A (en) | A kind of gate driving circuit, array substrate, display panel and display device | |
| CN106910452B (en) | Shift register cell, its driving method, gate driving circuit and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20180501 Effective date of abandoning: 20200331 |