CN112037727A - Shift register unit and gate drive circuit - Google Patents
Shift register unit and gate drive circuit Download PDFInfo
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- CN112037727A CN112037727A CN202010960335.3A CN202010960335A CN112037727A CN 112037727 A CN112037727 A CN 112037727A CN 202010960335 A CN202010960335 A CN 202010960335A CN 112037727 A CN112037727 A CN 112037727A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Crystallography & Structural Chemistry (AREA)
- Liquid Crystal Display Device Control (AREA)
- Shift Register Type Memory (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a shift register unit and a grid drive circuit, comprising: the device comprises a forward input module, a reverse input module, a forward control module, a reverse control module, an output module, a node control module and an adjusting module; the forward control module and the reverse control module are respectively used for controlling the second node, so that the regulating module enables the third switching transistor in the node control module to be connected with the third node under the control of the second node, thereby ensuring that the forward control module controls the second node when the forward input module provides a signal to the first node, and enabling the regulating module to disconnect the third switching transistor and the third node in the node control module under the control of the second node, so as to avoid forming a direct current path in the shift registering unit, reduce the power consumption of the shift registering unit, effectively improve the competitive relationship between the first switching transistor and the second switching transistor, and improve the reliability of the panel.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a shift register unit and a gate driving circuit.
Background
In the modern times of the growing technology, liquid crystal displays have been widely used in electronic display products, such as televisions, computers, mobile phones, and personal digital assistants. The lcd includes a data Driver (Source Driver), a Gate Driver (Gate Driver), and an lcd panel. The liquid crystal display panel is provided with a pixel array, and the grid driving device is used for sequentially opening corresponding pixel rows in the pixel array so as to transmit pixel data output by the data driver to the pixels and further display an image to be displayed.
At present, a Gate driving device is generally formed on an Array substrate of a liquid crystal display by an Array process, that is, a Gate Driver on Array (GOA) process of the Array substrate, and this integration process not only saves cost, but also can achieve a symmetric aesthetic design on both sides of a liquid crystal Panel (Panel), and simultaneously, a Bonding area of a Gate Integrated Circuit (IC) and a wiring space of a Fan-out (Fan-out) are also saved, thereby realizing a design of a narrow frame; moreover, the integration process can also omit the Bonding process in the direction of a grid scanning line, thereby improving the productivity and the yield.
The conventional gate driving apparatus is generally composed of a plurality of cascaded shift register units. The conventional shift register unit includes 9 switching transistors M1 to M9, as shown in fig. 1. As shown in fig. 2, when M1 turns on and pulls up the PU node of the shift register unit, CKB turns on M4 of the shift register unit, charges the PD node of the shift register unit, turns on both M3 and M5 of the shift register unit, and forms a contention relationship between M3 and M5, thereby forming a dc path between M3 and M5, and increasing the power consumption of the shift register unit. Meanwhile, the switching transistor of the shift register unit is damaged by impact, and the reliability of the display panel is reduced.
Disclosure of Invention
The embodiment of the invention provides a shift register unit and a gate drive circuit, which are used for solving the problem that a direct current path exists in the shift register unit in the prior art.
An embodiment of the present invention provides a shift register unit, including: the device comprises a forward input module, a reverse input module, a forward control module, a reverse control module, an output module, a node control module and an adjusting module;
the forward input module is used for providing a signal of a first reference signal end to a first node under the control of an input signal end;
the inverting input module is used for providing a signal of a second reference signal terminal to the first node under the control of a reset signal terminal;
the forward control module is used for providing a signal of a first clock signal end to a second node under the control of the first reference signal end;
the reverse control module is used for providing a signal of a second clock signal end to the second node under the control of the second reference signal end;
the node control module comprises a first switch transistor, a second switch transistor, a third switch transistor and a fourth switch transistor; the first switch transistor is used for conducting a first reference voltage source and the first node under the control of a third node, the second switch transistor is used for conducting the first reference voltage source and the third node under the control of the first node, the third switch transistor is used for conducting a third clock signal end and the adjusting module under the control of a third clock signal end, and the fourth switch transistor is used for conducting the first reference voltage source and the third node under the control of a signal output end;
the adjusting module is used for enabling the third switching transistor to be conducted with the third node under the control of the second node;
the output module is configured to provide a signal of a fourth clock signal terminal to the signal output terminal under the control of the first node, or provide a signal of the first reference voltage source to the signal output terminal under the control of the third node.
In a possible implementation manner, in the shift register unit provided in an embodiment of the present invention, the forward input module includes a sixth switching transistor; wherein:
a gate of the sixth switching transistor is connected to the input signal terminal, a first pole of the sixth switching transistor is connected to the first reference signal terminal, and a second pole of the sixth switching transistor is connected to the first node.
In a possible implementation manner, in the shift register unit provided in the embodiment of the present invention, the inverting input module includes a seventh switching transistor; wherein:
a gate of the seventh switching transistor is connected to the reset signal terminal, a first pole of the seventh switching transistor is connected to the second reference signal terminal, and a second pole of the seventh switching transistor is connected to the first node.
In a possible implementation manner, in the shift register unit provided in the embodiment of the present invention, the forward control module includes an eighth switching transistor; wherein:
a gate of the eighth switching transistor is connected to the first reference signal terminal, a first pole of the eighth switching transistor is connected to the first clock signal terminal, and a second pole of the eighth switching transistor is connected to the second node.
In a possible implementation manner, in the shift register unit provided in the embodiment of the present invention, the inversion control module includes a ninth switching transistor; wherein:
the gate of the ninth switching transistor is connected to the second reference signal terminal, the first pole of the ninth switching transistor is connected to the second clock signal terminal, and the second pole of the ninth switching transistor is connected to the second node.
In a possible implementation manner, in the shift register unit provided in the embodiment of the present invention, the adjusting module includes a tenth switching transistor; wherein:
a gate of the tenth switching transistor is connected to the second node, a first pole of the tenth switching transistor is connected to the third switching transistor, and a second pole of the tenth switching transistor is connected to the third node.
In a possible implementation manner, in the shift register unit provided in this embodiment of the present invention, the output module includes an eleventh switching transistor, a twelfth switching transistor, a first capacitor, and a second capacitor; wherein:
a gate of the eleventh switching transistor is connected to the first node, a first pole of the eleventh switching transistor is connected to the fourth clock signal terminal, and a second pole of the eleventh switching transistor is connected to the signal output terminal;
a gate of the twelfth switching transistor is connected to the third node, a first pole of the twelfth switching transistor is connected to the first reference voltage source, and a second pole of the twelfth switching transistor is connected to the signal output terminal;
the first capacitor is connected between the grid electrode of the eleventh switching transistor and the signal output end;
the second capacitor is connected between the third node and the first reference voltage source.
In a possible implementation manner, in the shift register unit provided in an embodiment of the present invention, the shift register unit further includes: a fifth switching transistor connected between the first node and a gate of the eleventh switching transistor; wherein the content of the first and second substances,
a gate of the fifth switching transistor is connected to a second reference voltage source, a first pole of the fifth switching transistor is connected to the first node, and a second pole of the fifth switching transistor is connected to a gate of the eleventh switching transistor.
In a possible implementation manner, in the shift register unit provided in the embodiment of the present invention, a thirteenth switching transistor is further included; wherein:
the gate of the thirteenth switching transistor is connected to the reset control terminal, the first pole of the thirteenth switching transistor is connected to a third reference voltage source, and the second pole of the thirteenth switching transistor is connected to the first node.
In a possible implementation manner, in the shift register unit provided in the embodiment of the present invention, a fourteenth switching transistor is further included; wherein:
a gate of the fourteenth switching transistor is connected to the touch control terminal, a first pole of the fourteenth switching transistor is connected to the first reference voltage source, and a second pole of the fourteenth switching transistor is connected to the signal output terminal.
Correspondingly, the embodiment of the invention also provides a gate drive circuit, which comprises a plurality of cascaded shift register units provided by the embodiment of the invention; wherein the content of the first and second substances,
except the first stage of shift register unit, the signal output end of each stage of shift register unit is respectively connected with the reset signal end of the adjacent previous stage of shift register unit;
except the last stage of shift register unit, the signal output end of each stage of shift register unit is respectively connected with the input signal end of the next stage of shift register unit. In one possible implementation mode, the beneficial effects of the invention are as follows:
the shift register unit and the gate driving circuit provided by the embodiment of the invention comprise: the device comprises a forward input module, a reverse input module, a forward control module, a reverse control module, an output module, a node control module and an adjusting module; the forward control module and the reverse control module are respectively used for controlling the second node, so that the regulating module enables the third switching transistor in the node control module to be connected with the third node under the control of the second node, thereby ensuring that the forward control module controls the second node when the forward input module provides a signal to the first node, and enabling the regulating module to disconnect the third switching transistor and the third node in the node control module under the control of the second node, so as to avoid forming a direct current path in the shift registering unit, reduce the power consumption of the shift registering unit, effectively improve the competitive relationship between the first switching transistor and the second switching transistor, and improve the reliability of the panel.
Drawings
FIG. 1 is a schematic diagram of a conventional gate driving circuit;
FIG. 2 is a timing diagram of signals corresponding to a conventional gate driving circuit;
FIG. 3 is a diagram illustrating a shift register unit according to an embodiment of the present invention;
FIG. 4 is a second schematic diagram of a shift register unit according to an embodiment of the present invention;
FIG. 5 is a third schematic diagram illustrating a shift register unit according to an embodiment of the present invention;
FIG. 6 is a fourth schematic diagram illustrating a shift register unit according to an embodiment of the present invention;
FIG. 7 is a timing diagram of a shift register unit according to an embodiment of the present invention;
FIG. 8 is a second timing diagram corresponding to the shift register unit according to the embodiment of the present invention;
fig. 9 is a schematic structural diagram of a gate driving circuit according to an embodiment of the invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, the present invention is further described with reference to the accompanying drawings and examples. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their repetitive description will be omitted. The words expressing the position and direction described in the present invention are illustrated in the accompanying drawings, but may be changed as required and still be within the scope of the present invention. The drawings of the present invention are for illustrative purposes only and do not represent true scale.
It should be noted that in the following description, specific details are set forth in order to provide a thorough understanding of the present invention. The invention can be implemented in a number of ways different from those described herein and similar generalizations can be made by those skilled in the art without departing from the spirit of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed below. The description which follows is a preferred embodiment of the present application, but is made for the purpose of illustrating the general principles of the application and not for the purpose of limiting the scope of the application. The protection scope of the present application shall be subject to the definitions of the appended claims.
The shift register unit and the gate driving circuit according to the embodiment of the invention are specifically described below with reference to the accompanying drawings.
An embodiment of the present invention provides a shift register unit, as shown in fig. 3, including: the system comprises a forward input module 01, a reverse input module 02, a forward control module 03, a reverse control module 04, an output module 05, a node control module 06 and an adjusting module 07; the forward input module 01 is configured to provide a signal of the first reference signal terminal CN to the first node PU under the control of the input signal terminal IN; the inverting input module 02 is configured to provide a signal of the second reference signal terminal CNB to the first node PU under the control of the reset signal terminal RES; the forward control module 03 is configured to provide a signal of the first clock signal terminal CS to the second node P under the control of the first reference signal terminal CN; the reverse control module 04 is configured to provide a signal of the second clock signal terminal CSB to the second node P under the control of the second reference signal terminal CNB; the node control module 06 includes a first switching transistor T1, a second switching transistor T2, a third switching transistor T3, and a fourth switching transistor T4; the first switch transistor T1 is used for turning on the first reference voltage source VG1 and the first node PU under the control of the third node PD, the second switch transistor T2 is used for turning on the first reference voltage source VG1 and the third node PD under the control of the first node PU, the third switch transistor T3 is used for turning on the third clock signal terminal CKB and the adjusting module 07 under the control of the third clock signal terminal CKB, and the fourth switch transistor T4 is used for turning on the first reference voltage source VG1 and the third node PD under the control of the signal output terminal OUT; the adjusting module 07 is configured to turn on the third switching transistor T3 and the third node PD under the control of the second node P; the output module 05 is used for providing the signal of the fourth clock signal terminal CK to the signal output terminal OUT under the control of the first node PU or providing the signal of the first reference voltage source VG1 to the signal output terminal OUT under the control of the third node PD.
The shift register unit provided by the embodiment of the invention comprises: the device comprises a forward input module, a reverse input module, a forward control module, a reverse control module, an output module, a node control module and an adjusting module; the forward control module and the reverse control module are respectively used for controlling the second node, so that the regulating module enables the third switching transistor in the node control module to be connected with the third node under the control of the second node, thereby ensuring that the forward control module controls the second node when the forward input module provides a signal to the first node, and enabling the regulating module to disconnect the third switching transistor and the third node in the node control module under the control of the second node, so as to avoid forming a direct current path in the shift registering unit, reduce the power consumption of the shift registering unit, effectively improve the competitive relationship between the first switching transistor and the second switching transistor, and improve the reliability of the panel.
The present invention will be described in detail with reference to specific examples. It should be noted that the present embodiment is for better explaining the present invention, but not limiting the present invention.
Alternatively, in the shift register unit provided in the embodiment of the present invention, as shown in fig. 4 and 5, the positive input module 01 includes a sixth switching transistor T6; wherein: a gate of the sixth switching transistor T6 is connected to the input signal terminal IN, a first pole of the sixth switching transistor T6 is connected to the first reference signal terminal CN, and a second pole of the sixth switching transistor T6 is connected to the first node PU.
Alternatively, in the shift register unit provided in the embodiment of the present invention, as shown in fig. 4 and 5, the inverting input module 02 includes a seventh switching transistor T7; wherein: a gate of the seventh switching transistor T7 is connected to the reset signal terminal RES, a first pole of the seventh switching transistor T7 is connected to the second reference signal terminal CNB, and a second pole of the seventh switching transistor T7 is connected to the first node PU.
Alternatively, in the shift register unit provided in the embodiment of the present invention, as shown in fig. 4 and 5, the forward control module 03 includes an eighth switching transistor T8; wherein: a gate of the eighth switching transistor T8 is connected to the first reference signal terminal CN, a first pole of the eighth switching transistor T8 is connected to the first clock signal terminal CS, and a second pole of the eighth switching transistor T8 is connected to the second node P.
Alternatively, in the shift register unit provided in the embodiment of the present invention, as shown in fig. 4 and 5, the inversion control module 04 includes a ninth switching transistor T9; wherein: a gate of the ninth switching transistor T9 is connected to the second reference signal terminal CNB, a first pole of the ninth switching transistor T9 is connected to the second clock signal terminal CSB, and a second pole of the ninth switching transistor T9 is connected to the second node P.
Alternatively, in the shift register unit provided in the embodiment of the present invention, as shown in fig. 4 and 5, the adjusting module 07 includes a tenth switching transistor T10; wherein a gate of the tenth switching transistor T10 is connected to the second node P, a first pole of the tenth switching transistor T10 is connected to the third switching transistor T3, and a second pole of the tenth switching transistor T10 is connected to the third node PD.
Alternatively, in the shift register unit provided in the embodiment of the present invention, as shown in fig. 4 and 5, the output module 05 includes an eleventh switching transistor T11, a twelfth switching transistor T12, a first capacitor C1, and a second capacitor C2; wherein a gate of the eleventh switching transistor T11 is connected to the first node PU, a first pole of the eleventh switching transistor T11 is connected to the fourth clock signal terminal CK, and a second pole of the eleventh switching transistor T11 is connected to the signal output terminal OUT; a gate of the twelfth switching transistor T12 is connected to the third node PD, a first pole of the twelfth switching transistor T12 is connected to the first reference voltage source VG1, and a second pole of the twelfth switching transistor T12 is connected to the signal output terminal OUT; the first capacitor C1 is connected between the gate of the eleventh switching transistor T11 and the signal output terminal OUT; the second capacitor C2 is connected between the third node PD and the first reference voltage source VG 1.
The above is merely an example of the specific structure of each module in the shift register unit, and in the specific implementation, the specific structure of each module is not limited to the above structure provided by the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
Optionally, in the shift register unit provided in the embodiment of the present invention, as shown in fig. 5, the shift register unit further includes: a fifth switching transistor T5 connected between the first node PU and the gate of the eleventh switching transistor T11; a gate of the fifth switching transistor T5 is connected to the second reference voltage source VG2, a first pole of the fifth switching transistor T5 is connected to the first node PU, and a second pole of the fifth switching transistor T5 is connected to a gate of the eleventh switching transistor T11. To reduce the leakage current at the node PU-CN and ensure the gate potential of the eleventh switching transistor T11 to be stable.
Optionally, in the shift register unit provided in the embodiment of the present invention, as shown in fig. 5, a thirteenth switching transistor T13 is further included; wherein: a gate of the thirteenth switching transistor T13 is connected to the reset control terminal RST, a first pole of the thirteenth switching transistor T13 is connected to the third reference voltage source, and a second pole of the thirteenth switching transistor T13 is connected to the first node PU. Thus, when the display panel needs to be discharged, a high potential signal may be provided to the first node PU through the tenth switching transistor T13 to provide a high potential signal to each row of gate lines in the display panel, so that the display panel is discharged.
In a specific implementation, as shown in fig. 5, the third reference voltage source may be the same as the first reference voltage source VG1, or the same as the second reference voltage source. As long as it is ensured that a high potential signal is supplied to the first node through the tenth switching transistor when the display panel needs to be discharged.
Optionally, in the shift register unit provided in the embodiment of the present invention, as shown in fig. 5, a fourteenth switching transistor T14 is further included; wherein: a gate of the fourteenth switching transistor T14 is connected to the touch control terminal, a first pole of the fourteenth switching transistor T14 is connected to the first reference voltage source VG1, and a second pole of the fourteenth switching transistor T14 is connected to the signal output terminal OUT. Thus, when the display panel is in the touch stage, the first reference voltage source VG1 is provided to the signal output terminal OUT through the fourteenth switching transistor T14, so as to prevent the signal output by the shift register unit from affecting touch.
Preferably, in the shift register unit according to the embodiment of the present invention, the switch transistors are generally transistors made of the same material, and in the specific implementation, when the effective pulse signal of the input signal is a high potential, all the switch transistors are N-type transistors; when the effective pulse signal of the input signal is at low potential, all the switch transistors are P-type transistors.
Furthermore, in specific implementation, the N-type switch transistor is turned on under the action of high potential and is turned off under the action of low potential; the P-type switching transistor is turned off under the action of a high potential and turned on under the action of a low potential.
It should be noted that the switch transistors mentioned in the above embodiments of the present invention are all Metal Oxide Semiconductor field effect transistors (MOS). In specific implementations, the first and second poles of these transistors may be interchanged in function, depending on the type of transistor and the input signal, and are not specifically distinguished herein.
Further, in the shift register unit provided in the embodiment of the present invention, the forward input module 01 and the backward input module 02 are designed symmetrically, so that functions can be interchanged, and thus the shift register unit provided in the embodiment of the present invention can implement bidirectional scanning. Specifically, when all the switching transistors are N-type transistors, the effective pulse signal of the input signal terminal IN is at a high potential; during forward scanning, the first reference signal terminal CN and the second reference voltage source VG2 are both high-level signals, and the second reference signal terminal CNB and the first reference voltage source VG1 are both low-level signals; in the reverse scan, the second reference signal terminal CNB and the second reference voltage source VG2 are both high-level signals, and the first reference signal terminal CN and the first reference voltage source VG1 are both low-level signals. When all the switch transistors are P-type transistors, the effective pulse signal of the input signal end IN is at low potential; during forward scanning, the first reference signal terminal CN and the second reference voltage source VG2 are both low-potential signals, and the second reference signal terminal CNB and the first reference voltage source VG1 are both high-potential signals; in the reverse scan, the second reference signal terminal CNB and the second reference voltage source VG2 are both low-level signals, and the first reference signal terminal CN and the first reference voltage source VG1 are both high-level signals.
The operation of the shift register unit provided by the embodiment of the present invention is described below by taking the shift register unit shown in fig. 4 as an example and taking forward scan as an example, and the operation timing chart of the shift register unit is shown in fig. 7 and can be divided into six stages t 1-t 6.
In the following description, a high potential signal is represented by "1" and a low potential signal is represented by "0".
IN stage t1, IN is 1, RES is 0, CK is 1, CKB is 0, CS is 0, and CSB is 1.
The sixth switching transistor T6 is turned on, the potential of the first node PU becomes high, the fifth transistor is turned on, the node PU _ CN is high, the eleventh switching transistor T11 and the second switching transistor T2 are turned on, a low potential signal of the first reference voltage source VG1 is transmitted to the third node PD through the second switching transistor T2, meanwhile, the eighth switching transistor T8 is turned on, the seventh switching transistor T7 and the ninth switching transistor T9 are turned off, the potential of the second node P is low, the tenth switching transistor T10 is turned off, the third switching transistor T3 is turned off, the potential of the third node PD is low, and the first switching transistor T1 and the twelfth switching transistor T12 are turned off. The signal output terminal OUT outputs a low signal, and the fourth switching transistor T4 is turned off.
IN stage t2, IN is 0, RES is 0, CK is 0, CKB is 1, CS is 0, and CSB is 1.
The sixth switching transistor T6 is turned off, the seventh switching transistor T7 is turned off, the ninth switching transistor T9 is turned off, the eighth switching transistor T8 is turned on, the potential of the second node P is a low potential, the tenth switching transistor T10 is turned off, the third switching transistor T3 is turned on, the fifth switching transistor T5 is turned on, the bootstrap action of the first capacitor C1 keeps the node PU _ CN at a high potential, the eleventh switching transistor T11 and the second switching transistor T2 are turned on, the low potential signal of the first reference voltage source VG1 is transmitted to the third node PD through the second switching transistor T2, the low potential signal of the first reference voltage source VG1 is transmitted to the third node PD through the second switching transistor T2, the potential of the third node PD is a low potential, and the first switching transistor T1 and the twelfth switching transistor T12 are turned off. The signal output terminal OUT outputs a low signal, and the fourth switching transistor T4 is turned off.
IN stage t3, IN is 0, RES is 0, CK is 1, CKB is 0, CS is 1, and CSB is 0.
The sixth switching transistor T6 is turned off, the seventh switching transistor T7 is turned off, the ninth switching transistor T9 is turned off, the eighth switching transistor T8 is turned on, the potential of the second node P becomes a high potential, the tenth switching transistor T10 is turned on, the third switching transistor T3 is turned off, the fifth switching transistor T5 is turned on, the node PU _ CN is further pulled high by the bootstrap action of the first capacitor C1, the eleventh switching transistor T11 and the second switching transistor T2 are turned on, the low potential signal of the first reference voltage source VG1 is transmitted to the third node PD through the second switching transistor T2, the low potential signal of the first reference voltage source VG1 is transmitted to the third node PD through the second switching transistor T2, the potential of the third node PD is a low potential, and the first switching transistor T1 and the twelfth switching transistor T12 are turned off. The signal output terminal OUT outputs a high signal, and the fourth switching transistor T4 is turned on.
IN stage t4, IN is 0, RES is 0, CK is 0, CKB is 1, CS is 1, and CSB is 0.
The sixth switching transistor T6 is turned off, the seventh switching transistor T7 is turned off, the ninth switching transistor T9 is turned off, the eighth switching transistor T8 is turned on, the potential of the second node P is high, the tenth switching transistor T10 is turned on, the third switching transistor T3 is turned on, the fifth switching transistor T5 is turned on, the bootstrap action of the first capacitor C1 keeps the node PU _ CN high, the eleventh switching transistor T11 and the second switching transistor T2 are turned on, the low-potential signal of the first reference voltage source VG1 is transmitted to the third node PD through the second switching transistor T2, the low-potential signal of the first reference voltage source VG1 is transmitted to the third node PD through the second switching transistor T2, the potential of the third node PD is low, and the first switching transistor T1 and the twelfth switching transistor T12 are turned off. The signal output terminal OUT outputs a low signal, and the fourth switching transistor T4 is turned off.
IN stage t5, IN is 0, RES is 1, CK is 1, CKB is 0, CS is 1, and CSB is 0.
The sixth switching transistor T6 is turned off, the seventh switching transistor T7 is turned on, the ninth switching transistor T9 is turned off, the eighth switching transistor T8 is turned on, the potential of the second node P is high, the tenth switching transistor T10 is turned on, the third switching transistor T3 is turned off, the potential of the first node PU becomes low, the fifth switching transistor T5 is turned on, the eleventh switching transistor T11 and the second switching transistor T2 are turned off, the potential of the third node PD becomes high, and the first switching transistor T1 and the twelfth switching transistor T12 are turned on. The signal output terminal OUT outputs a low signal, and the fourth switching transistor T4 is turned off.
IN stage t6, IN is 0, RES is 0, CK is 0, CKB is 0, CS is 0, and CSB is 1.
The sixth switching transistor T6 is turned off, the seventh switching transistor T7 is turned off, the ninth switching transistor T9 is turned off, the eighth switching transistor T8 is turned on, the potential of the second node P is high, the tenth switching transistor T10 is turned on, the third switching transistor T3 is turned on, the fifth switching transistor T5 is turned on, the eleventh switching transistor T11 and the second switching transistor T2 are turned off, the potential of the third node PD becomes high, and the first switching transistor T1 and the twelfth switching transistor T12 are turned on. The signal output terminal OUT outputs a low signal, and the fourth switching transistor T4 is turned off.
Specifically, as shown in fig. 6, when all the switch transistors in the shift register unit are P-type transistors, the operation timing diagram is shown in fig. 8, and the specific operation principle is the same as that of the shift register unit shown in fig. 4, and will not be described in detail herein.
Based on the same inventive concept, an embodiment of the present invention further provides a gate driving circuit, as shown in fig. 9, including a plurality of cascaded shift register units GOAn; wherein the content of the first and second substances,
except the first-stage shift register unit GOA1, the signal output end OUTn of each shift register unit GOAn is respectively connected with the reset signal end RES of the adjacent previous-stage shift register unit GOAn-1;
except the last stage of shift register unit GOAN, the signal output terminal OUTn of each stage of shift register unit GOAN is connected to the input signal terminal IN of the next stage of shift register unit GOAN + 1.
Since the principle of the gate driving circuit for solving the problem is similar to that of the shift register unit, the implementation of the gate driving circuit can refer to the implementation of the shift register unit, and repeated details are not repeated.
The shift register unit and the gate driving circuit provided by the embodiment of the invention comprise: the device comprises a forward input module, a reverse input module, a forward control module, a reverse control module, an output module, a node control module and an adjusting module; the forward control module and the reverse control module are respectively used for controlling the second node, so that the regulating module enables the third switching transistor in the node control module to be connected with the third node under the control of the second node, thereby ensuring that the forward control module controls the second node when the forward input module provides a signal to the first node, and enabling the regulating module to disconnect the third switching transistor and the third node in the node control module under the control of the second node, so as to avoid forming a direct current path in the shift registering unit, reduce the power consumption of the shift registering unit, effectively improve the competitive relationship between the first switching transistor and the second switching transistor, and improve the reliability of the panel.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (11)
1. A shift register unit, comprising: the device comprises a forward input module, a reverse input module, a forward control module, a reverse control module, an output module, a node control module and an adjusting module;
the forward input module is used for providing a signal of a first reference signal end to a first node under the control of an input signal end;
the inverting input module is used for providing a signal of a second reference signal terminal to the first node under the control of a reset signal terminal;
the forward control module is used for providing a signal of a first clock signal end to a second node under the control of the first reference signal end;
the reverse control module is used for providing a signal of a second clock signal end to the second node under the control of the second reference signal end;
the node control module comprises a first switch transistor, a second switch transistor, a third switch transistor and a fourth switch transistor; the first switch transistor is used for conducting a first reference voltage source and the first node under the control of a third node, the second switch transistor is used for conducting the first reference voltage source and the third node under the control of the first node, the third switch transistor is used for conducting a third clock signal end and the adjusting module under the control of a third clock signal end, and the fourth switch transistor is used for conducting the first reference voltage source and the third node under the control of a signal output end;
the adjusting module is used for enabling the third switching transistor to be conducted with the third node under the control of the second node;
the output module is configured to provide a signal of a fourth clock signal terminal to the signal output terminal under the control of the first node, or provide a signal of the first reference voltage source to the signal output terminal under the control of the third node.
2. The shift register cell of claim 1, wherein the forward input block comprises a sixth switching transistor; wherein:
a gate of the sixth switching transistor is connected to the input signal terminal, a first pole of the sixth switching transistor is connected to the first reference signal terminal, and a second pole of the sixth switching transistor is connected to the first node.
3. The shift register cell of claim 1, wherein the inverting input module comprises a seventh switching transistor; wherein:
a gate of the seventh switching transistor is connected to the reset signal terminal, a first pole of the seventh switching transistor is connected to the second reference signal terminal, and a second pole of the seventh switching transistor is connected to the first node.
4. The shift register cell of claim 1, wherein the forward control block comprises an eighth switching transistor; wherein:
a gate of the eighth switching transistor is connected to the first reference signal terminal, a first pole of the eighth switching transistor is connected to the first clock signal terminal, and a second pole of the eighth switching transistor is connected to the second node.
5. The shift register cell of claim 1, wherein the inversion control module comprises a ninth switching transistor; wherein:
the gate of the ninth switching transistor is connected to the second reference signal terminal, the first pole of the ninth switching transistor is connected to the second clock signal terminal, and the second pole of the ninth switching transistor is connected to the second node.
6. The shift register cell of claim 1, wherein the adjustment module comprises a tenth switching transistor; wherein:
a gate of the tenth switching transistor is connected to the second node, a first pole of the tenth switching transistor is connected to the third switching transistor, and a second pole of the tenth switching transistor is connected to the third node.
7. The shift register cell of claim 1, wherein the output module comprises an eleventh switching transistor, a twelfth switching transistor, a first capacitor, and a second capacitor; wherein:
a gate of the eleventh switching transistor is connected to the first node, a first pole of the eleventh switching transistor is connected to the fourth clock signal terminal, and a second pole of the eleventh switching transistor is connected to the signal output terminal;
a gate of the twelfth switching transistor is connected to the third node, a first pole of the twelfth switching transistor is connected to the first reference voltage source, and a second pole of the twelfth switching transistor is connected to the signal output terminal;
the first capacitor is connected between the grid electrode of the eleventh switching transistor and the signal output end;
the second capacitor is connected between the third node and the first reference voltage source.
8. The shift register unit according to claim 7, further comprising: a fifth switching transistor connected between the first node and a gate of the eleventh switching transistor; wherein the content of the first and second substances,
a gate of the fifth switching transistor is connected to a second reference voltage source, a first pole of the fifth switching transistor is connected to the first node, and a second pole of the fifth switching transistor is connected to a gate of the eleventh switching transistor.
9. The shift register cell of claim 1, further comprising a thirteenth switching transistor; wherein:
the gate of the thirteenth switching transistor is connected to the reset control terminal, the first pole of the thirteenth switching transistor is connected to a third reference voltage source, and the second pole of the thirteenth switching transistor is connected to the first node.
10. The shift register cell of claim 1, further comprising a fourteenth switching transistor; wherein:
a gate of the fourteenth switching transistor is connected to the touch control terminal, a first pole of the fourteenth switching transistor is connected to the first reference voltage source, and a second pole of the fourteenth switching transistor is connected to the signal output terminal.
11. A gate driver circuit comprising a plurality of shift register units according to any one of claims 1 to 10 in cascade; wherein the content of the first and second substances,
except the first stage of shift register unit, the signal output end of each stage of shift register unit is respectively connected with the reset signal end of the adjacent previous stage of shift register unit;
except the last stage of shift register unit, the signal output end of each stage of shift register unit is respectively connected with the input signal end of the next stage of shift register unit.
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