CN207134354U

CN207134354U - A kind of sensitive circuit structure and system level chip

Info

Publication number: CN207134354U
Application number: CN201720886923.0U
Authority: CN
Inventors: 李秦; 王钊
Original assignee: Wuxi Zhonggan Microelectronics Co Ltd
Current assignee: Wuxi Zhonggan Microelectronics Co Ltd
Priority date: 2017-07-20
Filing date: 2017-07-20
Publication date: 2018-03-23
Anticipated expiration: 2027-07-20

Abstract

The domain structure field for suppressing noise is the utility model is related to, discloses a kind of sensitive circuit structure, including more metal layers, the bottom of the more metal layers is arranged to sensitive circuit layer, and top layer is arranged to metal cap；The metal cap is grounded by external pad.The metal cap is shaped to netted.The width of the metal wire of the metal cap is more than 10 μm.On the premise of chip area is not increased, noise is restrained effectively, improves circuit performance.

Description

A kind of sensitive circuit structure and system level chip

Technical field

It the utility model is related to the construction applications for suppressing noise, more particularly to a kind of method for isolating noise with metal cap.

Background technology

It is inner in system level chip (SOC), various noises generally be present, have from Switching Power Supply, also come from Digit chip, it is numerous.But some circuits are especially sensitive to noise inside chip, such as high precision clock circuit, make an uproar Sound can cause the skew of clock, cause the clock signal of output inaccurate.Therefore need to reduce as far as possible noise to these circuits Influence.Way typically now is the other noise suppression circuit of increase, is also exactly to increase noise-sensitive circuit on domain With the distance of noise source.These ways add the complexity of circuit, and chip area can also increase, and power consumption and cost are also therewith Improve.

Utility model content

The purpose of this utility model is, in place of solving above shortcomings in the prior art, is not increasing domain face Suppress noise on the premise of product, improve circuit performance.

To achieve the above object, one side the utility model provides a kind of sensitive circuit structure, including more metal layers, The bottom of the more metal layers is arranged to sensitive circuit layer, and top layer is arranged to metal cap；Metal cap is grounded by external pad.

Preferably, more metal layers are three-layer metal layer, and its bottom metal layer is arranged to sensitive circuit, and top-level metallic is set For the first metal cap, intermediate layer is arranged to the second metal cap；First metal cap and the second metal cap are grounded by pad.

Preferably, metal cap is shaped to netted.

Preferably, the width of the metal wire of metal cap is more than 10 μm.

Preferably, sensitive circuit is to the circuit of noise-sensitive, including high precision clock circuit in system level chip.

Preferably, the connection line width of metal cap and external pad is 3-8 μm.

On the other hand, the utility model provides a kind of system level chip, and the system level chip is included in one or more State sensitive circuit structure, and pad；Metal cap in sensitive circuit structure is grounded by pad.

The beneficial effects of the utility model are：The utility model sets the bottom of the more metal layers in sensitive circuit structure Sensitive circuit layer is set to, top layer is arranged to metal cap；Metal cap is grounded by external pad, metal cap be shaped to it is netted, On the premise of chip area is not increased, noise is restrained effectively, improves circuit performance.

Brief description of the drawings

Fig. 1 is a kind of sensitive circuit structure and external pad locations schematic top plan view that the utility model embodiment provides；

Fig. 2 is the locations of structures signal of a kind of sensitive circuit structure that the utility model embodiment provides and external pad Figure；

Fig. 3 is that another sensitive circuit structure that the utility model embodiment provides and external pad locations overlook signal Figure；

Fig. 4 is the locations of structures signal of another sensitive circuit structure that the utility model embodiment provides and external pad Figure；

Fig. 5 is a kind of structural representation of the metal level for sensitive circuit structure that the utility model embodiment provides；

Fig. 6 is a kind of structural representation for system level chip that the utility model embodiment provides.

Embodiment

Below we by system level chip to the high precision clock circuit structure of noise-sensitive exemplified by, with reference to accompanying drawing and reality Example is applied, the technical solution of the utility model is described in further detail.

In one embodiment, as depicted in figs. 1 and 2, the sensitive circuit includes two metal layers, and bottom is high accuracy Clock circuit 10, top layer set layer of metal cover 30, and then metal cap 30 is grounded by external pad 20, so can be outside Various noises separate, avoid impacting objective circuit.

Specifically, metal cap 30 is shaped to netted, meets that production technology has the requirement of density metal.

Specifically, the width of the metal wire of metal cap 30 is more than 10 μm, can strengthen the effect of noise suppressed.

Specifically, the connection line width of metal cap and external pad is 3-8 μm.

In the second embodiment, as shown in Figure 3 and Figure 4, the circuit structure includes three-layer metal layer, and bottom is high accuracy Clock circuit 10, top layer metallic layer are arranged to the first metal cap 31, and metallic intermediate layer layer is arranged to the second metal cap 32, the first gold medal Category cover 31 is connected with the second metal cap 32 by metal wire, and the first metal cap 31 is grounded by external pad 20, so can be Outside various noises separate, and avoid impacting objective circuit.

Specifically, the first metal cap 31 and the second metal cap 32 are shaped to netted, meet that production technology has metal The requirement of density.

Specifically, the width of the metal wire of the first metal cap 31 and the second metal cap 32 is more than 10 μm, can strengthen and make an uproar The effect that sound suppresses.

Fig. 5 is a kind of structural representation of the metal level for sensitive circuit structure that the utility model embodiment provides.

In the 3rd embodiment, as shown in figure 5, the sensitive circuit structure includes metal level M1, metal level M2, metal Layer M3, totally 5 layers of metal level, M1, M2 and M3 of bottom are arranged to sensitive electrical as bottom metal layer by metal level M4, metal level M5 Road, the M5 of top layer are arranged to the first metal cap, and middle M4 is arranged to the second metal cap.

It is needing to illustrate but, the bottom metal layer that we are previously mentioned in the embodiment above, top layer metallic layer, intermediate layer Metal level refers to relative position, is not singly to refer to layer of metal layer, the specific number of plies will determine according to actual process.

Fig. 6 is a kind of structural representation for system level chip that the utility model embodiment provides, as shown in fig. 6, this is Irrespective of size chip, including sensitive circuit structure A, sensitive circuit structure B, sensitive circuit structure C and sensitive circuit structure D, and weldering Disk, the metal cap in sensitive circuit structure are grounded by pad.

Embodiment above, has been carried out further to the purpose of this utility model, technical scheme and beneficial effect Describe in detail, should be understood that and these are only specific embodiment of the present utility model, be not used to limit this practicality New protection domain, all within the spirit and principles of the utility model, any modification, equivalent substitution and improvements done etc., It should be included within the scope of protection of the utility model.

Claims

1. a kind of sensitive circuit structure, including more metal layers, it is characterised in that：The bottom of the more metal layers is arranged to quick Inductive circuit layer, top layer are arranged to metal cap；The metal cap is grounded by external pad.

2. structure according to claim 1, it is characterised in that the more metal layers are three-layer metal layer, and its bottom is golden Category layer is arranged to sensitive circuit, and top-level metallic is arranged to the first metal cap, and intermediate layer is arranged to the second metal cap；First gold medal Category cover and second metal cap are grounded by pad.

3. structure according to claim 1 or 2, it is characterised in that the metal cap is shaped to netted.

4. structure according to claim 1 or 2, it is characterised in that the width of the metal wire of the metal cap be 10 μm with On.

5. structure according to claim 1 or 2, it is characterised in that the sensitive circuit is to noise in system level chip Sensitive circuit, including high precision clock circuit.

6. structure according to claim 1 or 2, it is characterised in that the connecting line of the metal cap and the external pad Width is 3-8 μm.

A kind of 7. system level chip, it is characterised in that：Including one or more as described in any claim in claim 1-6 Sensitive circuit structure, and pad；Metal cap in the sensitive circuit structure is grounded by the pad.