CN206672916U - Big current semiconductor device - Google Patents

Big current semiconductor device Download PDF

Info

Publication number
CN206672916U
CN206672916U CN201720164445.2U CN201720164445U CN206672916U CN 206672916 U CN206672916 U CN 206672916U CN 201720164445 U CN201720164445 U CN 201720164445U CN 206672916 U CN206672916 U CN 206672916U
Authority
CN
China
Prior art keywords
chip
shaped metal
metal pad
side pin
several
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201720164445.2U
Other languages
Chinese (zh)
Inventor
张春尧
彭兴义
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangsu Salt Core Microelectronics Co Ltd
Original Assignee
Jiangsu Salt Core Microelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Salt Core Microelectronics Co Ltd filed Critical Jiangsu Salt Core Microelectronics Co Ltd
Priority to CN201720164445.2U priority Critical patent/CN206672916U/en
Application granted granted Critical
Publication of CN206672916U publication Critical patent/CN206672916U/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The utility model discloses a kind of big current semiconductor device, including the first chip, the second chip, the first L-shaped metal pad, the second L-shaped metal pad, several left side pins, several right side pins and epoxy resin cladding;Some first gold thread both ends electrically connect with the first chip, the second chip and left side pin respectively, some second gold thread both ends electrically connect with the first chip, the second chip and right side pin respectively, the first L-shaped metal pad, the second L-shaped metal pad upper surface are provided with the annular storage cream groove of a closure along edge, the cross sectional shape that this annular stores up cream groove is inverted trapezoidal, and this annular storage cream groove is located at the fringe region of the first chip, the second chip underface and close chip.The utility model is advantageous to pin and metal pad being more firmly fixed, and improves the reliability welded between PCB, exposed metal pad, so that chip quickly conducts heat, good heat dissipation effect at work.

Description

Big current semiconductor device
Technical field
A kind of chip-packaging structure is the utility model is related to, is related to technical field of semiconductors.
Background technology
The design of IC devices is according to circuit theory diagrams, realizes the function required for circuit designers.It is referred mainly to Layout design is, it is necessary to consider the layout of external connection, and the optimization of internal electronic element is laid out, the optimization cloth of metal connecting line and through hole The various factors such as office, electromagnetic protection, heat dissipation.Outstanding IC devices design can save production cost, reach good circuit Performance and heat dispersion.Pad is most normal contact and most important concept, the pad type of selection element in the design of IC devices Consider the factors such as shape, size, arrangement form, vibration and heated situation, the Impact direction of the element.Prior art is held The problems such as easily causing device missing solder, rosin joint.
The content of the invention
The utility model purpose is to provide a kind of big current semiconductor device, and the big current semiconductor device is in an encapsulation Two chips need to isolating are encapsulated in structure, realize dual chip encapsulation function, and are advantageous to pin and metal pad more It is firmly fixed, improves the reliability welded between PCB.
To reach above-mentioned purpose, the technical solution adopted in the utility model is:A kind of big current semiconductor device, including the One chip, the second chip, the first L-shaped metal pad, the second L-shaped metal pad, several left side pins, several right side pins With epoxy resin cladding;
The first L-shaped metal pad, the second L-shaped metal pad by slide glass area and are connected at the top of slide glass area one end Rod-type extension forms, and the slide glass area of the first L-shaped metal pad is embedded in the indentation, there of the second L-shaped metal pad, and described the The slide glass area of two L-shaped metal pads is embedded in the indentation, there of the first L-shaped metal pad;
First chip, the second chip are fixed on the first L-shaped metal pad, the second L-shaped gold by the glue-line that insulate respectively Belong to the middle section of pad respective slide glass area upper surface, be arranged at the first core several left side pin spacing side by side The left side of piece, the second chip, it is arranged at the first chip, the right side of the second chip several right side pin spacing side by side, The first L-shaped metal pad, the second L-shaped metal pad its lower edge are provided with the first gap slot, the left side pin with The opposite medial extremity bottom of first L-shaped metal pad, the second L-shaped metal pad is provided with the second gap slot, the right side pin with The opposite medial extremity bottom of first L-shaped metal pad, the second L-shaped metal pad is provided with the 3rd gap slot, the epoxy resin bag Cover body and be coated on chip, the first L-shaped metal pad, the second L-shaped metal pad, several left side pins, several right side pins On, the first L-shaped metal pad, the second L-shaped metal pad, left side pin and the respective lower surface of right side pin expose ring The bottom of oxygen tree fat cladding;
Some first gold thread both ends electrically connect with the first chip, the second chip and left side pin respectively, some second Gold thread both ends electrically connect with the first chip, the second chip and right side pin respectively, the first L-shaped metal pad, the second L-shaped gold Category pad upper surface is provided with the annular storage cream groove of a closure along edge, and the cross sectional shape of this annular storage cream groove is inverted trapezoidal, this Annular storage cream groove is located at the fringe region of the first chip, the second chip underface and close chip;The left side pin, right side are drawn The metal-coated coating in lower surface of pin, the coat of metal are 1 with the thickness ratio of left side pin or right side pin:8~10.
Further improved scheme is as follows in above-mentioned technical proposal:
In such scheme, the number of the left side pin and right side pin is 3 ~ 10.
In such scheme, the coat of metal is tin layers or NiPdAu layer.
Because above-mentioned technical proposal is used, the utility model has following advantages compared with prior art:
1. the utility model big current semiconductor device, its first chip, the second chip, the first L-shaped metal pad, Two L-shaped metal pads, several left side pins, several right side pins and epoxy resin cladding, the first L-shaped metal pad, Second L-shaped metal pad forms by slide glass area and the rod-type extension being connected at the top of slide glass area one end, the first L-shaped gold The slide glass area for belonging to pad is embedded in the indentation, there of the second L-shaped metal pad, the slide glass area insertion first of the second L-shaped metal pad The indentation, there of L-shaped metal pad;Because being provided with Liang Ge slide glasses area, two cores that need to isolate are encapsulated in an encapsulating structure Piece, realize dual chip encapsulation function.
2. the utility model big current semiconductor device, its metal pad its lower edge is provided with the first gap slot, described Left side pin and the opposite medial extremity bottom of metal pad are provided with the second gap slot, and the right side pin and metal pad are opposite Medial extremity bottom is provided with the 3rd gap slot, is advantageous to pin and metal pad being more firmly fixed, improves between PCB The reliability of welding;Secondly, its chip is fixed on the middle section of metal pad upper surface by the glue-line that insulate, metal pad, Left side pin and the respective lower surface of right side pin expose the bottom of epoxy resin cladding, exposed metal pad, so as to Chip quickly conducts heat, good heat dissipation effect at work.
3. the utility model big current semiconductor device, its left side pin, the metal-coated plating in the lower surface of right side pin Layer, had both reduced device and PCB conductive contact resistance, the raising for the weld strength being also beneficial between PCB.
Brief description of the drawings
Accompanying drawing 1 is the utility model big current semiconductor device structural representation;
Accompanying drawing 2 is the partial structural diagram of accompanying drawing 1;
Accompanying drawing 3 is the A-A cross-sectional views of accompanying drawing 1.
In the figures above:101st, the first chip;102nd, the second chip;201st, the first L-shaped metal pad;202nd, the second L-shaped Metal pad;3rd, left side pin;4th, right side pin;5th, epoxy resin cladding;6th, heat conductive insulating glue-line;7th, the first gap slot; 8th, the second gap slot;9th, the 3rd gap slot;10th, annular storage cream groove;11st, the coat of metal;15th, the first gold thread;16th, the second gold thread; 21st, slide glass area;22nd, rod-type extension.
Embodiment
Below in conjunction with the accompanying drawings and embodiment is further described to the utility model:
Embodiment 1:A kind of big current semiconductor device, including the first chip 101, the second chip 102, the first L-shaped metal Pad 201, the second L-shaped metal pad 202, several left side pins 3, several right side pins 4 and epoxy resin cladding 5;
The first L-shaped metal pad 201, the second L-shaped metal pad 202 by slide glass area 21 and are connected to slide glass area 21 Rod-type extension 22 at the top of one end forms, and the slide glass area 21 of the first L-shaped metal pad 201 is embedded in the second L-shaped metal welding The indentation, there of disk 202, the slide glass area 21 of the second L-shaped metal pad 202 are embedded in the indentation, there of the first L-shaped metal pad 201;
First chip 101, the second chip 102 respectively by the glue-line 6 that insulate be fixed on the first L-shaped metal pad 201, The middle section of second L-shaped metal pad, the 202 respective upper surface of slide glass area 21, several described spacing side by side of left side pin 3 Ground is arranged at the first chip 101, the left side of the second chip 102, is arranged at first several spacing side by side of right side pin 4 The right side of chip 101, the second chip 102, the first L-shaped metal pad 201, its lower edge of the second L-shaped metal pad 202 It is provided with the first gap slot 7, the L-shaped metal pad 201 of left side pin 3 and first, the second L-shaped metal pad 202 are opposite Medial extremity bottom is provided with the second gap slot 8, the L-shaped metal pad 201 of right side pin 4 and first, the second L-shaped metal pad 202 opposite medial extremity bottoms are provided with the 3rd gap slot 9, and the epoxy resin cladding 5 is coated on chip 1, the first L-shaped metal Pad 201, the second L-shaped metal pad 202, several left side pins 3, several right side pins 4 on, the first L-shaped metal Pad 201, the second L-shaped metal pad 202, left side pin 3 and 4 respective lower surface of right side pin expose epoxy resin cladding The bottom of body 5;
Some both ends of first gold thread 15 electrically connect with the first chip 101, the second chip 102 and left side pin 3 respectively, if The dry both ends of the second gold thread of root 16 electrically connect with the first chip 101, the second chip 102 and right side pin 4 respectively, first L-shaped Metal pad 201, the upper surface of the second L-shaped metal pad 202 are provided with the annular storage cream groove 10 of a closure, this annular storage along edge The cross sectional shape of cream groove 10 is inverted trapezoidal, and this annular storage cream groove 10 is immediately below the first chip 101, the second chip 102 and leans on The fringe region of nearly chip;The left side pin 3, the metal-coated coating 11 in the lower surface of right side pin 4, the coat of metal 17 and the thickness ratio of left side pin 3 or right side pin 4 are 1:8.5.
The number of above-mentioned left side pin 3 and right side pin 4 is 8;The above-mentioned coat of metal 11 is tin layers.
Embodiment 2:A kind of big current semiconductor device, including the first chip 101, the second chip 102, the first L-shaped metal Pad 201, the second L-shaped metal pad 202, several left side pins 3, several right side pins 4 and epoxy resin cladding 5;
The first L-shaped metal pad 201, the second L-shaped metal pad 202 by slide glass area 21 and are connected to slide glass area 21 Rod-type extension 22 at the top of one end forms, and the slide glass area 21 of the first L-shaped metal pad 201 is embedded in the second L-shaped metal welding The indentation, there of disk 202, the slide glass area 21 of the second L-shaped metal pad 202 are embedded in the indentation, there of the first L-shaped metal pad 201;
First chip 101, the second chip 102 respectively by the glue-line 6 that insulate be fixed on the first L-shaped metal pad 201, The middle section of second L-shaped metal pad, the 202 respective upper surface of slide glass area 21, several described spacing side by side of left side pin 3 Ground is arranged at the first chip 101, the left side of the second chip 102, is arranged at first several spacing side by side of right side pin 4 The right side of chip 101, the second chip 102, the first L-shaped metal pad 201, its lower edge of the second L-shaped metal pad 202 It is provided with the first gap slot 7, the L-shaped metal pad 201 of left side pin 3 and first, the second L-shaped metal pad 202 are opposite Medial extremity bottom is provided with the second gap slot 8, the L-shaped metal pad 201 of right side pin 4 and first, the second L-shaped metal pad 202 opposite medial extremity bottoms are provided with the 3rd gap slot 9, and the epoxy resin cladding 5 is coated on chip 1, the first L-shaped metal Pad 201, the second L-shaped metal pad 202, several left side pins 3, several right side pins 4 on, the first L-shaped metal Pad 201, the second L-shaped metal pad 202, left side pin 3 and 4 respective lower surface of right side pin expose epoxy resin cladding The bottom of body 5;
Some both ends of first gold thread 15 electrically connect with the first chip 101, the second chip 102 and left side pin 3 respectively, if The dry both ends of the second gold thread of root 16 electrically connect with the first chip 101, the second chip 102 and right side pin 4 respectively, first L-shaped Metal pad 201, the upper surface of the second L-shaped metal pad 202 are provided with the annular storage cream groove 10 of a closure, this annular storage along edge The cross sectional shape of cream groove 10 is inverted trapezoidal, and this annular storage cream groove 10 is immediately below the first chip 101, the second chip 102 and leans on The fringe region of nearly chip;The left side pin 3, the metal-coated coating 11 in the lower surface of right side pin 4, the coat of metal 17 and the thickness ratio of left side pin 3 or right side pin 4 are 1:9.
The number of above-mentioned left side pin 3 and right side pin 4 is 4;The above-mentioned coat of metal 11 is NiPdAu layer.
During using above-mentioned big current semiconductor device, it is sealed because being provided with Liang Ge slide glasses area in an encapsulating structure Two chips that need to isolate are filled, realize dual chip encapsulation function;Secondly, be advantageous to pin and metal pad is more firm It is fixed, improve the reliability welded between PCB;Again, its exposed metal pad, so that chip quickly passes at work Heat conduction amount, good heat dissipation effect;Again, it effectively prevent, missing solder and the problem of rosin joint, both improved the carrying electric current of device, and also carried The high stability and reliability of integrated chip.
For above-described embodiment only to illustrate technical concepts and features of the present utility model, its object is to allow be familiar with technique Personage can understand content of the present utility model and implement according to this, the scope of protection of the utility model can not be limited with this. All equivalent change or modifications made according to the utility model Spirit Essence, should all cover the scope of protection of the utility model it It is interior.

Claims (3)

  1. A kind of 1. big current semiconductor device, it is characterised in that:Including the first chip(101), the second chip(102), the first L-shaped Metal pad(201), the second L-shaped metal pad(202), several left side pins(3), several right side pins(4)And epoxy Resin-coating body(5);
    The first L-shaped metal pad(201), the second L-shaped metal pad(202)By slide glass area(21)Be connected to slide glass area (21)Rod-type extension at the top of one end(22)Composition, the first L-shaped metal pad(201)Slide glass area(21)Embedded second L-shaped metal pad(202)Indentation, there, the second L-shaped metal pad(202)Slide glass area(21)Embedded first L-shaped metal Pad(201)Indentation, there;
    First chip(101), the second chip(102)Pass through the glue-line that insulate respectively(6)It is fixed on the first L-shaped metal pad (201), the second L-shaped metal pad(202)Respective slide glass area(21)The middle section of upper surface, several described left side pins (3)It is arranged at the first chip spacing side by side(101), the second chip(102)Left side, several described right side pins(4)And Row is positioned apart from the first chip(101), the second chip(102)Right side, the first L-shaped metal pad(201), second L-shaped metal pad(202)Its lower edge is provided with the first gap slot(7), the left side pin(3)With the first L-shaped metal welding Disk(201), the second L-shaped metal pad(202)Opposite medial extremity bottom is provided with the second gap slot(8), the right side pin(4) With the first L-shaped metal pad(201), the second L-shaped metal pad(202)Opposite medial extremity bottom is provided with the 3rd gap slot(9), The epoxy resin cladding(5)It is coated on chip(1), the first L-shaped metal pad(201), the second L-shaped metal pad(202)、 Several left side pins(3), several right side pins(4)On, the first L-shaped metal pad(201), the second L-shaped metal welding Disk(202), left side pin(3)With right side pin(4)Respective lower surface exposes epoxy resin cladding(5)Bottom;
    Some first gold threads(15)Both ends respectively with the first chip(101), the second chip(102)With left side pin(3)It is electrically connected Connect, some second gold threads(16)Both ends respectively with the first chip(101), the second chip(102)With right side pin(4)It is electrically connected Connect, the first L-shaped metal pad(201), the second L-shaped metal pad(202)Upper surface is provided with the ring of a closure along edge Shape stores up cream groove(10), this annular storage cream groove(10)Cross sectional shape be inverted trapezoidal, this annular storage cream groove(10)Positioned at the first chip (101), the second chip(102)Underface and the fringe region of close chip;The left side pin(3), right side pin(4)Under Coating surface has the coat of metal(11), the coat of metal(17)With left side pin(3)Or right side pin(4)Thickness ratio be 1:8~10.
  2. 2. big current semiconductor device according to claim 1, it is characterised in that:The left side pin(3)Draw with right side Pin(4)Number be 3 ~ 10.
  3. 3. big current semiconductor device according to claim 1 or 2, it is characterised in that:The coat of metal(11)For tin Layer or NiPdAu layer.
CN201720164445.2U 2017-02-23 2017-02-23 Big current semiconductor device Expired - Fee Related CN206672916U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201720164445.2U CN206672916U (en) 2017-02-23 2017-02-23 Big current semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201720164445.2U CN206672916U (en) 2017-02-23 2017-02-23 Big current semiconductor device

Publications (1)

Publication Number Publication Date
CN206672916U true CN206672916U (en) 2017-11-24

Family

ID=60379376

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201720164445.2U Expired - Fee Related CN206672916U (en) 2017-02-23 2017-02-23 Big current semiconductor device

Country Status (1)

Country Link
CN (1) CN206672916U (en)

Similar Documents

Publication Publication Date Title
CN104425417B (en) Semiconductor device and method for fabricating the same
TW201503304A (en) Semiconductor device and method of manufacture
CN203721707U (en) Chip packaging structure
CN207269022U (en) A kind of lead frame and its flip chip encapsulation structure
CN104701272B (en) A kind of chip encapsulation assembly and its manufacture method
CN206532771U (en) Cooling type semiconductor device
CN206789543U (en) High heat conduction type package structure of semiconductor device
CN206672916U (en) Big current semiconductor device
CN206595249U (en) Carry the SOP device encapsulation structures of high current
CN209104141U (en) A kind of chip exposed type encapsulating structure
CN208608186U (en) Chip-packaging structure
CN208045486U (en) Wafer stage chip encapsulating structure
CN206789540U (en) The semiconductor devices of SOT encapsulating structures
CN110429068A (en) A kind of antenna packages structure and preparation method thereof, communication equipment
CN206595248U (en) The encapsulating structure of semiconductor devices
CN206789537U (en) Surface mount rectification chip
TWI501370B (en) Semiconductor package and method of manufacture
CN206532770U (en) The new SOP structures of chip package
CN206789534U (en) High reliability chip-packaging structure
CN206992085U (en) High heat conduction power device
TWI582905B (en) Chip package structure and manufacturing method thereof
CN206532775U (en) Multichip device encapsulating structure
CN201838575U (en) Flipchip thin-small outline packaged lead frame and package structure thereof
CN106298709A (en) Low cost fan-out formula encapsulating structure
CN109065515B (en) Chip packaging structure with high conductivity and low resistance and preparation method thereof

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20171124

CF01 Termination of patent right due to non-payment of annual fee