CN206505723U - A kind of mram cell control circuit based on STT MTJ - Google Patents
A kind of mram cell control circuit based on STT MTJ Download PDFInfo
- Publication number
- CN206505723U CN206505723U CN201720106322.3U CN201720106322U CN206505723U CN 206505723 U CN206505723 U CN 206505723U CN 201720106322 U CN201720106322 U CN 201720106322U CN 206505723 U CN206505723 U CN 206505723U
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- circuit
- phase inverter
- output end
- wordline
- input
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Abstract
Circuit is controlled the utility model discloses a kind of mram cell based on STT MTJ, it includes the first wordline logic circuit, negative pulse generation circuit, the second Word line control circuit, the first phase inverter and the second phase inverter；The output end of the first wordline logic circuit is connected to the input of the first phase inverter, and the output end of first phase inverter is connected to the first wordline, and the earth terminal of first phase inverter is connected to negative pulse generation circuit；The output end of second Word line control circuit is connected to the input of the second phase inverter, and the output end of second phase inverter is connected to the second wordline.The utility model can compensate for writing 0 process electric current, so that being prevented effectively from 0 process of writing produces maloperation.
Description
Technical field
The utility model is related to storage circuit technical field, specifically related to a kind of mram cell control based on STT-MTJ
Circuit.
Background technology
Magnetoresistive RAM (MRAM, Magnetic Random Access Memory) is a kind of non-volatile magnetic
Property random access memory it possess the high speed of SRAM and read write capability, and dynamic RAM high collection
Cheng Du, and can substantially be repeatedly written infinitely.
The mram cell of one standard includes a metal-oxide-semiconductor and a STT-MTJ knot, and shown in Figure 1, MRAM is in work
During certain threshold current and write time is required to complete write-in, pass through low current and realize and read.Because MRAM has
It is preferably non-volatile, thus more and more applied.
And in standard mram cell structure, there are two kinds of asymmetry for writing 1 and writing 0.Be first 1 and 0 resistance
Difference, is the forward and reverse threshold current of identical in fact（Write activity）Under, 1 is different with the voltage of 0 write-in, for writing 0 process electricity
Stream is smaller, causes to write 0 process easily producing maloperation.
The content of the invention
Goal of the invention of the present utility model is to provide a kind of mram cell control circuit based on STT-MTJ, by introducing
Auxiliary circuit is write, 0 process electric current is write in compensation, so that being prevented effectively from 0 process of writing produces maloperation.
To achieve the above object of the invention, the technical solution adopted in the utility model is：A kind of MRAM based on STT-MTJ is mono-
Member control circuit, it includes the first wordline logic circuit, negative pulse generation circuit, the second Word line control circuit, the first phase inverter
With the second phase inverter；
The output end of the first wordline logic circuit is connected to the input of the first phase inverter, first phase inverter
Output end is connected to the first wordline, and the earth terminal of first phase inverter is connected to negative pulse generation circuit；
The output end of second Word line control circuit is connected to the input of the second phase inverter, second phase inverter
Output end is connected to the second wordline.
Preferably, first phase inverter includes the first PMOS transistor and the first nmos pass transistor；
Second phase inverter includes the second PMOS transistor and the second nmos pass transistor.
Preferably, the source electrode of first nmos pass transistor is connected to the output end of negative pulse generation circuit, described second
The source ground of nmos pass transistor.
Preferably, the negative pulse generation circuit includes the first NAND gate circuit, the second NAND gate circuit, the first NOT gate electricity
Road, the second not circuit, the 3rd not circuit, the 4th not circuit, electrolytic capacitor and the 3rd nmos pass transistor；
The input of first not circuit is connected to the first wordline, the input difference of first NAND gate circuit
It is connected to the inside timing control signal end of the output end, the second wordline and negative pulse generation circuit of the first NOT gate, described first
The output end of NAND gate circuit is connected to the input of the second not circuit, and the input of second NAND gate circuit connects respectively
It is connected to the output end of the second not circuit and enables signal end, the output end of second NAND gate circuit is connected to the 3rd NOT gate
The input of circuit, the output end of the 3rd not circuit is connected to the input of the 4th not circuit, the 4th NOT gate
The output end of circuit is connected respectively to the positive pole of electrolytic capacitor and the grid of the 3rd nmos pass transistor, the electrolytic capacitor
The source electrode of negative pole and the 3rd nmos pass transistor is all connected to the earth terminal of the first phase inverter, the drain electrode of the 3rd nmos pass transistor
Ground connection.
Preferably, the negative pulse generation circuit only the second wordline level be 1 and first wordline level be 0 when output it is negative
Pulse.
Because above-mentioned technical proposal is used, the utility model has following advantages compared with prior art：
The utility model writes auxiliary circuit by introducing, wherein, the negative pulse generation circuit is only in the second wordline level
For 1 and first wordline level be 0 when export negative pulse, can compensate for writing 0 process electric current, thus be prevented effectively from write 0 process generation
Maloperation.
Brief description of the drawings
Fig. 1 is the first wordline logic electrical block diagram of the utility model embodiment one.
Fig. 2 is the second wordline logic electrical block diagram of the utility model embodiment one.
Fig. 3 is the negative pulse generation circuit structural representation of the utility model embodiment one.
Embodiment
Below in conjunction with the accompanying drawings and embodiment is further described to the utility model：
Embodiment one：
Referring to shown in Fig. 1 to 3, a kind of mram cell based on STT-MTJ controls circuit, and it includes the first wordline logic electricity
Road, negative pulse generation circuit, the second Word line control circuit, the first phase inverter and the second phase inverter；
The output end of the first wordline logic circuit is connected to the input of the first phase inverter, first phase inverter
Output end is connected to the first wordline, and the earth terminal of first phase inverter is connected to negative pulse generation circuit；
The output end of second Word line control circuit is connected to the input of the second phase inverter, second phase inverter
Output end is connected to the second wordline.
In the present embodiment, first phase inverter and the second phase inverter are existing standard CMOS phase inverter, wherein, institute
Stating the first phase inverter includes the first PMOS transistor MP1 and the first nmos pass transistor MN1；
Second phase inverter includes the second PMOS transistor MP2 and the second nmos pass transistor MN2.
The source electrode of the first nmos pass transistor MN1 is connected to the output end of negative pulse generation circuit, the 2nd NMOS
Transistor MN2 source ground.
The negative pulse generation circuit is by internal timing control signal GIC, the first wordline BL level, the second wordline BLB electricity
Flat and enable signal NBLEN co- controllings, specially including the first NAND gate circuit, the second NAND gate circuit, the first NOT gate
Circuit, the second not circuit, the 3rd not circuit, the 4th not circuit, electrolytic capacitor and the 3rd nmos pass transistor MN3；
The input of first not circuit is connected to the first wordline BL, the input point of first NAND gate circuit
The inside timing control signal end of output end, the second wordline BLB and the negative pulse generation circuit of the first NOT gate is not connected to, it is described
The output end of first NAND gate circuit is connected to the input of the second not circuit, the input point of second NAND gate circuit
The output end of the second not circuit is not connected to and signal end is enabled, and the output end of second NAND gate circuit is connected to the 3rd
The input of not circuit, the output end of the 3rd not circuit is connected to the input of the 4th not circuit, the described 4th
The output end of not circuit is connected respectively to the positive pole of electrolytic capacitor and the 3rd nmos pass transistor MN3 grid, the electrolysis
The negative pole of capacitor and the 3rd nmos pass transistor MN3 source electrode are all connected to the earth terminal of the first phase inverter, the 3rd NMOS
Transistor MN3 grounded drain.
The negative pulse generation circuit only when writing 0, i.e. the second wordline BLB level be 1 and first wordline BL level be 0
When, negative pulse is exported, to compensate reset current, now MTJ is in anti-parallel state；Other moment negative pulse generation circuits are output as
Ground.
Claims (5)
1. a kind of mram cell control circuit based on STT-MTJ, it is characterised in that：It includes the first wordline logic circuit, born
Pulse-generating circuit, the second Word line control circuit, the first phase inverter and the second phase inverter；
The output end of the first wordline logic circuit is connected to the input of the first phase inverter, the output of first phase inverter
End is connected to the first wordline, and the earth terminal of first phase inverter is connected to negative pulse generation circuit；
The output end of second Word line control circuit is connected to the input of the second phase inverter, the output of second phase inverter
End is connected to the second wordline.
2. the mram cell control circuit according to claim 1 based on STT-MTJ, it is characterised in that：Described first is anti-
Phase device includes the first PMOS transistor and the first nmos pass transistor；
Second phase inverter includes the second PMOS transistor and the second nmos pass transistor.
3. the mram cell control circuit according to claim 2 based on STT-MTJ, it is characterised in that：Described first
The source electrode of nmos pass transistor is connected to the output end of negative pulse generation circuit, the source ground of second nmos pass transistor.
4. the mram cell control circuit according to claim 1 based on STT-MTJ, it is characterised in that：The negative pulse
Generation circuit includes the first NAND gate circuit, the second NAND gate circuit, the first not circuit, the second not circuit, the 3rd NOT gate
Circuit, the 4th not circuit, electrolytic capacitor and the 3rd nmos pass transistor；
The input of first not circuit is connected to the first wordline, and the input of first NAND gate circuit is connected respectively
The inside timing control signal end of output end, the second wordline and negative pulse generation circuit to the first NOT gate, described first with it is non-
The output end of gate circuit is connected to the input of the second not circuit, and the input of second NAND gate circuit is connected respectively to
The output end and enable signal end of second not circuit, the output end of second NAND gate circuit are connected to the 3rd not circuit
Input, the output end of the 3rd not circuit is connected to the input of the 4th not circuit, the 4th not circuit
Output end be connected respectively to the positive pole of electrolytic capacitor and the grid of the 3rd nmos pass transistor, the negative pole of the electrolytic capacitor
The earth terminal of the first phase inverter is all connected to the source electrode of the 3rd nmos pass transistor, the drain electrode of the 3rd nmos pass transistor connects
Ground.
5. the control circuit of the mram cell based on STT-MTJ according to claim 1 or 4, it is characterised in that：The negative arteries and veins
Rush generation circuit only the second wordline level be 1 and first wordline level be 0 when export negative pulse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720106322.3U CN206505723U (en) | 2017-02-03 | 2017-02-03 | A kind of mram cell control circuit based on STT MTJ |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720106322.3U CN206505723U (en) | 2017-02-03 | 2017-02-03 | A kind of mram cell control circuit based on STT MTJ |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206505723U true CN206505723U (en) | 2017-09-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720106322.3U Expired - Fee Related CN206505723U (en) | 2017-02-03 | 2017-02-03 | A kind of mram cell control circuit based on STT MTJ |
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| CN (1) | CN206505723U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106782640A (en) * | 2017-02-03 | 2017-05-31 | 苏州大学 | A kind of mram cell control circuit based on STT MTJ |
-
2017
- 2017-02-03 CN CN201720106322.3U patent/CN206505723U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106782640A (en) * | 2017-02-03 | 2017-05-31 | 苏州大学 | A kind of mram cell control circuit based on STT MTJ |
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| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170919 Termination date: 20200203 |
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| CF01 | Termination of patent right due to non-payment of annual fee |