CN112382325B - Sub-threshold SRAM read-write auxiliary circuit - Google Patents
Sub-threshold SRAM read-write auxiliary circuit Download PDFInfo
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- CN112382325B CN112382325B CN202011436085.XA CN202011436085A CN112382325B CN 112382325 B CN112382325 B CN 112382325B CN 202011436085 A CN202011436085 A CN 202011436085A CN 112382325 B CN112382325 B CN 112382325B
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- 239000003990 capacitor Substances 0.000 claims abstract description 25
- 230000001133 acceleration Effects 0.000 claims abstract description 20
- 230000001808 coupling effect Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
Abstract
The invention provides a sub-threshold SRAM read-write auxiliary circuit, which comprises: the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the NMOS transistor, the capacitor and the inverter. The grid electrode of the first PMOS transistor is connected with a read auxiliary control signal and is used for connecting the positive electrode of a power supply andVDDWL. The grid electrode of the second PMOS transistor is connected with a read acceleration control signal and is used for connecting the positive electrode of a power supply andVDDWL. The gate of the third PMOS transistor is connected with the input signal for connectingVDDWLAnd a word line. The gate of the fourth PMOS transistor MP4 is connected to the read-assist control signal, and is used to connect the ground line and the word line of the power supply. The gate of the NMOS transistor is connected with an input signal for connecting with the ground GND of the power supply. The upper polar plate of the capacitor is connected with the word line, and the lower polar plate is connected with the output of the inverter. The inverter input is a write assist control signal. The invention realizes the quick access of the SRAM on the premise of ensuring the reading stability. And the word line is raised by the coupling action of the capacitor so that the voltage of the word line is higher than the voltage of the power supply, thereby realizing the write assistance.
Description
Technical Field
The invention relates to the technical field of memory access, in particular to a sub-threshold SRAM read-write auxiliary circuit.
Background
As the cell supply voltage decreases, the read stability and write capability of the SRAM (Static Random Access Memory ) decreases. When the SRAM performs a read operation, the data stored in the cell is easy to change, so that the SRAM is in error function. Word line under-voltage read assist circuitry is a common read assist circuitry, but conventional read assist circuitry negatively affects the access time and write capability of the SRAM. How to reduce access time and strengthen writing capability on the premise of ensuring reading stability becomes a technical problem to be solved urgently.
Disclosure of Invention
The invention aims to provide a sub-threshold SRAM read-write auxiliary circuit so as to reduce access time and strengthen write capability on the premise of ensuring read stability.
In order to achieve the above object, the present invention provides the following solutions:
a sub-threshold SRAM read/write assist circuit, said assist circuit comprising: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, an NMOS transistor, a capacitor, and an inverter;
the source electrode of the first PMOS transistor and the source electrode of the second PMOS transistor are connected with the positive electrode of the power supply, the drain electrode of the first PMOS transistor and the drain electrode of the second PMOS transistor are connected with the source electrode of the third PMOS transistor, the grid electrode of the first PMOS transistor is connected with the read auxiliary control signal, and the grid electrode of the second PMOS transistor is connected with the read acceleration control signal;
the drain electrode of the third PMOS transistor, the drain electrode of the NMOS transistor, the source electrode of the fourth PMOS transistor and the positive plate of the capacitor are all connected with a word line; the grid electrode of the third PMOS transistor and the grid electrode of the NMOS transistor are connected with an input signal; the source electrode of the NMOS transistor is connected with the ground wire of the power supply;
the drain electrode of the fourth PMOS transistor is connected with the ground wire of the power supply, and the grid electrode of the fourth PMOS transistor is connected with the read auxiliary control signal;
the negative plate of the capacitor is connected with the output end of the inverter, and the input end of the inverter is connected with the write auxiliary control signal.
Optionally, when the under-voltage read assist operation is performed: the read auxiliary control signal is at a low level, the read acceleration control signal is at a high level, at this time, the first PMOS transistor and the fourth PMOS transistor are turned on, and the second PMOS transistor is turned off.
Optionally, when the input signal is at a low level, the third PMOS transistor is turned on, the NMOS transistor is turned off, and the output voltage of the word line is an intermediate level voltage divided by the first PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor.
Optionally, when the input signal is at a high level, the third PMOS transistor is turned off, the NMOS transistor is turned on, and the output voltage of the word line is a low level voltage pulled down by the NMOS transistor.
Alternatively, when the read acceleration operation is performed: the read assist control signal is high, and the read speed up control signal is low, and at this time, the first PMOS transistor and the fourth PMOS transistor are turned off, and the second PMOS transistor is turned on.
Optionally, when the input signal is at a low level, the third PMOS transistor is turned on, the NMOS transistor is turned off, the output voltage of the word line is increased to the voltage of the power supply by charging the capacitor, then the read acceleration control signal is set to a high level, the second PMOS transistor is turned off, and the voltage of the lower plate of the capacitor is raised by the write assist control signal, so that the output voltage of the word line is higher than the voltage of the power supply.
Optionally, when the input signal is at a high level, the third PMOS transistor is turned off, the NMOS transistor is turned on, and the output voltage of the word line is a low level voltage pulled down by the NMOS transistor.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention provides a sub-threshold SRAM read-write auxiliary circuit, which comprises: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, an NMOS transistor, a capacitor, and an inverter; the source electrode of the first PMOS transistor and the source electrode of the second PMOS transistor are connected with the positive electrode of the power supply, the drain electrode of the first PMOS transistor and the drain electrode of the second PMOS transistor are connected with the source electrode of the third PMOS transistor, the grid electrode of the first PMOS transistor is connected with the read auxiliary control signal, and the grid electrode of the second PMOS transistor is connected with the read acceleration control signal; the drain electrode of the third PMOS transistor, the drain electrode of the NMOS transistor, the source electrode of the fourth PMOS transistor and the positive plate of the capacitor are all connected with a word line; the grid electrode of the third PMOS transistor and the grid electrode of the NMOS transistor are connected with an input signal; the source electrode of the NMOS transistor is connected with the ground wire of the power supply; the drain electrode of the fourth PMOS transistor is connected with the ground wire of the power supply, and the grid electrode of the fourth PMOS transistor is connected with the read auxiliary control signal; the negative plate of the capacitor is connected with the output end of the inverter, and the input end of the inverter is connected with the write auxiliary control signal. The invention realizes the quick access of the SRAM on the premise of ensuring the reading stability. And the word line is raised by the coupling action of the capacitor so that the voltage of the word line is higher than the voltage of the power supply, thereby realizing the write assistance.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a circuit diagram of a sub-threshold SRAM read-write assist circuit provided by the present invention;
fig. 2 is a working schematic diagram of a sub-threshold SRAM read/write assist circuit according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention aims to provide a sub-threshold SRAM read-write auxiliary circuit so as to reduce access time and strengthen write capability on the premise of ensuring read stability.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
As shown in fig. 1, the invention discloses a subthreshold SRAM read/write auxiliary circuit, which comprises: the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the NMOS transistor MN1, the capacitor CAP, and the inverter INV.
The source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are both connected with the positive electrode of the power supplyVDDThe drain of the first PMOS transistor MP1 and the drain of the second PMOS transistor MP2 are connected with the source of the third PMOS transistor MP3, and the gate of the first PMOS transistor MP1 is connected with a read auxiliary control signalA(read auxiliary control Signal)AThe waveform of (2) is as V #, in figure 2A) Shown) is connected with the gate of the second PMOS transistor and the read acceleration control signalB(read acceleration control Signal)BThe waveform of (2) is as V #, in figure 2B) Shown) are connected. That is, as shown in FIG. 1, the gate of the first PMOS transistor MP1 is connected to the read auxiliary control signalAPositive electrode for connecting power supplyVDDVoltage line to word lineVDDWL. The grid electrode of the second PMOS transistor MP2 is connected with a read acceleration control signalBPositive electrode for connecting power supplyVDDVoltage line to word lineVDDWL。
The drain of the third PMOS transistor MP3, the drain of the NMOS transistor MN1, the source of the fourth PMOS transistor MP4, and the positive plate of the capacitor CAP are connected to a word lineWLConnection, word lineWLThe waveform of the upper signal is as V in figure 2WL) The method comprises the steps of carrying out a first treatment on the surface of the The gate of the third PMOS transistor MP3 and the gate of the NMOS transistor MN1 are both connected with the input signalWLnConnection, input signalWLnThe waveform of (2) is as V #, in figure 2WLn) The method comprises the steps of carrying out a first treatment on the surface of the The source of the NMOS transistor MN1 is connected with the ground line of the power supply. That is, as shown in FIG. 1, the gate of the third PMOS transistor MP3 is connected to the input signalWLnFor connectingVDDWLAndWL. NMOS transistor MN1 having a gate connected to an input signalWLnGround wire for connecting power supply andVDDWL。
the drain of the fourth PMOS transistor MP4 is connected with the ground line of the power supply, and the gate of the fourth PMOS transistor MP4 is connected with the read auxiliary control signalAAnd (5) connection. That is, as shown in FIG. 1, the gate of the fourth PMOS transistor MP4 is connected to the read auxiliary control signalAGround and word lines for connecting power supplyWL。
The negative plate of the capacitor CAP is connected with the output end of an inverter INV, and the input end of the inverter INV is connected with a write auxiliary control signalC. Inverter INV, input as write assist control signalCWrite assist control signalCIs of the waveform of (a)As V in figure 2C) The output is connected with the lower polar plate of the capacitor CAP.
The working principle is as follows: as shown in fig. 2, when the under-voltage read assist operation is performed: read-assisted control signalALow level, read acceleration control signalBAt a high level, i.e. read-assist control signalAWaveform V #, ofA) Low level, read acceleration control signalBWaveform V #, ofB) At this time, the first PMOS transistor MP1 and the fourth PMOS transistor MP4 are turned on, and the second PMOS transistor MP2 is turned off. When the input signal is low, i.e. waveform V of the input signal in FIG. 2WLn) At low level, the third PMOS transistor MP3 is turned on, the NMOS transistor MN1 is turned off, and the word lineWLThe output voltage of (a) is the intermediate level voltage divided by the first PMOS transistor MP1, the third PMOS transistor MP3 and the fourth PMOS transistor MP4, such as the word line in FIG. 2WLWaveform V #, ofWL) As shown. When inputting signalsWLnAt a high level, i.e. waveform V of the input signal in FIG. 2WLn) At high level, the third PMOS transistor MP3 is turned off, the NMOS transistor MN1 is turned on, and the word lineWLThe output voltage of (a) is a low level voltage pulled down by NMOS transistor, such as word line in FIG. 2WLWaveform V #, ofWL) As shown.
When a read acceleration operation is performed: read-assisted control signalAHigh level, read acceleration control signalBAt a low level, i.e. read-assist control signalAWaveform V #, ofA) High level, read acceleration control signalBWaveform V #, ofB) At this time, the first PMOS transistor MP1 and the fourth PMOS transistor MP4 are turned off, and the second PMOS transistor MP2 is turned on. When the input signal is low, i.e. waveform V of the input signal in FIG. 2WLn) At low level, the third PMOS transistor MP3 is turned on, the NMOS transistor MN1 is turned off, and the capacitor CAP is charged to charge the word lineWLThe output voltage of (a) is slowly increased to the voltage of the power supply, such as the word line in FIG. 2WLWaveform V #, ofWL) As shown, then, read acceleration control signalBSet to high level, i.e. read acceleration control signalBWaveform V #, ofB) Set to high level to turn off the second PMOS transistor MP2 and pass the write assist control signalC(write assist control Signal)CThe waveform of (2) is as V #, in figure 2C) Raising the voltage of the lower plate of the capacitor CAP to make the word lineWLThe output voltage of (a) is higher than the voltage of the power supply, such as the word line in FIG. 2WLWaveform V #, ofWL) As shown. When the input signal is at a high level, i.e., waveform V of the input signal in FIG. 2WLn) At high level, the third PMOS transistor MP3 is turned off, the NMOS transistor MN1 is turned on, and the word lineWLThe output voltage of (a) is a low level voltage pulled down by NMOS transistor MN1, such as the word line in FIG. 2WLWaveform V #, ofWL) As shown.
The specific function of the present invention is realized as follows, in the beginning stage of the word line rising, the first PMOS transistor MP1, the fourth PMOS transistor MP4 are turned on, and the second PMOS transistor MP2 is turned off.VDDWLFrom the following componentsVDDThe first PMOS transistor MP1 is powered, the first PMOS transistor MP1, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 form a voltage division, and the word lineWLThe signal of the (C) is quickly stabilized at the middle level, and the word line under-voltage reading assistance is realized. The first PMOS transistor MP1 and the fourth PMOS transistor MP4 are then turned off, and the second PMOS transistor MP2 is turned on.VDDForming RC load through small-sized second PMOS transistor MP2 and capacitance on word line, slowly connecting word lineWLIs charged toVDD. The second PMOS transistor MP2 is then turned off and the output of the inverter INV is pulled high to charge the lower plate of the capacitor. By coupling action of the capacitor CAP, the word line is further raised to make the word line voltage higher thanVDDWrite assist is achieved. On the premise of ensuring the read stability, the SRAM is accessed quickly, and the writing capability is improved.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present invention and the core ideas thereof; also, it is within the scope of the present invention to be modified by those of ordinary skill in the art in light of the present teachings. In view of the foregoing, this description should not be construed as limiting the invention.
Claims (7)
1. A sub-threshold SRAM read/write assist circuit, said assist circuit comprising: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, an NMOS transistor, a capacitor, and an inverter;
the source electrode of the first PMOS transistor and the source electrode of the second PMOS transistor are connected with the positive electrode of the power supply, the drain electrode of the first PMOS transistor and the drain electrode of the second PMOS transistor are connected with the source electrode of the third PMOS transistor, the grid electrode of the first PMOS transistor is connected with the read auxiliary control signal, and the grid electrode of the second PMOS transistor is connected with the read acceleration control signal;
the drain electrode of the third PMOS transistor, the drain electrode of the NMOS transistor, the source electrode of the fourth PMOS transistor and the positive plate of the capacitor are all connected with a word line; the grid electrode of the third PMOS transistor and the grid electrode of the NMOS transistor are connected with an input signal; the source electrode of the NMOS transistor is connected with the ground wire of the power supply;
the drain electrode of the fourth PMOS transistor is connected with the ground wire of the power supply, and the grid electrode of the fourth PMOS transistor is connected with the read auxiliary control signal;
the negative plate of the capacitor is connected with the output end of the inverter, and the input end of the inverter is connected with the write auxiliary control signal.
2. The sub-threshold SRAM read/write assist circuit of claim 1, wherein, when performing an under-voltage read assist operation: the read auxiliary control signal is at a low level, the read acceleration control signal is at a high level, at this time, the first PMOS transistor and the fourth PMOS transistor are turned on, and the second PMOS transistor is turned off.
3. The sub-threshold SRAM read/write assist circuit according to claim 2, wherein when the input signal is at a low level, the third PMOS transistor is turned on, the NMOS transistor is turned off, and the output voltage of the word line is an intermediate level voltage divided by the first PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor.
4. The sub-threshold SRAM read/write assist circuit as claimed in claim 2, wherein when the input signal is high, the third PMOS transistor is turned off, the NMOS transistor is turned on, and the output voltage of the word line is a low level voltage pulled down by the NMOS transistor.
5. The sub-threshold SRAM read/write assist circuit according to claim 1, wherein, when performing a read acceleration operation: the read assist control signal is high, and the read speed up control signal is low, and at this time, the first PMOS transistor and the fourth PMOS transistor are turned off, and the second PMOS transistor is turned on.
6. The sub-threshold SRAM read/write assist circuit of claim 5 wherein when the input signal is low, the third PMOS transistor is turned on and the NMOS transistor is turned off, the output voltage of the wordline is increased to the voltage of the power supply by charging the capacitor, then the read acceleration control signal is set high, the second PMOS transistor is turned off, and the voltage of the lower plate of the capacitor is raised by the write assist control signal, so that the output voltage of the wordline is higher than the voltage of the power supply.
7. The sub-threshold SRAM read/write assist circuit according to claim 5, wherein when the input signal is high, the third PMOS transistor is turned off, the NMOS transistor is turned on, and the output voltage of the word line is low voltage pulled down by the NMOS transistor.
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| CN112382325B true CN112382325B (en) | 2024-03-05 |
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| JP4912016B2 (en) * | 2005-05-23 | 2012-04-04 | ルネサスエレクトロニクス株式会社 | Semiconductor memory device |
| KR101505554B1 (en) * | 2008-09-08 | 2015-03-25 | 삼성전자주식회사 | Semiconductor Memory Device, Method of Operating the same |
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| KR20000026835A (en) * | 1998-10-23 | 2000-05-15 | 김영환 | Output driver of semiconductor element |
| JP2007058979A (en) * | 2005-08-24 | 2007-03-08 | Matsushita Electric Ind Co Ltd | Semiconductor storage device |
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