CN112382325A - Sub-threshold SRAM read-write auxiliary circuit - Google Patents
Sub-threshold SRAM read-write auxiliary circuit Download PDFInfo
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- CN112382325A CN112382325A CN202011436085.XA CN202011436085A CN112382325A CN 112382325 A CN112382325 A CN 112382325A CN 202011436085 A CN202011436085 A CN 202011436085A CN 112382325 A CN112382325 A CN 112382325A
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- 230000001133 acceleration Effects 0.000 claims abstract description 21
- 230000001808 coupling effect Effects 0.000 abstract description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
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- Static Random-Access Memory (AREA)
Abstract
The invention provides a sub-threshold SRAM read-write auxiliary circuit, which comprises: the transistor comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, an NMOS transistor, a capacitor and an inverter. The grid electrode of the first PMOS transistor is connected with a reading auxiliary control signal and is used for being connected with the positive electrode of a power supplyVDDWL. The grid of the second PMOS transistor is connected with a read acceleration control signal and is used for connecting the positive pole of a power supplyVDDWL. The gate of the third PMOS transistor is connected with the input signal for connectionVDDWLAnd a word line. The gate of the fourth PMOS transistor MP4 is connected to the read assist control signal for connecting the ground line of the power supply and the word line. The gate of the NMOS transistor is connected with an input signal and is used for being connected with a ground wire GND of a power supply. The upper polar plate of the capacitor is connected with the word line, and the lower polar plate of the capacitor is connected with the output of the phase inverter. The inverter input is the write assist control signal. The invention realizes the quick access of the SRAM on the premise of ensuring the reading stability. And the word line is raised by utilizing the coupling effect of the capacitor, so that the voltage of the word line is higher than the power supply voltage, and the writing assistance is realized.
Description
Technical Field
The invention relates to the technical field of memory access, in particular to a sub-threshold SRAM read-write auxiliary circuit.
Background
As the cell supply voltage decreases, the read stability and write capability of an SRAM (Static Random Access Memory) decreases. When the SRAM is read, the data stored in the unit is easy to change, which causes the function error of the SRAM. The word line undervoltage read assist circuit is a commonly used read assist circuit, but the conventional read assist circuit has a negative influence on the access time and the write capability of the SRAM. How to realize on the premise of ensuring the reading stability, the access time is reduced, and the writing capability is enhanced, which becomes a technical problem to be solved urgently.
Disclosure of Invention
The invention aims to provide a sub-threshold SRAM read-write auxiliary circuit to reduce access time and enhance write capability on the premise of ensuring read stability.
In order to achieve the purpose, the invention provides the following scheme:
a sub-threshold SRAM read-write assist circuit, the assist circuit comprising: the transistor comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, an NMOS transistor, a capacitor and a phase inverter;
the source electrode of the first PMOS transistor and the source electrode of the second PMOS transistor are both connected with the anode of a power supply, the drain electrode of the first PMOS transistor and the drain electrode of the second PMOS transistor are both connected with the source electrode of the third PMOS transistor, the grid electrode of the first PMOS transistor is connected with a reading auxiliary control signal, and the grid electrode of the second PMOS transistor is connected with a reading acceleration control signal;
the drain electrode of the third PMOS transistor, the drain electrode of the NMOS transistor, the source electrode of the fourth PMOS transistor and the positive plate of the capacitor are all connected with a word line; the grid electrode of the third PMOS transistor and the grid electrode of the NMOS transistor are both connected with an input signal; the source electrode of the NMOS transistor is connected with the ground wire of the power supply;
the drain electrode of the fourth PMOS transistor is connected with the ground wire of the power supply, and the grid electrode of the fourth PMOS transistor is connected with the reading auxiliary control signal;
and the negative plate of the capacitor is connected with the output end of the phase inverter, and the input end of the phase inverter is connected with the write auxiliary control signal.
Optionally, when performing the under-voltage reading auxiliary operation: the reading auxiliary control signal is at a low level, the reading acceleration control signal is at a high level, at the moment, the first PMOS transistor and the fourth PMOS transistor are switched on, and the second PMOS transistor is switched off.
Optionally, when the input signal is at a low level, the third PMOS transistor is turned on, the NMOS transistor is turned off, and the output voltage of the word line is an intermediate level voltage divided by the first PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor.
Optionally, when the input signal is at a high level, the third PMOS transistor is turned off, the NMOS transistor is turned on, and the output voltage of the word line is a low-level voltage pulled down by the NMOS transistor.
Optionally, when performing a read acceleration operation: the reading auxiliary control signal is at a high level, the reading acceleration control signal is at a low level, at the moment, the first PMOS transistor and the fourth PMOS transistor are disconnected, and the second PMOS transistor is connected.
Optionally, when the input signal is a low level, the third PMOS transistor is turned on, the NMOS transistor is turned off, the capacitor is charged, so that the output voltage of the word line is increased to the voltage of the power supply, then, the read acceleration control signal is set to a high level, the second PMOS transistor is turned off, and the lower plate voltage of the capacitor is raised by the write auxiliary control signal, so that the output voltage of the word line is higher than the voltage of the power supply.
Optionally, when the input signal is at a high level, the third PMOS transistor is turned off, the NMOS transistor is turned on, and the output voltage of the word line is a low-level voltage pulled down by the NMOS transistor.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention provides a sub-threshold SRAM read-write auxiliary circuit, which comprises: the transistor comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, an NMOS transistor, a capacitor and a phase inverter; the source electrode of the first PMOS transistor and the source electrode of the second PMOS transistor are both connected with the anode of a power supply, the drain electrode of the first PMOS transistor and the drain electrode of the second PMOS transistor are both connected with the source electrode of the third PMOS transistor, the grid electrode of the first PMOS transistor is connected with a reading auxiliary control signal, and the grid electrode of the second PMOS transistor is connected with a reading acceleration control signal; the drain electrode of the third PMOS transistor, the drain electrode of the NMOS transistor, the source electrode of the fourth PMOS transistor and the positive plate of the capacitor are all connected with a word line; the grid electrode of the third PMOS transistor and the grid electrode of the NMOS transistor are both connected with an input signal; the source electrode of the NMOS transistor is connected with the ground wire of the power supply; the drain electrode of the fourth PMOS transistor is connected with the ground wire of the power supply, and the grid electrode of the fourth PMOS transistor is connected with the reading auxiliary control signal; and the negative plate of the capacitor is connected with the output end of the phase inverter, and the input end of the phase inverter is connected with the write auxiliary control signal. The invention realizes the quick access of the SRAM on the premise of ensuring the reading stability. And the word line is raised by utilizing the coupling effect of the capacitor, so that the voltage of the word line is higher than the power supply voltage, and the writing assistance is realized.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a circuit diagram of a sub-threshold SRAM read/write assist circuit according to the present invention;
fig. 2 is a working schematic diagram of a sub-threshold SRAM read-write assist circuit according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a sub-threshold SRAM read-write auxiliary circuit to reduce access time and enhance write capability on the premise of ensuring read stability.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
As shown in fig. 1, the present invention discloses a sub-threshold SRAM read/write auxiliary circuit, which comprises: a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, an NMOS transistor MN1, a capacitor CAP, and an inverter INV.
The source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are both connected to the positive electrode of the power supplyVDDA drain of the first PMOS transistor MP1 and a drain of the second PMOS transistor MP2 are both connected to a source of the third PMOS transistor MP3, a gate of the first PMOS transistor MP1 is connected to a read assist control signalA(read Assist control SignalAThe waveform of (A) is V (V) in FIG. 2A) Shown), the gate of the second PMOS transistor is connected to a read acceleration control signalB(read acceleration control signal)BThe waveform of (A) is V (V) in FIG. 2B) Shown) is connected. That is, as shown in fig. 1, the gate of the first PMOS transistor MP1 is connected to the read assist control signalAFor connection to the positive pole of a power supplyVDDAnd voltage line of word lineVDDWL. The gate of the second PMOS transistor MP2 is connected with the read acceleration control signalBFor connection to the positive pole of a power supplyVDDAnd voltage line of word lineVDDWL。
The drain of the third PMOS transistor MP3, the drain of the NMOS transistor MN1, the source of the fourth PMOS transistor MP4, and the positive plate of the capacitor CAP are all connected to a word lineWLConnecting, word linesWLThe waveform of the signal on (C) is V (V) in FIG. 2WL) (ii) a The gate of the third PMOS transistor MP3 and the gate of the NMOS transistor MN1 are connected with an input signalWLnConnecting, inputting signalsWLnThe waveform of (A) is V (V) in FIG. 2WLn) (ii) a The source of the NMOS transistor MN1 is connected with the power supplyAnd the ground wire is connected. That is, as shown in fig. 1, the gate of the third PMOS transistor MP3 is connected to the input signalWLnFor connecting toVDDWLAndWL. NMOS transistor MN1 with gate connected to input signalWLnGround wire for connecting power supply andVDDWL。
the drain of the fourth PMOS transistor MP4 is connected to the ground of the power supply, and the gate of the fourth PMOS transistor MP4 is connected to the auxiliary read control signalAAnd (4) connecting. That is, as shown in FIG. 1, the gate of the fourth PMOS transistor MP4 is connected to the read assist control signalAGround line and word line for connecting power supplyWL。
The negative plate of the capacitor CAP is connected with the output end of an inverter INV, and the input end of the inverter INV is connected with a write auxiliary control signalC. An inverter INV having a write assist control signal as an inputCWrite assist control signalCWaveform of (A), as shown by V (in FIG. 2)C) And the output is connected with the lower plate of the capacitor CAP.
The working principle is as follows: as shown in FIG. 2, when an under-voltage read assist operation is performed: read assist control signalAAt low level, reading the acceleration control signalBAt a high level, i.e. read auxiliary control signalAWaveform V (V: (A) At low level, reading the acceleration control signalBWaveform V (V: (B) At high level, the first PMOS transistor MP1 and the fourth PMOS transistor MP4 are turned on, and the second PMOS transistor MP2 is turned off. When the input signal is low, i.e. the waveform V (of the input signal in FIG. 2)WLn) When the voltage level is low, the third PMOS transistor MP3 is turned on, the NMOS transistor MN1 is turned off, and the word line is turned onWLThe output voltage of (1) is an intermediate level voltage divided by the first PMOS transistor MP1, the third PMOS transistor MP3 and the fourth PMOS transistor MP4, such as the word line in FIG. 2WLWaveform V (V: (WL) As shown. When inputting a signalWLnAt a high level, i.e., waveform V (of the input signal in FIG. 2)WLn) When the voltage is high, the third PMOS transistor MP3 is turned off, the NMOS transistor MN1 is turned on, and the word line is turned onWLThe output voltage of (1) is a low level voltage pulled down by an NMOS transistor, such as a word line in FIG. 2WLWaveform V (V: (WL) As shown.
When performing a read acceleration operation: read assist controlSignalAAt high level, read the acceleration control signalBAt low level, i.e. read auxiliary control signalAWaveform V (V: (A) At high level, read the acceleration control signalBWaveform V (V: (B) At low level, the first PMOS transistor MP1 and the fourth PMOS transistor MP4 are turned off, and the second PMOS transistor MP2 is turned on. When the input signal is low, i.e. the waveform V (of the input signal in FIG. 2)WLn) When the level is low, the third PMOS transistor MP3 is turned on, the NMOS transistor MN1 is turned off, and the capacitor CAP is charged to turn on the word lineWLIs slowly increased to the voltage of the power supply, such as the word line in fig. 2WLWaveform V (V: (WL) Then, read acceleration control signal is sentBSet to high level, i.e. read acceleration control signalBWaveform V (V: (B) Set to high level, the second PMOS transistor MP2 is turned off and controlled by the write assist control signalC(write assist control signal)CThe waveform of (A) is V (V) in FIG. 2C) Raise the lower plate voltage of the capacitor CAP to make the word lineWLIs higher than the voltage of the power supply, e.g. word line in fig. 2WLWaveform V (V: (WL) As shown. When the input signal is high, i.e., the waveform V (of the input signal in FIG. 2)WLn) When the voltage is high, the third PMOS transistor MP3 is turned off, the NMOS transistor MN1 is turned on, and the word line is turned onWLThe output voltage of (1) is a low level voltage pulled down by NMOS transistor MN1, such as the word line in FIG. 2WLWaveform V (V: (WL) As shown.
The specific function of the present invention is realized as follows, in the beginning stage of the word line rising, the first PMOS transistor MP1 and the fourth PMOS transistor MP4 are turned on, and the second PMOS transistor MP2 is turned off.VDDWLByVDDThe first PMOS transistor MP1, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 form a voltage division by being powered by the first PMOS transistor MP1, and the word lineWLThe signal of (2) is quickly stabilized at the middle level, and the word line undervoltage reading assistance is realized. Subsequently, the first PMOS transistor MP1 and the fourth PMOS transistor MP4 are turned off, and the second PMOS transistor MP2 is turned on.VDDThe word line is slowly pulled by forming an RC load through the small-sized second PMOS transistor MP2 and the capacitance on the word lineWLIs charged toVDD. The second PMOS transistor MP2 is then turned off, the output of the inverter INVThe pull-up charges the lower plate of the capacitor. By using the coupling effect of the capacitor CAP, the word line is further raised to make the voltage of the word line higher than that of the word lineVDDWrite assist is implemented. On the premise of ensuring the reading stability, the SRAM is quickly accessed, and the writing capability is improved.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (7)
1. A sub-threshold SRAM read-write assist circuit, the assist circuit comprising: the transistor comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, an NMOS transistor, a capacitor and a phase inverter;
the source electrode of the first PMOS transistor and the source electrode of the second PMOS transistor are both connected with the anode of a power supply, the drain electrode of the first PMOS transistor and the drain electrode of the second PMOS transistor are both connected with the source electrode of the third PMOS transistor, the grid electrode of the first PMOS transistor is connected with a reading auxiliary control signal, and the grid electrode of the second PMOS transistor is connected with a reading acceleration control signal;
the drain electrode of the third PMOS transistor, the drain electrode of the NMOS transistor, the source electrode of the fourth PMOS transistor and the positive plate of the capacitor are all connected with a word line; the grid electrode of the third PMOS transistor and the grid electrode of the NMOS transistor are both connected with an input signal; the source electrode of the NMOS transistor is connected with the ground wire of the power supply;
the drain electrode of the fourth PMOS transistor is connected with the ground wire of the power supply, and the grid electrode of the fourth PMOS transistor is connected with the reading auxiliary control signal;
and the negative plate of the capacitor is connected with the output end of the phase inverter, and the input end of the phase inverter is connected with the write auxiliary control signal.
2. The sub-threshold SRAM read-write assist circuit of claim 1, wherein when performing an under-voltage read assist operation: the reading auxiliary control signal is at a low level, the reading acceleration control signal is at a high level, at the moment, the first PMOS transistor and the fourth PMOS transistor are switched on, and the second PMOS transistor is switched off.
3. The sub-threshold SRAM read/write assist circuit of claim 2, wherein when the input signal is low, the third PMOS transistor is turned on, the NMOS transistor is turned off, and the output voltage of the word line is an intermediate level voltage divided by the first PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor.
4. The sub-threshold SRAM read/write assist circuit of claim 2 wherein when the input signal is high, the third PMOS transistor is turned off, the NMOS transistor is turned on, and the output voltage of the word line is a low voltage pulled down by the NMOS transistor.
5. The sub-threshold SRAM read-write assist circuit of claim 1, wherein when performing a read speed-up operation: the reading auxiliary control signal is at a high level, the reading acceleration control signal is at a low level, at the moment, the first PMOS transistor and the fourth PMOS transistor are disconnected, and the second PMOS transistor is connected.
6. The sub-threshold SRAM read/write assist circuit of claim 5 wherein when the input signal is low, the third PMOS transistor is turned on and the NMOS transistor is turned off, increasing the output voltage of the word line to the voltage of the power supply by charging the capacitor, and then setting the read acceleration control signal to high, turning off the second PMOS transistor, and raising the voltage of the lower plate of the capacitor by the write assist control signal, so that the output voltage of the word line is higher than the voltage of the power supply.
7. The sub-threshold SRAM read/write assist circuit of claim 5 wherein when the input signal is high, the third PMOS transistor is turned off, the NMOS transistor is turned on, and the output voltage of the word line is a low voltage pulled down by the NMOS transistor.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113628650A (en) * | 2021-06-21 | 2021-11-09 | 杭州未名信科科技有限公司 | Static random access memory unit structure and static random access memory |
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