CN206259349U - A kind of test structure - Google Patents

Abstract

The utility model provides a kind of test structure, and the test structure includes the multiple MOS transistors set in array；The grid structure that the MOS transistor includes the SiGe source regions being formed in substrate, SiGe drain regions and is formed on the substrate and is located between the SiGe source regions and SiGe drain regions；The SiGe source regions and SiGe drain regions are drawn by the described first connection metal level, for testing SiGe integration of interface quality.Test structure of the present utility model is without destructiveness, it is possible to achieve region-wide mos transistor array SiGe integration of interface（interface integration）Quality test, obtains the electric leakage performance of device in the first connection metal level stage in time, test period can be reduced to 0.5 month by 2 months, substantially increases production efficiency.

Description

A kind of test structure

Technical field

The utility model belongs to field of semiconductor manufacture, is related to a kind of test structure.

Background technology

Cmos circuit has the advantages that low-power consumption, and the power consumption caused by leakage current under static conditions can be ignored, and only exist Transition period circuit is from the larger electric current of electrical source consumption.Supply voltage represents that Q represents static (quiescent), then with VDD IDDQ can be used to represent the electric current obtained from power supply during MOS circuit statics, and the test to this electric current is referred to as iddq test, and this is one Application prospect is planted widely to test.

The principle of iddq test is exactly leakage current when detecting that cmos circuit is static, and quiescent current is very small when circuit is normal (nA grades), and (such as gate oxide short or metal wire short circuit) if much bigger IDDQ methods measure certain if quiescent current during existing defects The electric current of one circuit is extraordinary, then mean that this circuit there may be defect.

Germanium silicon (SiGe) is widely adopted in 28nm node PMOS drawing processes.Fig. 1 is being shown as SiGe deposition interface just Often when structure chart, Fig. 2 be shown as SiGe deposition interface it is abnormal when structure chart.SiGe film deposition interface problem will be led Cause very big IDDQ.

SiGe deposition needs to use HCl, SiH₄、B₂H₆Deng reacting gas, every kind of gas is filled with steel cylinder, at one section Between be finished after need the steel cylinder that more renews, and due to every bottle of gas, all there is some difference, and influence is possible to after more renewing bottle SiGe deposition technique, this is the major reason for causing to occur SiGe film deposition interface problem.Therefore, in conventional reacting gas After HCl is changed, conventional transmission electron microscope (TEM) method is used to check SiGe film interface problem.Tem analysis are more In time, but with destructiveness, it is impossible to check most of device.The PMOS that is caused by SiGe deposition interface problem big junction leakage Stream is embodied (IDDQ exceptional values occur) in wafer level test (Final CP) before final encapsulation.But from offline TEM tests generally need to take two months to final CP tests, time-consuming more long, pinpoint the problems too late, are easily caused huge Waste.

Fig. 3-Fig. 6 is shown as existing four kinds of test structures, including active area 101, connecting pole 102 and metal 103, point Not Yong Lai test different types active area junction leakage.Wherein, test structure shown in Fig. 3 is directed to active area, is surveyed shown in Fig. 4 Examination structure be directed to fringe region, test structure shown in Fig. 5 is directed to silicon island, test structure shown in Fig. 6 be directed to shallow trench every From (STI) structure.But, these test structures are only applicable to diode in the prior art, and are not suitable for MOS transistor.

Therefore, a kind of test structure how is provided, with quick, safety inspection after changing HCl gases in SiGe deposition technique SiGe deposition interface problem is surveyed, as those skilled in the art's important technological problems urgently to be resolved hurrily.

Utility model content

The shortcoming of prior art in view of the above, the purpose of this utility model is to provide a kind of test structure, is used for Solve test period in the prior art long, it is impossible to find the problem of region-wide SiGe deposition integration of interface quality in time.

In order to achieve the above objects and other related objects, the utility model provides a kind of test structure, the test structure Including the multiple MOS transistors set in array；The MOS transistor includes the SiGe source regions, the SiGe leakages that are formed in substrate Area and the grid structure for being formed on the substrate and being located between the SiGe source regions and SiGe drain regions；The SiGe source regions And SiGe drain regions are drawn by the described first connection metal level, for testing SiGe integration of interface quality.

Alternatively, the test structure at least includes 5000 MOS transistors.

Alternatively, the Substrate bias, the grid structure floating, the SiGe source regions are connected with the SiGe drain regions, Leakage current for testing MOS transistor using two hold-carryings.

Alternatively, the SiGe source regions, SiGe drain regions, grid structure and substrate are drawn by the first connection metal level, For carrying out MOS transistor test using four-end method.

Alternatively, the SiGe source regions and SiGe drain regions are connected metal level with described first and are connected by conductive pole.

Alternatively, the test structure is arranged at the Cutting Road region of wafer.

Alternatively, the grid structure includes polysilicon gate and is formed at the side wall knot of the polysilicon gate both sides Structure.

Alternatively, the substrate is Si substrates or Ge substrates.

Alternatively, in the multiple MOS transistors in array setting, shallow ridges is passed through between adjacent rows MOS transistor Recess isolating structure is isolated, positioned at the MOS transistor common grid structure of same row.

As described above, test structure of the present utility model, has the advantages that：Test structure of the present utility model is not With destructiveness, it is possible to achieve region-wide mos transistor array SiGe integration of interface (interface integration) matter Examination is measured, the electric leakage performance of device is obtained in the first connection metal level stage in time, test period can be reduced to by 2 months 0.5 month, substantially increase production efficiency.Test structure of the present utility model uses different test modes.One kind is to use Four-end method (4pin) carries out conventional MOS tests, and source electrode, drain electrode, grid, the substrate of MOS transistor are by the first connection gold Category layer (M1) is drawn, and test event includes linear threshold voltage (Vtlin), linear leakage current (Idlin), saturated drain-source current (Idsat), drain electrode cut-off current (Idoff), master curve (universal curve) etc..If SiGe film is not substantially grown, Then Idlin/Vtlin and master curve can substantially drift about relative to a reference value (BL).Another kind is using using the test of two hold-carryings Junction leakage, MOS transistor source electrode is connected metal level (M1) and draws with drain electrode by first, if SiGe film is not substantially grown Good, then the leakage current of transistor is compared with a reference value (BL), can substantially increase 1~2 order of magnitude.Wherein, second group of test be more It is sensitivity.

Brief description of the drawings

Structure chart when Fig. 1 is shown as that SiGe deposition interface is normal in the prior art.

Fig. 2 be shown as SiGe deposition interface it is abnormal when structure chart.

Fig. 3-Fig. 6 is shown as four kinds of schematic diagrames of test structure in the prior art.

Fig. 7 is shown as the plane figure of test structure of the present utility model.

Fig. 8 is shown as the cross-sectional view of MOS transistor in test structure of the present utility model.

Component label instructions

101 active areas

102 connecting poles

103 metals

201 SiGe source regions

202 SiGe drain regions

203 grid structures

204 conductive poles

205 substrates

Specific embodiment

Implementation method of the present utility model is illustrated by particular specific embodiment below, those skilled in the art can be by this Content disclosed by specification understands other advantages of the present utility model and effect easily.

Refer to Fig. 7 to Fig. 8.It should be clear that structure, ratio, size depicted in this specification institute accompanying drawings etc., is only used to Coordinate the content disclosed in specification, so that those skilled in the art understands and reads, be not limited to the utility model Enforceable qualifications, therefore do not have technical essential meaning, the modification of any structure, the change of proportionate relationship or size Adjustment, in the effect for not influenceing the utility model can be generated and under the purpose to be reached, all should still fall in the utility model In the range of disclosed technology contents are obtained and can covered.Meanwhile, in this specification it is cited as " on ", D score, " left side ", The term on " right side ", " centre " and " one " etc., is merely convenient to understanding for narration, and it is enforceable to be not used to restriction the utility model Scope, being altered or modified for its relativeness is enforceable when the utility model is also considered as under without essence change technology contents Category.

The utility model provides a kind of test structure, refers to Fig. 7, is shown as the plane figure of the test structure, wraps Include the multiple MOS transistors set in array.Fig. 8 is referred to, the cross-sectional view of the MOS transistor is shown as.Institute Stating MOS transistor includes the SiGe source regions 201 being formed in substrate 205, SiGe drain regions 202 and is formed at the substrate 205 The upper and grid structure 203 between the SiGe source regions 201 and SiGe drain regions 202；The SiGe source regions 201 and SiGe leak Drawn for testing by the first connection metal level (M1) in area 202.

Specifically, the substrate 20 includes but is not limited to the conventional semiconductor substrates such as Si substrates, Ge substrates.The substrate 20 In be provided with well region, the SiGe source regions 201 are with SiGe drain regions 202 in well region.The SiGe source regions 201 and SiGe drain regions 202 are connected metal level (M1) with described first by conductive pole 204 is connected.

Specifically, the grid structure 203 includes polysilicon gate and is formed at the side wall of the polysilicon gate both sides Structure.In the present embodiment, in the multiple MOS transistors in array setting, shallow ridges is passed through between adjacent rows MOS transistor Recess isolating structure is isolated, positioned at the MOS transistor common grid structure of same row.

Specifically, the test structure at least includes 5000 MOS transistors.MOS transistor quantity is more, and signal is brighter It is aobvious, it is more beneficial for the reading of signal.

The application method of test structure of the present utility model is as follows：

As an example, setting two sets of test structures in the Cutting Road region of wafer.

For first set test structure, the SiGe source regions 201, SiGe drain regions 202, grid structure 203 and substrate 205 are equal Drawn by the described first connection metal level (M1), for carrying out conventional MOS transistor test using four-end method.Test event Including linear threshold voltage (Vtlin), linear leakage current (Idlin), saturated drain-source current (Idsat), drain electrode cut-off current (Idoff), master curve (universal curve) etc..If SiGe film is not substantially grown, Idlin/Vtlin and general Curve can substantially drift about relative to a reference value (BL).

For second set of test structure, the substrate 205 is biased into (or for well region is biased), the grid structure 203 Floating, the SiGe source regions 201 are connected with the SiGe drain regions 202, in order to test the electric leakage of MOS transistor using two hold-carryings Stream.If SiGe film is not substantially grown, the leakage current of transistor is compared with a reference value (BL), can substantially increase 1~2 quantity Level.Relative to first set test structure, second set of test structure is more sensitive.

In sum, test structure of the present utility model is without destructiveness, it is possible to achieve region-wide MOS transistor battle array Row SiGe integration of interface (interface integration) quality test, obtains device in the first connection metal level stage in time , test period, by 2 months can be reduced to 0.5 month by the electric leakage performance of part, substantially increase production efficiency.So, this reality Effectively overcome various shortcoming of the prior art and had high industrial utilization with new.

Above-described embodiment only illustrative principle of the present utility model and its effect are new not for this practicality is limited Type.Any person skilled in the art can all be carried out under without prejudice to spirit and scope of the present utility model to above-described embodiment Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the essence disclosed in the utility model All equivalent modifications completed under god and technological thought or change, should be covered by claim of the present utility model.

Claims (9)

1. a kind of test structure, it is characterised in that：The test structure includes the multiple MOS transistors set in array；It is described MOS transistor includes the SiGe source regions being formed in substrate, SiGe drain regions and is formed on the substrate and is located at described Grid structure between SiGe source regions and SiGe drain regions；The SiGe source regions and SiGe drain regions are drawn by the first connection metal level Go out, for testing SiGe integration of interface quality.

2. test structure according to claim 1, it is characterised in that：The test structure at least includes 5000 MOS crystalline substances Body pipe.

3. test structure according to claim 1, it is characterised in that：The Substrate bias, the grid structure floating, institute State SiGe source regions to be connected with the SiGe drain regions, the leakage current for testing MOS transistor using two hold-carryings.

4. test structure according to claim 1, it is characterised in that：The SiGe source regions, SiGe drain regions, grid structure and Substrate is drawn by the described first connection metal level, for carrying out MOS transistor test using four-end method.

5. test structure according to claim 1, it is characterised in that：The SiGe source regions and SiGe drain regions are by conduction Post is connected metal level with described first and is connected.

6. test structure according to claim 1, it is characterised in that：The test structure is arranged at the Cutting Road area of wafer Domain.

7. test structure according to claim 1, it is characterised in that：The grid structure includes polysilicon gate and formation In the sidewall structure of the polysilicon gate both sides.

8. test structure according to claim 1, it is characterised in that：The substrate is Si substrates or Ge substrates.

9. test structure according to claim 1, it is characterised in that：In multiple MOS transistors in array setting, Isolated by fleet plough groove isolation structure between adjacent rows MOS transistor, positioned at the MOS transistor common grid knot of same row Structure.