CN208422914U - Thermal-shutdown circuit - Google Patents
Thermal-shutdown circuit Download PDFInfo
- Publication number
- CN208422914U CN208422914U CN201820067872.3U CN201820067872U CN208422914U CN 208422914 U CN208422914 U CN 208422914U CN 201820067872 U CN201820067872 U CN 201820067872U CN 208422914 U CN208422914 U CN 208422914U
- Authority
- CN
- China
- Prior art keywords
- temperature
- thermal
- shutdown circuit
- comparator
- current source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The utility model provides a kind of thermal-shutdown circuit, comprising: provides the current source of constant-current source；Detect the temperature sampling pipe of temperature；The comparator of temperature detection signal is generated based on the temperature detected；The control signal generation unit of temperature control signals is generated based on temperature detection signal；The metal-oxide-semiconductor field effect transistor of overheat protector is realized by shutdown or conducting based on temperature control signals.The temperature sampling device of the utility model can collect real time temperature in time and accurately, and thermal-shutdown circuit is made effectively to work, and without considering the error in heat conductive process, simplify thermal Protection Circuit Design；Simultaneously; semiconductor devices and control module are integrated in an encapsulating package by the way of closing envelope; a thermal-shutdown circuit is formed, the chip based on different process is organically combined together, monolithic is avoided the occurrence of and realizes said function bring process complexity and high cost.
Description
Technical field
The utility model relates to field of semiconductor manufacture, more particularly to a kind of thermal-shutdown circuit.
Background technique
It is as shown in Figure 1 the structural schematic diagram of existing large power supply managing chip 1, wherein integrated circuit 11 is as control
Circuit processed is set in a chip, including control module 112；Power device 12 is set in another chip, including power switch
Pipe 121；The two is integrated in an encapsulating package.Large power supply managing chip is larger due to generating heat, in order to preferably protect
Excessively high heat is burnt when chip is not worked, and usual built-in temperature Sampling device 111 is to cooperate the control module 112 to realize
Overheat protector, and existing temperature sampling device 111 is generally positioned in the integrated circuit 11.
Integrated circuit 11 and power device 12 generate heat using encapsulation technique one power management integrated chip of formation is closed
Heat source is on the PN junction of power switch tube 121, but temperature sampling device is set on integrated circuit 11, therefore, power switch tube
The heat generated on 121 is needed to be transmitted to by encapsulating material in integrated circuit 11 and is perceived by temperature sampling device 111, by
In the pyroconductivity (heat directly conducted under the unit temperature difference and in the unit time of material of unit section, length of encapsulating material
Amount) it is bad, heat cannot be timely and be accurately collected by temperature sampling device 111.This is easy to cause control module 112 to generate
Error, in the case where power switch tube 121 has needed overheat protector or has removed overheat protector, temperature sampling device 111
Temperature does not still reach turn threshold；Under extreme case, in the case that the PN junction overheat of power switch tube 121 is burnt, due to
Encapsulating material heat transfer is bad, and the temperature of temperature sampling device 111 does not still rise to or drop to turn threshold, leads to electricity
Source control chip makes physical damages or is unable to rearming, so that overheat protector cannot play due effect at all.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of thermal-shutdown circuit,
For solving the problems, such as that thermal-shutdown circuit heat sensitivity is poor in the prior art.
In order to achieve the above objects and other related objects, the utility model provides a kind of semiconductor devices, the semiconductor
Device includes at least:
The metal-oxide-semiconductor field effect transistor and temperature sampling pipe being formed in same semi-conductive substrate.
Preferably, the temperature sampling pipe is diode or the triode that base collector is shorted.
In order to achieve the above objects and other related objects, the utility model also provides a kind of thermal-shutdown circuit, the mistake
Temperature protection circuit includes at least:
Above-mentioned semiconductor device, current source, comparator and control signal generation unit；
One end connection supply voltage, the other end of the current source are grounded after the temperature sampling pipe, to provide perseverance
Stream source；
The input terminal of the comparator is separately connected the output end and a reference voltage of the current source, to generate temperature inspection
Survey signal；
The control signal generation unit receives the temperature detection signal of the comparator output, and is examined based on the temperature
It surveys signal and generates temperature control signals；
The drain terminal of the metal-oxide-semiconductor field effect transistor connects the temperature control signals, source ground connection as output end, grid end, by
The temperature control signals control shutdown or conducting, to realize overheat protector.
Preferably, the current source, the comparator and the control signal generation unit are set to as control module
With in semi-conductive substrate.
It is highly preferred that the semiconductor devices and the control module are integrated in an encapsulating package in a manner of envelope by closing.
It is highly preferred that the semiconductor devices is fixed on the first packaging frame Ji Dao by way of load glue or eutectic weldering
On, the control module is fixed on the second packaging frame Ji Dao by way of load glue or eutectic weldering, the semiconductor devices
It is electrically connected between the control module by encapsulation bonding wire realization.
Preferably, the temperature sampling pipe is diode, and the anode of the diode connects the comparator, cathode connects
Ground.
Preferably, the temperature sampling pipe is triode, and the emitter of the triode connects the comparator, collector
And base earth.
It is highly preferred that the inverting input terminal of the comparator connects the connection section of the current source Yu the temperature sampling pipe
Point, normal phase input end connect the reference voltage.
As described above, the thermal-shutdown circuit of the utility model, has the advantages that
1, temperature sampling device and power switch tube are made on same substrate, the collected temperature of temperature sampling device
The temperature that the power switch tube exactly generated heat generates, can collect real time temperature in time and accurately, make thermal-shutdown circuit
Effectively work, without considering the error in heat conductive process, simplifies thermal Protection Circuit Design.
2, semiconductor devices and control module are integrated in an encapsulating package by the way of closing envelope, forms a mistake
Temperature protection circuit, the chip based on different process is organically combined together, and is avoided the occurrence of monolithic and is realized that said function is brought
Process complexity and high cost.
Detailed description of the invention
Fig. 1 is shown as the structural schematic diagram of large power supply managing chip in the prior art.
Fig. 2 is shown as the structural schematic diagram of the thermal-shutdown circuit of the utility model.
Fig. 3 is shown as the schematic layout pattern of the semiconductor devices of the utility model.
Fig. 4 is shown as the encapsulation schematic diagram of the semiconductor devices of the utility model.
Fig. 5 is shown as the working principle diagram of the thermal-shutdown circuit of the utility model.
Fig. 6 is shown as the schematic cross-sectional view of the semiconductor devices of the utility model.
Component label instructions
1 power management chip
11 integrated circuits
111 temperature sampling devices
112 control modules
12 power devices
121 power switch tubes
2 thermal-shutdown circuits
21 semiconductor devices
211 metal-oxide-semiconductor field effect transistors
212 temperature sampling pipes
213 terminal areas
214 substrates
214a epitaxial layer
214b metal layer
215 oxygen layer
216 grid oxide layers
217 N-type polycrystal layers
218 p-type polycrystal layers
22 control modules
221 current sources
222 comparators
223 control signal generation units
31 first packaging frame Ji Dao
32 second packaging frame Ji Dao
4 load glue
5 encapsulation bonding wires
6 pins
S1~S6 step
Specific embodiment
Illustrate the embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different specific embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer
With carrying out various modifications or alterations under the spirit without departing from the utility model.
Please refer to Fig. 2~Fig. 6.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model is only shown with related component in the utility model rather than when according to actual implementation in schema then
Component count, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind
Become, and its assembly layout kenel may also be increasingly complex.
As shown in Fig. 2, the utility model provides a kind of thermal-shutdown circuit 2, the thermal-shutdown circuit 2 includes:
Semiconductor devices 21 and control module 22；The semiconductor devices 21 includes metal-oxide-semiconductor field effect transistor 211 and temperature sampling
Pipe 212；The control module 22 includes current source 221, comparator 222 and control signal generation unit 223.
As shown in Fig. 2, one end connection supply voltage VDD, the other end of the current source 221 pass through the temperature sampling pipe
It is grounded after 212, to provide constant-current source.
Specifically, in the present embodiment, the temperature sampling pipe 212 is diode, and the anode of the diode connects institute
State input terminal (being in the present embodiment inverting input terminal), the minus earth VSS of comparator 222.In practical applications, the temperature
Degree sampling pipe 212 may be configured as triode (not shown), and the emitter of the triode connects the defeated of the comparator 222
Enter end, collector and base stage and be shorted ground VSS, the device of any achievable temperature detection is suitable for the utility model, not with this
Embodiment is limited.
As shown in Fig. 2, the input terminal of the comparator 222 is separately connected output end and a reference for the current source 221
Voltage Vref, to generate temperature detection signal.
Specifically, in the present embodiment, the inverting input terminal of the comparator 222 connect the current source 221 with it is described
The connecting node of temperature sampling pipe 212, normal phase input end connect the reference voltage Vref.In practical applications, the comparison
The polarity of the input terminal of device 222 is interchangeable, can realize identical logic function by increasing phase inverter, not be with the present embodiment
Limit.
As shown in Fig. 2, the control signal generation unit 223 receives the temperature detection signal that the comparator 222 exports,
And temperature control signals are generated based on the temperature detection signal.
As shown in Fig. 2, the drain terminal of the metal-oxide-semiconductor field effect transistor 211 connects the temperature control letter as output end SW, grid end
Number, source ground connection, by the temperature control signals control shutdown or be connected, to realize overheat protector.
It should be noted that in the present embodiment, the metal-oxide-semiconductor field effect transistor 211 and the temperature sampling pipe 212 are formed in
With in semi-conductive substrate, the current source 221, the comparator 222 and the control signal generation unit 223 are formed in separately
In semi-conductive substrate, to realize the accuracy and sensitivity of temperature detection.
It is illustrated in figure 3 the topological chip plan of the semiconductor devices 21, S is that the source of the metal-oxide-semiconductor field effect transistor 211 is welded
Disk, G are the grid end pad of the metal-oxide-semiconductor field effect transistor 211, and T is the positive terminal pad of the diode.
Specifically, the metal-oxide-semiconductor field effect transistor 211 is prepared on same substrate with the diode, when the MOS field-effect
Pipe 211 generates heat, and the diode can collect real time temperature in time and accurately, and the sensitivity of the thermal-shutdown circuit 2 is big
It is big to improve.
It should be noted that in the present embodiment, the semiconductor devices 21 and the control module 22 are to close in a manner of envelope
It is integrated in an encapsulating package.
Specifically, as shown in figure 4, the semiconductor devices 21 is fixed on the first encapsulation by load glue 4 (or eutectic weldering)
On frame base island 31, the control module 22 is fixed on the second packaging frame base island 32 by load glue 4 (or eutectic weldering), institute
State between semiconductor devices 21 and the control module 22 by encapsulation bonding wire 5 realization be electrically connected, the semiconductor devices 21 and
The external-connected port of the control module 22 draws the encapsulating package by pin 6.Dotted portion illustrates heat from institute in Fig. 4
It states on semiconductor devices 21 to the conducting path of temperature sampling pipe 212, it is seen then that heat conduction path substantially reduces.
As shown in figure 5, the working principle of the thermal-shutdown circuit 2 is as follows:
Under normal circumstances, (current potential or diode of transistor emitter are just for the current potential on the temperature sampling pipe 212
Electrode potential) it is higher than the reference voltage Vref, the comparator 222 exports low level, and chip works normally.
When the temperature increases, due to the section voltage of temperature sampling pipe 212 (voltage of transistor emitter to base stage or two poles
The junction voltage of pipe) there is negative temperature coefficient, the current potential on the temperature sampling pipe 212 can reduce, when temperature is more than turn threshold
When TH, the anti-phase input terminal potential of the comparator 222 is lower than the reference voltage Vref, and the comparator 222 exports
High level is burnt to turn off the metal-oxide-semiconductor field effect transistor 211 by the control signal generation unit 223 to avoid chip
It ruins.
Upon a drop in temperature, temperature is lower than turn threshold TL, and the anti-phase input terminal potential of the comparator 222 is higher than described
Reference voltage Vref, the comparator 222 export low level, to reopen the metal-oxide-semiconductor field effect transistor 211, chip is again
Work.
The thermal-shutdown circuit 2 is set with sluggish temperature, so that temperature turn threshold TH > TL, sets sluggish effect
Be preventing the metal-oxide-semiconductor field effect transistor 211 overturning point near be frequently switched on and off, cause chip cisco unity malfunction or
Damage.
As shown in fig. 6, the preparation method of the semiconductor devices 21, the specific steps are as follows:
Step S1: providing a substrate 214, injects in carrying out terminal on the substrate 214 to form terminal area 213.
Specifically, as shown in fig. 6, in the present embodiment, the conduction type of the substrate 214 is n-type doping, the substrate
Epitaxial layer 214a is formed on 214, the conduction type of the epitaxial layer 214a is n-type doping, and doping concentration is less than the lining
The doping concentration at bottom 214.Oxidation processes are carried out in the surface of the epitaxial layer 214a, terminal photoetching is then carried out, passes through ion
Injection forms the terminal area 213, and as shown in Figure 3 and Figure 6, the terminal area 213 is a cyclic structure.
Step S2: field oxygen layer 215 is formed in the surface epitaxial layer 214a that the terminal area 213 surrounds, with temperature
The position of sampling pipe 212.Grid oxide layer 216 is formed in the surface epitaxial layer 214a that the terminal area 213 surrounds, to determine MOS
The position of field-effect tube 211.
Specifically, as shown in fig. 6, in the present embodiment, growing the field oxygen layer 215 first, active area light is then carried out
It carves and grows the grid oxide layer 216.The thickness of the field oxygen layer 215 is greater than the thickness of the grid oxide layer 216.
Step S3: polycrystal layer is formed in the surface of the field oxygen layer 215 and the grid oxide layer 216.
Specifically, as shown in fig. 6, passing through polycrystalline photoetching and polycrystalline in the body structure surface deposit polycrystalline layer that step S2 is formed
It etches and is respectively formed polycrystal layer (217 and 218) in the surface of the field oxygen layer 215 and the grid oxide layer 216.
Step S4: carrying out the injection of body area in the epitaxial layer 214a of 216 down either side of grid oxide layer, forms body area P-
body。
Specifically, as shown in fig. 6, carrying out the photoetching of body area, the body area P-body is formed by ion implanting, in this implementation
In example, the body area P-body is adulterated using p-type.
Step S5: forming diode in the polycrystal layer in the field oxygen layer 215, in 216 down either side of grid oxide layer
Body area P-body in formed source region N+, in the body area P-body formed body contact zone P+.
Specifically, as shown in fig. 6, passing through N+ photoetching for part polycrystal layer, the grid oxide layer 216 in the field oxygen layer 215
On the part body area P-body of 216 down either side of polycrystal layer and the grid oxide layer expose, ion note is carried out to the part of exposing
Enter, in the present embodiment, using n-type doping.In formation N-type polycrystal layer 217 in the field oxygen layer 215；In the grid oxide layer 216
Upper formation N-type polycrystal layer 217, the grid oxide layer 216 form the metal-oxide-semiconductor field effect transistor with the N-type polycrystal layer 217 above it
211 grid end structure；Source region N+ is formed in the body area P-body of 216 down either side of grid oxide layer.Pass through contact hole photoetching
And contact hole etching forms contact hole, and p-type polycrystal layer is formed in the polycrystal layer in the field oxygen layer 215 using ion implanting
218, the p-type polycrystal layer 218 forms PN junction (diode) in the N-type polycrystal layer 217；Using ion implanting in the body area
Body contact zone P+ is formed in P-body, in the present embodiment, the doping concentration of the body contact zone P+ is greater than the body area P-
The doping concentration of body.In the present embodiment, injected using the N-type injection of the source region N+ and the p-type of the body contact zone P+,
While not increasing technique level, a polycrystalline diode is manufactured in the semiconductor devices 21.
Step S6: source contact, grid contact are formed in the upper layer of step S5 resulting structures, in the back side shape of the substrate 214
At drain contact, to form the semiconductor devices.
Specifically, source contact is formed using Metal deposition, metal lithographic, metal etch and grid contacts, and in each contact jaw
Between deposit passivation layer, pass through passivation layer photoetching and passivation layer etching realize insulated barriers；And gold is formed in described 214 back side
Belong to layer 214b, and then realizes drain contact.
In conclusion the utility model provides a kind of thermal-shutdown circuit, comprising: provide the current source of constant-current source；Detection
The temperature sampling pipe of temperature；The comparator of temperature detection signal is generated based on the temperature detected；It is produced based on temperature detection signal
The control signal generation unit of raw temperature control signals；Overheat protector is realized by shutdown or conducting based on temperature control signals
Metal-oxide-semiconductor field effect transistor.Temperature sampling device and power switch tube are made in same substrate by the thermal-shutdown circuit of the utility model
On, the collected temperature of temperature sampling device is exactly the temperature that the power switch tube generated heat generates, and can be adopted in time and accurately
Collect real time temperature, thermal-shutdown circuit is made effectively to work, without considering the error in heat conductive process, simplifies excess temperature guarantor
Protection circuit design；Meanwhile being integrated semiconductor devices and control module in an encapsulating package by the way of closing envelope, it is formed
One thermal-shutdown circuit, the chip based on different process is organically combined together, and is avoided the occurrence of monolithic and is realized same function
It can bring process complexity and high cost.So the utility model effectively overcomes various shortcoming in the prior art and has
High industrial utilization value.
The above embodiments are only illustrative of the principle and efficacy of the utility model, and not for limitation, this is practical new
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
All equivalent modifications or change completed under mind and technical idea, should be covered by the claim of the utility model.
Claims (7)
1. a kind of thermal-shutdown circuit, which is characterized in that the thermal-shutdown circuit includes at least:
Semiconductor devices, current source, comparator and control signal generation unit；
The semiconductor devices includes the metal-oxide-semiconductor field effect transistor being formed in same semi-conductive substrate and temperature sampling pipe；
One end connection supply voltage, the other end of the current source are grounded after the temperature sampling pipe, to provide constant-current source；
The input terminal of the comparator is separately connected the output end and a reference voltage of the current source, to generate temperature detection letter
Number；
The control signal generation unit receives the temperature detection signal of the comparator output, and is believed based on the temperature detection
Number generate temperature control signals；
The drain terminal of the metal-oxide-semiconductor field effect transistor connects the temperature control signals, source ground connection as output end, grid end, by described
Temperature control signals control shutdown or conducting, to realize overheat protector.
2. thermal-shutdown circuit according to claim 1, it is characterised in that: the current source, the comparator and described
Control signal generation unit is set in same semi-conductive substrate as control module.
3. thermal-shutdown circuit according to claim 2, it is characterised in that: the semiconductor devices and the control module
It is integrated in an encapsulating package in a manner of envelope by closing.
4. thermal-shutdown circuit according to claim 3, it is characterised in that: the semiconductor devices is by load glue or altogether
Brilliant weldering mode is fixed on the first packaging frame Ji Dao, and the control module is fixed on second by way of load glue or eutectic weldering
On packaging frame Ji Dao, it is electrically connected between the semiconductor devices and the control module by encapsulation bonding wire realization.
5. thermal-shutdown circuit according to claim 1, it is characterised in that: the temperature sampling pipe is diode, described
The anode of diode connects the comparator, minus earth.
6. thermal-shutdown circuit according to claim 1, it is characterised in that: the temperature sampling pipe is triode, described
The emitter of triode connects the comparator, collector and base earth.
7. thermal-shutdown circuit described according to claim 1 or 5 or 6, it is characterised in that: the inverting input terminal of the comparator
It connects the current source and connect the reference voltage with the connecting node of the temperature sampling pipe, normal phase input end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820067872.3U CN208422914U (en) | 2018-01-16 | 2018-01-16 | Thermal-shutdown circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820067872.3U CN208422914U (en) | 2018-01-16 | 2018-01-16 | Thermal-shutdown circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208422914U true CN208422914U (en) | 2019-01-22 |
Family
ID=65119529
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820067872.3U Active CN208422914U (en) | 2018-01-16 | 2018-01-16 | Thermal-shutdown circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208422914U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111352454A (en) * | 2020-03-16 | 2020-06-30 | 深圳市创新微源半导体有限公司 | Constant temperature loop circuit for switch type current source chip |
| CN112653216A (en) * | 2020-12-18 | 2021-04-13 | 苏州赛芯电子科技股份有限公司 | Battery protection circuit |
| CN117134757A (en) * | 2023-10-25 | 2023-11-28 | 晶艺半导体有限公司 | Semiconductor sealing device and over-temperature protection circuit and method thereof |
-
2018
- 2018-01-16 CN CN201820067872.3U patent/CN208422914U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111352454A (en) * | 2020-03-16 | 2020-06-30 | 深圳市创新微源半导体有限公司 | Constant temperature loop circuit for switch type current source chip |
| CN112653216A (en) * | 2020-12-18 | 2021-04-13 | 苏州赛芯电子科技股份有限公司 | Battery protection circuit |
| CN117134757A (en) * | 2023-10-25 | 2023-11-28 | 晶艺半导体有限公司 | Semiconductor sealing device and over-temperature protection circuit and method thereof |
| CN117134757B (en) * | 2023-10-25 | 2024-01-19 | 晶艺半导体有限公司 | Semiconductor sealing device and over-temperature protection circuit and method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN208422914U (en) | Thermal-shutdown circuit | |
| CN102569297B (en) | Monolithic IGBT and diode structure and method for preparing quasi-resonant converter | |
| CN103413824A (en) | RC-LIGBT device and manufacturing method thereof | |
| CN100492642C (en) | Production method of metal-oxide-semiconductor field effect transistor protection circuit | |
| CN102916042B (en) | Reverse conducting IGBT device structure and manufacturing method | |
| CN112086524A (en) | Infrared detection device and preparation method | |
| CN108109999A (en) | Thermal-shutdown circuit, semiconductor devices and preparation method thereof | |
| CN107994009A (en) | A kind of SiCMOSFET devices of integrated temperature inductor | |
| CN204348725U (en) | The low capacitor transient stage voltage suppressor device of a kind of single channel | |
| CN105720100A (en) | Power semiconductor element and manufacturing method thereof | |
| CN109087944B (en) | RC-IGBT (resistor-capacitor-insulated gate bipolar transistor) integrated with MOS (metal oxide semiconductor) current sampling structure | |
| CN201804874U (en) | MOS (metal oxide semiconductor) field effect transistor with diode protective circuit | |
| CN111430305B (en) | Method for manufacturing electrostatic discharge protection device and electrostatic discharge protection device | |
| US7615396B1 (en) | Photodiode stack for photo MOS relay using junction isolation technology | |
| CN111430468B (en) | Dual-core isolation structure of dual-cell packaged Schottky diode chip and manufacturing method | |
| CN102842611A (en) | Five-mask insulated gate bipolar transistor (IGBT) chip and manufacturing method thereof | |
| US20120205756A1 (en) | Semiconductor device and method of testing the same | |
| TW201347142A (en) | Semiconductor arrangement for a current sensor in a power semiconductor | |
| CN107359125A (en) | A kind of method and device for optimizing body diode reverse recovery characteristics | |
| CN103887303B (en) | Signal IO protection device with reference to single supply and forming method thereof | |
| CN207250502U (en) | The silicon carbide substrates and gallium nitride substrate semiconductor device of Series Package | |
| CN102931228B (en) | Reverse conducting IGBT device and manufacturing method thereof | |
| US20070222017A1 (en) | Photodetector arrangement, measurement arrangement with a photodetector arrangement and process for operating a measurement arrangement | |
| CN206685391U (en) | Power semiconductor | |
| CN102315217A (en) | Multi-finger strip-type gate-ground N-channel metal oxide semiconductor (GGNMOS) and electrostatic protection circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |